Electronic packaging module and manufacturing method thereof

Abstract

The invention provides an electronic packaging module and a manufacturing method thereof. The electronic packaging module comprises a circuit substrate, an electronic element located on the circuit substrate and a sealing material, wherein the sealing material wraps the circuit substrate and the electronic element. The circuit substrate comprises a first circuit layer and a first insulating layer covering the first circuit layer, wherein the first insulating layer is provided with an interface. The second circuit layer is arranged on the interface, and the second insulating layer partially covers the second circuit layer. The second insulating layer exposes an area around the interface, and the sealing material is in direct contact with the area and the second insulating layer, so that the circuit substrate is prevented from being damaged due to direct contact with the cutting device.

Description

Technical Field

[0001] The invention relates to an electronic packaging module, in particular to an electronic packaging module with a redistribution layer. Background Art

[0002] As electronic devices are becoming thinner and lighter, it is necessary to add signal input and output (I / O) components in a limited space. Therefore, redistribution layer (RDL) packaging technology has been developed. However, during the single-body cutting process of the package, the RDL substrate is prone to damage, such as cracks on the edge of the cutting surface, and the ultra-thin RDL substrate is more serious.

[0003] On the other hand, the adhesion between these ultra-thin redistribution layer substrates and the molding compound is insufficient, which also causes the structural strength of the packaging module to be insufficient. All of the above factors affect the yield of the redistribution layer packaging, thereby reducing the reliability of electronic products using this technology. Summary of the invention

[0004] Therefore, an embodiment of the present invention provides a method for manufacturing an electronic packaging module with improved yield and an electronic packaging module manufactured by the method.

[0005] An electronic packaging module provided in one embodiment of the present invention includes a circuit substrate, which includes a first circuit layer; a first insulating layer covering the first circuit layer and having a first interface; a second circuit layer located on the first interface of the first insulating layer and electrically connected to the first circuit layer; a second insulating layer located on the first interface and partially covering the second circuit layer, wherein the second insulating layer exposes a first area of ​​the first interface, and the first area is located around the first interface; an electronic component located on the circuit substrate and electrically connected to the circuit substrate; and a sealing material covering the circuit substrate and the electronic component, wherein the sealing material directly contacts the first area of ​​the first interface and the second insulating layer.

[0006] In an embodiment of the present invention, the second insulating layer further includes a plurality of grooves, wherein the sealing material directly contacts inner surfaces of the grooves, and the grooves do not overlap with the first region of the first interface.

[0007] In one embodiment of the present invention, the inner surface of the groove includes a portion of the first interface.

[0008] In an embodiment of the present invention, the electronic component overlaps with the second region of the first interface, and at least one of the grooves is located between the second region and the first region.

[0009] In an embodiment of the present invention, the electronic component covers at least one of the grooves.

[0010] In one embodiment of the present invention, the electronic packaging module further comprises a plurality of welding materials electrically connecting the electronic element and the second circuit layer, and the welding materials overlap with a plurality of third regions of the first interface, wherein at least one of the grooves is located between two adjacent third regions.

[0011] In one embodiment of the present invention, the electronic packaging module further includes a third circuit layer, which is located on the second interface of the second insulating layer and is electrically connected to the second circuit layer. The first interface and the second interface are respectively located on opposite sides of the second insulating layer. The electronic packaging module further includes a third insulating layer, which is located on the second interface and partially covers the third circuit layer. The third insulating layer exposes a second area of ​​the second interface, the second area is located at the periphery of the second interface, and the sealing material directly contacts the second area.

[0012] In an embodiment of the present invention, the sealing material covers the sidewalls of the first insulating layer.

[0013] A manufacturing method for an electronic packaging module provided in one embodiment of the present invention includes providing a temporary carrier board; forming a circuit substrate on the temporary carrier board and exposing the surface of the temporary carrier board; setting electronic components on the circuit substrate and electrically connecting the electronic components to the circuit substrate; setting a sealing material on the temporary carrier board to cover the circuit substrate and the electronic components, wherein the sealing material covers the surface of the temporary carrier board; after setting the sealing material, removing the temporary carrier board; and after removing the temporary carrier board, cutting the sealing material; wherein the circuit substrate includes a recessed area, and the recessed area is formed around the side wall of the circuit substrate, and the sealing material fills the recessed area.

[0014] In one embodiment of the present invention, a method for forming a circuit substrate on a temporary carrier board includes forming a first circuit layer on the temporary carrier board; disposing a first insulating material on the first circuit layer so that the first insulating material covers the temporary carrier board and the first circuit layer; patterning the first insulating material to form a first insulating layer, and the first insulating layer exposes the surface of the temporary carrier board; forming a second circuit layer on the first insulating layer, wherein the second circuit layer is electrically connected to the first circuit layer; disposing a second insulating material on the second circuit layer so that the second insulating material covers the first insulating layer and the second circuit layer; patterning the second insulating material to form a second insulating layer, wherein the interface of the first insulating layer is located between the first insulating layer and the second insulating layer, and the second insulating layer exposes a portion of this interface to form a recessed area of ​​the circuit substrate.

[0015] In one embodiment of the present invention, the side wall of the circuit substrate is located on the second insulating layer, and the recessed area is formed around the side wall.

[0016] In one embodiment of the present invention, the method for manufacturing the electronic packaging module further includes forming a surface treatment layer on the first circuit layer after removing the temporary carrier plate.

[0017] In one embodiment of the present invention, the manufacturing method of the electronic packaging module further includes electrically connecting the electronic component and the second circuit layer with a plurality of welding materials, wherein the second insulating layer further exposes a portion of the interface to form a plurality of grooves, and the grooves are separated from the welding materials and the recessed area.

[0018] Based on the above, the sealing material of the present invention covers the side walls of the circuit substrate. In this way, during the individual cutting process, the sealing material can protect the side walls of the circuit substrate to prevent the circuit substrate from directly contacting the cutting device and being damaged, thereby improving the yield of the electronic packaging module. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The present invention will be understood from the following detailed description and the accompanying drawings. It should be noted that various features are not drawn to the standard scale in industry practice. In fact, the size of various features may be arbitrarily increased or decreased for clarity of discussion.

[0020] Figure 1A A cross-sectional view of an electronic packaging module according to an embodiment of the present invention is shown.

[0021] Figure 1B Draw Figure 1A A partial top view of an electronic package module according to an embodiment.

[0022] Figure 2A A cross-sectional view of an electronic packaging module according to another embodiment of the present invention is shown.

[0023] Figure 2B Draw Figure 2A A partial top view of an electronic package module according to an embodiment.

[0024] Figure 3A A cross-sectional view of an electronic packaging module according to another embodiment of the present invention is shown.

[0025] Figure 3B Draw Figure 3A A partial top view of an electronic package module according to an embodiment.

[0026] Figure 4 A cross-sectional view of an electronic packaging module according to another embodiment of the present invention is shown.

[0027] FIG. 5A to FIG. 5H A cross-sectional view is shown of a method for manufacturing an electronic packaging module according to an embodiment of the present invention.

[0028]

Main component symbol description

[0029] 10, 20, 30, 40: electronic packaging module 100, 100': circuit substrate

[0030] 100g: recessed area 102, 104: circuit layer

[0031] 112, 114: insulation layer 112': insulation material

[0032] 112a, 112c: Part 112f, 140f: Initial surface

[0033] 112i,114i: Interface 112p,114p: Peripheral

[0034] 112b,112e,112r,114r: Area 112s,140s,140t,501s: Surface

[0035] 112w, 114w: side wall 116: conductive through hole

[0036] 120: Electronic components 140: Sealing materials

[0037] 160: welding material 162,164: pad

[0038] 180: surface treatment layer 212t, 312t: groove

[0039] 501: Temporary carrier plate 510: Release layer

[0040] 503: seed layer p: cutting device DETAILED DESCRIPTION

[0041] In the following text, in order to clearly present the technical features of this case, the dimensions (such as length, width, thickness and depth) of the elements (such as layers, films, substrates and regions, etc.) in the drawings will be enlarged in unequal proportions, and the number of some elements will be reduced. Therefore, the description and explanation of the embodiments below are not limited to the number of elements in the drawings and the dimensions and shapes presented by the elements, but should cover the dimensions, shapes and deviations of the two caused by actual processes and / or tolerances. Therefore, the elements presented in the drawings of this case are mainly for illustration, and are not intended to accurately depict the actual shape of the elements, nor are they used to limit the scope of the patent application of this case.

[0042] Secondly, the words "approximately", "approximately" or "substantially" that appear in the content of this case not only cover the numerical values ​​and numerical ranges that are clearly recorded, but also cover the allowable deviation range that can be understood by those with ordinary knowledge in the technical field to which the invention belongs, wherein this deviation range can be determined by the error generated during measurement, and this error is caused by, for example, the limitations of the measurement system or process conditions. In addition, "approximately" can be expressed as one or more standard deviations of the above numerical values, such as ±5%, ±3% or ±1%. The words "approximately", "approximately" or "substantially" that appear in this text can select an acceptable deviation range or standard deviation based on optical properties, etching properties, mechanical properties or other properties, rather than applying a single standard deviation to all properties such as the above optical properties, etching properties, mechanical properties and other properties.

[0043] The present invention discloses an electronic packaging module, the structure of at least one embodiment of which is shown in FIG. Figure 1A The electronic packaging module 10 includes a circuit substrate 100, an electronic component 120 and a sealing material 140. In this embodiment, the circuit substrate 100 includes a circuit layer 102, a circuit layer 104, an insulating layer 112, an insulating layer 114 and a conductive via 116, wherein the circuit substrate 100 is substantially a redistribution layer. Figure 1A As shown, the insulating layer 112 covers the circuit layer 102 , and the insulating layer 112 has an interface 112 i and a surface 112 s opposite to the interface 112 i .

[0044] It is particularly noted that the insulating layer 112 covers one surface (not shown) of the circuit layer 102, while the other surface (not shown) of the circuit layer 102 is not covered by the insulating layer 112. The surface not covered by the insulating layer 112 is aligned with the surface 112s of the insulating layer 112, that is, one surface of the circuit layer 102 is coplanar with the surface 112s of the insulating layer 112. In addition, one surface (not shown) of the sealing material 140 is Figure 1A , please refer to Figure 5H The middle surface 140s) is coplanar with the surface 112s and one of the surfaces of the circuit layer 102.

[0045] The circuit layer 104 is located on the interface 112i of the insulating layer 112 and is electrically connected to the circuit layer 102 through the conductive via 116, wherein the conductive via 116 is located between the circuit layer 102 and the circuit layer 104. In this embodiment, only one conductive via 116 is shown, but the present invention is not limited thereto. The number of the conductive vias 116 is determined according to the circuit design and may be more than one.

[0046] The insulating layer 114 is located on the interface 112i of the insulating layer 112 and partially covers the circuit layer 104. Figure 1AAs shown, a plurality of pads 164 are located on the circuit layer 104 and directly contact a portion of the circuit layer 104. The portion of the circuit layer 104 that is in direct contact with the pads 164 is not covered by the insulating layer 114.

[0047] Figure 1B FIG. 1 is a partial top view of the electronic packaging module 10, and the sealing material 140 is omitted. Figure 1A as well as Figure 1B , the insulating layer 114 exposes a region 112r of the interface 112i, and the region 112r is located at a periphery 112p of the interface 112i. Figure 1B As shown, the region 112r is disposed around the insulating layer 114 to form a closed square. However, the present invention is not limited thereto, and the region 112r may discontinuously surround the insulating layer 114 to form a non-closed square.

[0048] See also Figure 2A The electronic packaging module 20 of another embodiment is similar to the aforementioned electronic packaging module 10, except that the insulating layer 114 of the electronic packaging module 20 further includes a plurality of grooves 212t. The grooves 212t are located on the interface 112i. Specifically, the inner surface of the grooves 212t includes a portion 112a (i.e., Figure 2A The bottom of the middle groove 212t).

[0049] Figure 2B This is a partial top view of the above embodiment, and the sealing material 140 is omitted. Please refer to Figure 2A as well as Figure 2B , the groove 212t does not overlap with the region 112r of the interface 112i. In other words, the groove 212t of the insulating layer 114 is separated from the region 112r. In addition, the electronic component 120 overlaps with the region 112e of the interface 112i. In other words, the region 112e is the range of the interface 112i covered by the electronic component 120. Figure 2A As shown, the region 112r surrounds the region 112e, and the groove 212t is located between the region 112r and the region 112e.

[0050] In this embodiment, the four grooves 212t are respectively located between the region 112r and the electronic component 120, and are arranged around the electronic component 120. However, the shape, number and position of the grooves 212t in the present invention are not limited thereto. In other embodiments of the present invention, the number of the grooves 212t may be more than one, and the grooves 212t may also surround the electronic component 120 to form a closed square.

[0051] See also Figure 3AThe electronic packaging module 30 is another embodiment of the electronic packaging module 30. The electronic packaging module 30 is similar to the aforementioned electronic packaging module 10, but the difference is that the insulating layer 114 further includes at least one groove 312t, and the groove 312t is located on the interface 112i. Figure 3A As shown, the electronic component 120 covers the groove 312t. In other words, the electronic component 120 and the groove 312t overlap in the normal direction of the interface 112i.

[0052] The electronic packaging module 30 further includes a plurality of welding materials 160, and these welding materials 160 electrically connect the electronic components 120 and the circuit layer 104. It is worth mentioning that in the aforementioned embodiments, the electronic components 120 are located on the circuit substrate 100 and electrically connected to the circuit substrate 100. Each welding material 160 is electrically connected to the electronic component 120 through a pad 162, and is electrically connected to the circuit layer 104 through another pad 164. In this embodiment, the welding material 160 overlaps with the plurality of regions 112b of the interface 112i. The welding material 160 can be a solder ball, a copper column, or various connection structures suitable for electrical connection.

[0053] Figure 3B FIG. 1 is a partial top view of the electronic packaging module 30 , and the electronic component 120 (including the pad 162 on the electronic component 120 ) and the sealing material 140 are omitted. Figure 3A as well as Figure 3B , where region 112b represents where the welding material 160 and the interface 112i overlap each other, and region 112r surrounds these regions 112b. In this embodiment, the groove 312t is located between two adjacent regions 112b. In detail, the groove 312t is separated from the region 112r of the interface 112i, and can be formed as follows: Figure 3B The grid pattern shown in FIG. 1 is shown in FIG. 1 , and each region 112b is located between the grids formed by a portion of the groove 312t. In other words, a portion of the groove 312t exists between each welding material 160 (i.e., each region 112b). In addition, the inner surface of the groove 312t includes a portion 112c of the interface 112i (i.e., Figure 3A The bottom of the middle groove 312t).

[0054] In other embodiments of the present invention, the electronic packaging module may include the groove 212t and the groove 312t of the above embodiment. For example, the groove 212t is located between the region 112r and the region 112e, and the groove 312t is located between two adjacent regions 112b.

[0055] In addition, see Figure 4In other embodiments of the present invention, the electronic component 120 may be electrically connected to the circuit substrate 100 by wire-bonding. Specifically, the electronic component 120 of the electronic packaging module 40 is electrically connected to the circuit substrate 100 through a metal wire 150, wherein two ends of the metal wire 150 are respectively connected to a pad 162 on the electronic component 120 and a pad 164 on the circuit layer 104.

[0056] The electronic packaging module of the present invention (eg, electronic packaging module 10) further comprises a sealing material 140, such as Figure 1A As shown, the sealing material 140 covers the circuit substrate 100 and the electronic component 120. In various embodiments of the present invention, the sealing material 140 directly contacts the region 112r of the interface 112i and the insulating layer 114. The sealing material 140 may include an insulating material such as an organic resin (such as epoxy resin or ABS resin) or the like. In addition, the sealing material 140 covers the side wall 112w of the insulating layer 112 and directly contacts the side wall 112w.

[0057] It is particularly worth mentioning that in the electronic packaging module 20, the sealing material 140 directly contacts the inner surface of the groove 212t. In detail, the groove 212t is completely filled with the sealing material 140. On the other hand, in the electronic packaging module 30, the sealing material 140 directly contacts the inner surface of the groove 312t, and the groove 312t is completely filled with the sealing material 140. In this way, the contact area between the sealing material 140 and the circuit substrate 100 can be increased to improve the adhesion between the sealing material 140 and the circuit substrate 100.

[0058] Although in the above embodiment, the circuit layer (i.e., the circuit layer 102 and the circuit layer 104) and the insulating layer (i.e., the insulating layer 112 and the insulating layer 114) in the circuit substrate 100 are respectively two layers, the present invention is not limited thereto, and can be more than two layers, for example, three layers. For example, see Figure 1A In other embodiments of the present invention, the electronic packaging module 10 may further include a circuit layer (not shown), which is located on the interface 114i of the insulating layer 114 and electrically connected to the circuit layer 104. The interface 112i and the interface 114i are located on opposite sides of the insulating layer 114, respectively.

[0059] In addition, the electronic packaging module 10 may further include an insulating layer (not shown), and the insulating layer is located on the interface 114i of the insulating layer 114 and partially covers the circuit layer (not shown) on the interface 114i. The insulating layer exposes a region 114r of the interface 114i, and the region 114r is located at a periphery 114p of the interface 114i. In particular, in these embodiments with more than three insulating layers, the sealing material 140 directly contacts the region 114r of the interface 114i.

[0060] See also Figure 1A Although in this embodiment, the angle between the region 112r and the sidewall 114w of the insulating layer 114 is a right angle, the present invention is not limited thereto. In other embodiments, the angle between the region 112r and the sidewall 114w of the insulating layer 114 may not be a right angle, and may even be a rounded angle.

[0061] like Figure 1A As shown, the electronic packaging module 10 may further include a plurality of surface treatment layers 180. The plurality of surface treatment layers 180 are located on the surface 112s of the insulating layer 112 and protrude from the surface 112s. In some embodiments, the circuit substrate 100 may further include at least one solder mask (not shown), which may cover the interface 114i of the insulating layer 114 and expose the pad 162. In addition, the solder mask may also cover the surface 112s of the insulating layer 112 and expose the surface treatment layer 180.

[0062] Although only one electronic component 120 is shown in each of the above embodiments for illustration, the present invention is not limited thereto. The number of the electronic components 120 may be more than one, for example, two. In addition, the electronic component 120 may be a packaged chip or an unpackaged die.

[0063] The method for manufacturing the electronic packaging component of the present invention may include: FIG. 5A to FIG. 5H Several steps are shown, among which FIG. 5A to FIG. 5H The disclosed manufacturing method is based on Figure 1A The electronic packaging module 10 in is used as an example. In this embodiment, first, a temporary carrier plate 501 is provided. The material of this temporary carrier plate 501 may include glass or a polymer material (such as PET). It is worth mentioning that a release layer 510 is also provided above the temporary carrier plate 501 of this embodiment. This release layer 510 may include a release material such as a silicone release agent. However, the present invention is not limited to this, and in other embodiments, the release layer 510 may not be included.

[0064] Next, a circuit substrate 100' is formed on the temporary carrier plate 501, and the surface 501s of the temporary carrier plate 501 is exposed. It is particularly mentioned that, since the present embodiment is provided with a release layer 510, the circuit substrate 100' will be formed on the release layer 510, and the surface 501s of the temporary carrier plate 501 will be covered by the release layer 510, rather than directly exposing the surface 501s. However, other embodiments of the present invention do not necessarily include a release layer 510, so the exposure of the temporary carrier plate 501 mentioned in the present invention is described on the premise that the release layer 510 is omitted.

[0065] The details of this step are as follows: First, a seed layer 503 is deposited on the temporary carrier 501 (or on the release layer 510) by, for example, sputtering. In this embodiment, the material of the seed layer 503 may include a metal material, such as copper. Next, a photoresist material (not shown) is deposited on the seed layer 503, and the photoresist material is patterned by, for example, exposure and development or laser direct imaging (LDI) to expose a portion of the seed layer 503.

[0066] Next, copper is deposited on the exposed seed layer 503 by, for example, electroplating or chemical plating. After copper is plated on the seed layer 503, the photoresist material is removed (striping), and a portion of the seed layer 503 covered by the photoresist material is removed by etching. Figure 5A In the steps shown, a circuit layer 102 is formed on the surface 501s of the temporary carrier plate 501. Figure 5B , forming a circuit substrate 100' (not shown in FIG. Figure 5B ) also includes disposing an insulating material 112' on the circuit layer 102, so that the insulating material 112' covers the temporary carrier 501 and the circuit layer 102. The insulating material 112' may include an insulating material such as an organic resin (such as epoxy resin) or the like.

[0067] See also Figure 5C After the insulating material 112' is provided, the insulating material 112' is patterned by laser direct imaging or the like to form an insulating layer 112. In addition, the insulating layer 112 exposes a surface 501s of the temporary carrier 501, and the surface 501s is located between the temporary carrier 501 and the circuit substrate 100' (not shown). Figure 5C ) between the insulating layers 112.

[0068] Next, see Figure 5D, forming a circuit layer 104 on the insulating layer 112. The steps of forming the circuit layer 104 are similar to the steps of forming the circuit layer 102, so they are not repeated here. It is worth mentioning that in order to make the circuit layer 104 electrically connected to the circuit layer 102, the process of forming the circuit layer 102 on the insulating layer 112 also includes forming a conductive through hole 116.

[0069] After forming the circuit layer 102, another insulating material (not shown) is disposed on the circuit layer 102 so that the insulating material (not shown) covers the insulating layer 112 and the circuit layer 102. The insulating material may include an insulating material such as an organic resin (such as epoxy resin) or the like. Figure 5E , patterning the insulating material (not shown) to form the insulating layer 114 .

[0070] like Figure 5E As shown, the interface 112i of the insulating layer 112 is located between the insulating layer 112 and the insulating layer 114. After patterning, the insulating layer 114 exposes the area 112r of the interface 112i, thereby forming a recessed area 100g of the circuit substrate 100'. In more detail, the circuit substrate 100' includes a recessed area 100g, and this recessed area 100g is formed around a portion of the side wall (not shown) of the circuit substrate 100', and this side wall is located on one side of the insulating layer 114 of the circuit substrate 100'. At this point, the steps of forming the circuit substrate 100' on the temporary carrier 501 (and the release layer 510) and exposing the surface 501s of the temporary carrier 501 are completed.

[0071] See also Fig. 5F After forming the circuit substrate 100', an electronic component 120 is disposed on the circuit substrate 100', and a plurality of soldering materials 160 are used to electrically connect the electronic component 120 and the circuit layer 104. The two sides of the soldering material 160 are respectively connected to the pads 162 on the electronic component 120 and the pads 164 on the circuit layer 104, so that the electronic component 120 is electrically connected to the circuit substrate 100'. Fig. 5F Only one electronic component 120 is shown, but the present invention is not limited thereto, and more than one electronic component 120 may be disposed on the circuit substrate 100 ′.

[0072] After setting up the electronics, such as Figure 5GAs shown, a sealing material 140 is disposed on a temporary carrier plate 501 (or on a release layer 510) to cover the circuit substrate 100' and the electronic component 120. It is particularly mentioned that the sealing material 140 covers the surface 501s of the temporary carrier plate 501 and fills the recessed area 100g of the circuit substrate 100'. In detail, the sealing material 140 covers the side wall (not shown) of the circuit substrate 100', a portion of the interface 112i of the insulating layer 112, and a portion of the interface 114i of the insulating layer 114. After the sealing material 140 is disposed, the temporary carrier plate 501 is removed, thereby exposing the initial surface 112f of the insulating layer 112 and the initial surface 140f of the sealing material 140. It is particularly mentioned that the temporary carrier plate 501 can be removed by laser stripping.

[0073] See also Figure 5H After removing the release layer 510 and the temporary carrier plate 501, a surface treatment layer 180 is formed on the circuit layer 102. The surface treatment layer 180 can be formed by, for example, tin spraying, organic protective film (Organic Soldering Preservative), chemical gold plating, chemical silver plating, and electroplating gold, etc., to prevent the circuit layer 102 from being oxidized. Further, in this embodiment, after removing the release layer 510 and the temporary carrier plate 501 and before forming the surface treatment layer 180, the seed layer 503, a part of the insulating layer 112, and a part of the sealing material 140 can be removed by etching, and the circuit layer 102, the surface 112s of the insulating layer 112, and the surface 140s of the sealing material 140 are exposed.

[0074] Next, the sealing material 140 is cut by, for example, mechanical cutting, laser cutting, or ion beam cutting. Figure 5H As shown, the cutting device p cuts from the surface 140t of the sealing material along the normal direction of the surface 140s to form a plurality of electronic packaging modules 10 separated from each other, wherein Figure 5H The cutting device p shown can be a cutting tool, a laser beam or an ion beam. Although the present embodiment performs cutting after the surface treatment layer 180 is provided, the present invention is not limited thereto, and the surface treatment layer 180 can also be provided after cutting.

[0075] Another embodiment of the present invention can form an electronic packaging module 20. In this embodiment, after the step of patterning the insulating layer 114, the insulating layer 114 further exposes another portion of the interface 112i to form a plurality of grooves 212t. The grooves 212t are separated from the solder material 160 and the recessed area 100g of the circuit substrate 100'.

[0076] In summary, the present invention covers the side wall of the circuit substrate with the sealing material before the cutting step is performed to form the electronic packaging module. In this way, the cutting device only cuts the sealing material without contacting the circuit substrate, thereby avoiding damage to the circuit substrate such as cracks due to cutting, thereby improving the yield of the cutting process. In addition, the recessed area and groove on the circuit substrate can increase the contact area between the sealing material and the circuit substrate, thereby enhancing the adhesion between the sealing material and the circuit substrate and breaking through the minimum adhesion height (standoff) limit, thereby improving the structural stability of the electronic packaging module.

[0077] Although the present invention has been disclosed as above by way of embodiments, they are not intended to limit the present invention. A person having ordinary knowledge in the technical field to which the present invention belongs may make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be determined by what is defined in the claims.

Claims

1. An electronic packaging module, characterized in that: Include: Circuit substrate, including: The first circuit layer; A first insulating layer, covering the first circuit layer and having a first interface; A second circuit layer is located on the first interface of the first insulating layer and is electrically connected to the first circuit layer; A second insulating layer is located on the first interface and partially covers the second circuit layer, wherein the second insulating layer exposes a first area of ​​the first interface, and the first area is located at the periphery of the first interface; An electronic component is located on the circuit substrate and is electrically connected to the circuit substrate; as well as The sealing material covers the circuit substrate and the electronic component, wherein the sealing material directly contacts the first area of ​​the first interface and the second insulating layer.

2. The electronic packaging module according to claim 1, characterized in that: The second insulating layer further comprises: A plurality of grooves, wherein the sealing material directly contacts inner surfaces of the plurality of grooves, and the plurality of grooves do not overlap with the first region of the first interface.

3. The electronic packaging module according to claim 2, characterized in that: The inner surfaces of the plurality of grooves include a portion of the first interface.

4. The electronic packaging module according to claim 2, characterized in that: The electronic component overlaps with the second area of ​​the first interface, and the first area surrounds the second area, and at least one of the plurality of grooves is located between the second area and the first area.

5. The electronic packaging module according to claim 2, characterized in that: The electronic component covers at least one of the plurality of grooves.

6. The electronic packaging module according to claim 4, characterized in that: Also includes: A plurality of welding materials electrically connecting the electronic element and the second circuit layer, wherein the plurality of welding materials overlap with a plurality of third regions of the first interface, wherein the first region surrounds the plurality of third regions; At least one of the plurality of grooves is located between two adjacent third regions.

7. The electronic packaging module according to claim 1, characterized in that: Also includes: A third circuit layer is located on the second interface of the second insulating layer and is electrically connected to the second circuit layer, wherein the first interface and the second interface are respectively located on two opposite sides of the second insulating layer; as well as A third insulating layer is located on the second interface and partially covers the third circuit layer, wherein the third insulating layer exposes a second area of ​​the second interface, and the second area is located at the periphery of the second interface; The sealing material directly contacts the second region.

8. The electronic packaging module according to claim 1, characterized in that: The sealing material covers the sidewalls of the first insulating layer.

9. A method for manufacturing an electronic packaging module, characterized in that: Include: Provide temporary load plates; forming a circuit substrate on the temporary carrier plate and exposing the surface of the temporary carrier plate; Arranging an electronic component on the circuit substrate and electrically connecting the electronic component to the circuit substrate; Disposing a sealing material on the temporary carrier plate to cover the circuit substrate and the electronic component, wherein the sealing material covers the surface of the temporary carrier plate; After the sealing material is disposed, removing the temporary carrier plate; as well as cutting the sealing material after removing the temporary carrier sheet; The circuit substrate includes a recessed area, and the recessed area is formed around the side wall of the circuit substrate, and the sealing material fills the recessed area.

10. The method according to claim 9, characterized in that The method for forming the circuit substrate on the temporary carrier plate comprises: forming a first circuit layer on the temporary carrier board; Disposing a first insulating material on the first circuit layer so that the first insulating material covers the temporary carrier plate and the first circuit layer; Patterning the first insulating material to form a first insulating layer, wherein the first insulating layer exposes the surface of the temporary carrier plate; forming a second circuit layer on the first insulating layer, wherein the second circuit layer is electrically connected to the first circuit layer; Disposing a second insulating material on the second circuit layer so that the second insulating material covers the first insulating layer and the second circuit layer; as well as The second insulating material is patterned to form a second insulating layer, wherein the interface of the first insulating layer is located between the first insulating layer and the second insulating layer, and the second insulating layer exposes the area of ​​the interface to form the recessed area of ​​the circuit substrate.

11. The method according to claim 10, characterized in that The side wall of the circuit substrate is the side wall of the second insulating layer, and the recessed area is formed around the side wall.

12. The method according to claim 10, characterized in that Also includes: After removing the temporary carrier plate, a surface treatment layer is formed on the first circuit layer.

13. The method according to claim 10, characterized in that Also includes: The electronic element and the second circuit layer are electrically connected by a plurality of welding materials, wherein the second insulating layer further exposes a portion of the interface to form a plurality of grooves, and the plurality of grooves are separated from the plurality of welding materials and the recessed area.

Images