Layout structure and layout method of chopper circuit

Abstract

The invention discloses a layout structure and a layout method of a chopper circuit. Two transistors in each set of transistors are arranged in the same type in the first direction, the adjacent ends of the two transistors are the same pole, the transistors of the same type are arranged in the first direction, the transistors of different types are arranged in the second direction, and a phase signal line is connected with grid electrodes of the multiple sets of transistors. The first transmission signal line is connected to one of the drain or the source of each transistor, and the second transmission signal line is connected to the other of the drain or the source of each transistor. Therefore, stray capacitance between the phase signal line and the transmission signal line can be reduced, and circuit performance can be improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a layout structure and a layout method of a chopper circuit. Background Art

[0002] The chopper circuit is responsible for modulating the input signal to a high frequency in order to separate the signal from low-frequency noise and offset voltage. In the design of high-precision amplifiers with high common-mode rejection ratio, low offset voltage, low gain error, and fixed gain, the input offset voltage is a very critical design parameter. The chopper circuit uses the chopper characteristic to reduce the input offset voltage. It is often constructed with a MOS (Metal-Oxide-Semiconductor Field-Effect Transistor) switch. Since the CMOS (Complementary Metal Oxide Semiconductor) structure has parasitic capacitance, including the parasitic capacitance of the device itself and the parasitic capacitance of the external connection, when the phase signal is inconsistent with the parasitic capacitance of the input or output, an additional input offset voltage will be generated. Therefore, there is an urgent need for a method to deal with the parasitic capacitance generated by the phase signal. Summary of the invention

[0003] In view of this, an object of an embodiment of the present invention is to provide a layout structure and a layout method of a chopper circuit, which can reduce the parasitic capacitance between the phase signal line and the transmission signal line and improve the circuit performance.

[0004] In a first aspect, an embodiment of the present invention provides a layout structure of a chopper circuit, the layout structure comprising:

[0005] 4n groups of transistors, each group of transistors includes two transistors, the two transistors are of the same type, the two transistors are arranged along a first direction and adjacent ends have the same pole;

[0006] a set of phase signal lines connected to the gates of the transistors;

[0007] n groups of first transmission signal lines connected to one of the drain or source of each of the transistors;

[0008] n groups of second transmission signal lines connected to the other of the drain or the source of each of the transistors;

[0009] The transistors of the same type are arranged along a first direction, and the transistors of different types are arranged along a second direction, and n is greater than or equal to 1.

[0010] In some embodiments, the layout structure further includes:

[0011] A group of shielding lines are arranged on both sides of the phase signal line.

[0012] In some embodiments, n is equal to 1, and the 4n sets of transistors include:

[0013] A first group of transistors including a first P-type transistor and a second P-type transistor;

[0014] a second group of transistors including a third P-type transistor and a fourth P-type transistor;

[0015] A third group of transistors includes a first N-type transistor and a second N-type transistor;

[0016] The fourth group of transistors includes a third N-type transistor and a fourth N-type transistor.

[0017] In some embodiments, the set of phase signal lines includes:

[0018] A first phase signal line connected to the gates of the first N-type transistor, the second P-type transistor, the third P-type transistor and the fourth N-type transistor;

[0019] The second phase signal line is connected to the gates of the first P-type transistor, the second N-type transistor, the third N-type transistor, and the fourth P-type transistor.

[0020] In some embodiments, the first phase signal line and the second phase signal line are extended along a first direction and are parallel to each other.

[0021] In some embodiments, the set of shielded wires includes:

[0022] A first shielded line and a second shielded line, wherein the first phase signal line and the second phase signal line are located between the first shielded line and the second shielded line.

[0023] In some embodiments, the first group of transistors and the second group of transistors are arranged along a first direction on a first side of the first shielding line, and the third group of transistors and the fourth group of transistors are arranged along the first direction on a second side of the second shielding line, wherein the first side of the first shielding line is opposite to the second side, the first side and the second side of the second shielding line are opposite to each other, and the second side of the first shielding line is adjacent to the first side of the second shielding line.

[0024] In some embodiments, the n groups of first transmission signal lines or the n groups of second transmission signal lines are connected to drains or sources of two transistors in each group of transistors that are adjacent to each other.

[0025] In some embodiments, a group of first transmission signal lines includes a first connection line and a second connection line, the first connection line and the second connection line are parallel and arranged along a second direction, and the first direction is perpendicular to the second direction;

[0026] A group of second transmission signal lines includes a third connection line and a fourth connection line, wherein the third connection line and the fourth connection line are parallel and arranged along a second direction, and the first direction is perpendicular to the second direction.

[0027] In some embodiments, the first P-type transistor and the second P-type transistor are symmetrically arranged on both sides of the first connecting line, the first N-type transistor and the second N-type transistor are symmetrically arranged on both sides of the first connecting line, the third P-type transistor and the fourth P-type transistor are symmetrically arranged on both sides of the second connecting line, and the third N-type transistor and the fourth N-type transistor are symmetrically arranged on both sides of the second connecting line.

[0028] In some embodiments, the first group of transistors and the third group of transistors are disposed on one side of the third and fourth connection lines, and the second group of transistors and the fourth group of transistors are disposed on the other side opposite to the third and fourth connection lines.

[0029] In some embodiments, the first phase signal line, the second phase signal line, the first shielding line, and the second shielding line are arranged on the same metal connection layer.

[0030] In some embodiments, the layout structure further includes:

[0031] The shielding layer is a metal connection layer disposed above the first phase signal line, the second phase signal line, the first shielding line, and the second shielding line, and is connected to the first shielding line and the second shielding line through a through hole.

[0032] In some embodiments, the layout structure further includes:

[0033] A first auxiliary connection line and a second auxiliary connection line extending along a first direction and arranged at a first side of the first group of transistors and the second group of transistors along a second direction;

[0034] A third auxiliary connection line and a fourth auxiliary connection line extending along the first direction and arranged along the second direction on the second side of the third group of transistors and the fourth group of transistors;

[0035] The third connection line is connected to the second auxiliary connection line and the third auxiliary connection line, and the fourth connection line is connected to the first auxiliary connection line and the fourth auxiliary connection line.

[0036] In some embodiments, the layout structure further includes:

[0037] a fifth auxiliary connecting line extending along the first direction;

[0038] a sixth auxiliary connection line extending along the first direction, arranged in parallel with the fifth auxiliary connection line, and arranged on a first side of the first and second groups of transistors or on a second side of the third and fourth groups of transistors;

[0039] Wherein, the third connection line is connected to the fifth auxiliary connection line, and the fourth connection line is connected to the sixth auxiliary connection line.

[0040] In some embodiments, the first connection line and the second connection line are input / output signal connection lines, and the third connection line and the fourth connection line are output / input signal connection lines;

[0041] Wherein, the first connecting line is connected to the source / drain of the first P-type transistor and the second P-type transistor, and is connected to the drain / source of the first N-type transistor and the second N-type transistor;

[0042] The second connection line is connected to the source / drain of the third P-type transistor and the fourth P-type transistor, and is connected to the drain / source of the third N-type transistor and the fourth N-type transistor;

[0043] A second auxiliary connection line is connected to the drain / source of the second P-type transistor and the fourth P-type transistor;

[0044] A third auxiliary connection line is connected to the source / drain of the second N-type transistor and the fourth N-type transistor;

[0045] A first auxiliary connection line is connected to the drain / source of the first P-type transistor and the third P-type transistor;

[0046] The fourth auxiliary connection line is connected to the source / drain of the first N-type transistor and the third N-type transistor.

[0047] In some embodiments, the first connection line and the second connection line are input / output signal connection lines, and the third connection line and the fourth connection line are output / input signal connection lines;

[0048] Wherein, the first connecting line is connected to the source / drain of the first P-type transistor and the second P-type transistor, and is connected to the drain / source of the first N-type transistor and the second N-type transistor;

[0049] The second connection line is connected to the source / drain of the third P-type transistor and the fourth P-type transistor, and is connected to the drain / source of the third N-type transistor and the fourth N-type transistor;

[0050] A fifth auxiliary connection line is connected to the drain / source of the second P-type transistor and the fourth P-type transistor, and is connected to the source / drain of the second N-type transistor and the fourth N-type transistor;

[0051] The sixth auxiliary connection line is connected to the drain / source of the first P-type transistor and the third P-type transistor, and is connected to the source / drain of the first N-type transistor and the third N-type transistor.

[0052] In some embodiments, the phase signal line and the transmission signal line are arranged in different metal connection layers.

[0053] In some embodiments, the phase signal line is disposed in a lowest level metal connection layer, and the transmission signal line is disposed in a highest level metal connection layer.

[0054] In some embodiments, the auxiliary connection line and the phase signal line are arranged in the same metal connection layer, and the distance between the phase signal line and the auxiliary connection line is greater than a predetermined value.

[0055] In some embodiments, n is greater than 1, and the 4n sets of transistors include:

[0056] n first groups of transistors, each of which includes a first P-type transistor and a second P-type transistor;

[0057] n second groups of transistors, each second group of transistors comprising a third P-type transistor and a fourth P-type transistor;

[0058] n third groups of transistors, each of which includes a first N-type transistor and a second N-type transistor;

[0059] There are n fourth groups of transistors, each of which includes a third N-type transistor and a fourth N-type transistor.

[0060] In a second aspect, an embodiment of the present invention provides a layout method of a chopper circuit layout structure, the method comprising:

[0061] 4n groups of transistors are arranged, each group of transistors includes two transistors, the two transistors are of the same type, the two transistors are arranged along a first direction and adjacent ends are at the same pole, the transistors of the same type are arranged along the first direction, and the transistors of different types are arranged along the second direction, and n is greater than or equal to 1;

[0062] connecting a set of phase signal lines to the gate of the transistor;

[0063] Connecting n groups of first transmission signal lines to one of the drain or source of the transistor;

[0064] The n groups of second transmission signal lines are connected to the other of the drain or the source of the transistor.

[0065] The technical solution of the embodiment of the invention is to set the two transistors in each group of transistors to be of the same type, arranged along the first direction and with the adjacent ends being the same pole, the transistors of the same type are arranged along the first direction, the transistors of different types are arranged along the second direction, the phase signal line is connected to the gates of the multiple groups of transistors, the first transmission signal line is connected to one of the drain or source of the transistor, and the second transmission signal line is connected to the other of the drain or source of the transistor. In this way, the parasitic capacitance between the phase signal line and the transmission signal line can be reduced, and the circuit performance can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0066] The above and other objects, features and advantages of the present invention will become more apparent through the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:

[0067] Figure 1 is a circuit diagram of an operational amplifier circuit according to an embodiment of the present invention;

[0068] Figure 2 is a circuit diagram of a chopper circuit according to an embodiment of the present invention;

[0069] Figure 3 is a schematic diagram of a first example of a layout structure of a chopper circuit according to a first embodiment of the present invention;

[0070] Figure 4 is a schematic diagram of a second example of the layout structure of the chopper circuit of the first embodiment of the present invention;

[0071] Figure 5 is a schematic diagram of a third example of the layout structure of the chopper circuit of the first embodiment of the present invention;

[0072] Figure 6 is a schematic diagram of a shielding structure according to an embodiment of the present invention;

[0073] Figure 7 is a schematic diagram of the layout structure of a chopper circuit according to a second embodiment of the present invention;

[0074] Figure 8 is a circuit diagram of a chopper circuit according to another embodiment of the present invention;

[0075] Fig. 9 is a schematic diagram of the layout structure of a chopper circuit according to a third embodiment of the present invention;

[0076] Fig.10 It is a flow chart of a layout method of a chopper circuit layout structure according to an embodiment of the present invention. DETAILED DESCRIPTION

[0077] The present invention is described below based on embodiments, but the present invention is not limited to these embodiments. In the detailed description of the present invention below, some specific details are described in detail. It is possible for a person skilled in the art to fully understand the present invention without the description of these details. In order to avoid confusing the essence of the present invention, known methods, processes, flows, components and circuits are not described in detail.

[0078] In addition, persons of ordinary skill in the art will appreciate that the drawings provided herein are for illustration purposes and are not necessarily drawn to scale.

[0079] At the same time, it should be understood that in the following description, "circuit" refers to a conductive loop composed of at least one element or subcircuit through electrical connection or electromagnetic connection. When an element or circuit is said to be "connected to" another element or an element / circuit is said to be "connected between" two nodes, it can be directly coupled or connected to another element or there can be an intermediate element, and the connection between the elements can be physical, logical, or a combination thereof. On the contrary, when an element is said to be "directly coupled to" or "directly connected to" another element, it means that there is no intermediate element between the two.

[0080] Unless the context clearly requires otherwise, the words "include", "comprising" and the like throughout this application should be interpreted as including rather than exclusive or exhaustive; that is, as meaning "including but not limited to".

[0081] In the description of the present invention, it should be understood that the terms "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or implying relative importance. In addition, in the description of the present invention, unless otherwise specified, "plurality" means two or more.

[0082] Figure 1 is a circuit diagram of an operational amplifier circuit according to an embodiment of the present invention. Figure 1 As shown, the operational amplifier circuit of the embodiment of the present invention includes multiple resistors, multiple amplifiers and multiple chopper circuits. The resistors include R 1P , R 2P , R 3P , R 4P , R 1N , R 2N , R 3N , R 4N The amplifier includes GMA, GMB, GMC, and the chopper circuit includes CH1 and CH2.

[0083] Among them, the resistor R 1P , R 2P , R 3P , R 4PConnected in series between the input terminal IN1 and the output terminal OUT1, the resistor R 1N , R 2N , R 3N , R 4N They are connected in series between the input terminal IN2 and the output terminal OUT2.

[0084] One input terminal of the chopper circuit CH1 is connected to R 2N and R 3N The other input terminal is connected to R 1P and R 2P The two output terminals of the chopper circuit CH1 are connected to the input terminals of the amplifier GMA.

[0085] One input terminal of the chopper circuit CH2 is connected to R 2P and R 3P The other input terminal is connected to R 1N and R 2N The two output ends of the chopper circuit CH2 are connected to the input ends of the amplifier GMB.

[0086] The outputs of the amplifier GMA and the amplifier GMB are superimposed and provided to the amplifier GMC. The two output terminals of the amplifier GMC are connected to the output terminal OUT1 and the output terminal OUT2 respectively.

[0087] In this embodiment, the layout structure of the chopper circuit includes 4n groups of transistors, a group of phase signal lines, n groups of first transmission signal lines and n groups of second transmission signal lines. Among them, every four groups of transistors correspond to a group of first transmission signal lines and a group of second transmission signal lines. The 4n groups of transistors share a group of phase signal lines. n is greater than or equal to 1, and n is a positive integer.

[0088] Figure 2 is a circuit diagram of a chopper circuit according to an embodiment of the present invention. Figure 2 The chopper circuit shown is a chopper circuit corresponding to the layout structure when n=1, including a plurality of transistors, a group of phase lines, a group of input terminals and a group of output terminals.

[0089] In this embodiment, the transistor is a MOSFET (Metal-Oxide-Semiconductor Field-EffectTransistor), also known as a MOS. MOS tubes are divided into PMOS tubes (P-channel MOS) and NMOS (N-channel MOS) tubes. Among them, the multiple transistors include four P-type transistors (PMOS) and four N-type transistors (NMOS). The four P-type transistors are respectively a first P-type transistor M1, a second P-type transistor M2, a third P-type transistor M3, and a fourth P-type transistor M4. The four N-type transistors are respectively a first N-type transistor M5, a second N-type transistor M6, a third N-type transistor M7, and a fourth N-type transistor M8.

[0090] A set of phase signal lines includes a first phase signal line PH1 and a second phase signal line PH2.

[0091] A set of input terminals includes IN P and IN N .

[0092] A set of output terminals includes OUT P and OUT N .

[0093] Each transistor includes a gate G, a drain D and a source S.

[0094] The first phase signal line PH1 is connected to gates of the second P-type transistor M2 , the third P-type transistor M3 , the first N-type transistor M5 , and the fourth N-type transistor M8 .

[0095] The second phase signal line PH2 is connected to the gates of the first P-type transistor M1 , the fourth P-type transistor M4 , the second N-type transistor M6 , and the third N-type transistor M7 .

[0096] The first transmission gate composed of the first P-type transistor M1 and the first N-type transistor M5 is connected to the input terminal IN. P and output terminal OUT P between.

[0097] The second transmission gate composed of the second P-type transistor M2 and the second N-type transistor M6 is connected to the input terminal IN P and output terminal OUT N between.

[0098] A third transmission gate composed of a third P-type transistor M3 and a third N-type transistor M7 is connected to the input terminal IN. N and output terminal OUT P between.

[0099] A fourth transmission gate composed of a fourth P-type transistor M4 and a fourth N-type transistor M8 is connected to the input terminal IN. N and output terminal OUT N between.

[0100] Since the phase signal line transmits a PWM (Pulse Width Modulation) signal, the rising or falling signal will produce a clock feedthrough effect. P / IN N And the output terminal OUT P / OUT N When the parasitic capacitance of the capacitor is inconsistent, additional offset voltage will be generated.

[0101] Therefore, the embodiment of the present invention provides a layout structure of a chopper circuit to reduce or eliminate the offset voltage.

[0102] Figure 3 1 is a schematic diagram of a first example of the layout structure of the chopper circuit of the first embodiment of the present invention. Figure 3 As shown, when n=1, the layout structure of the chopper circuit of the first embodiment of the present invention includes 4 groups of transistors, a group of phase signal lines, a group of first transmission signal lines, a group of second transmission signal lines, auxiliary connection lines, etc.

[0103] Among them, for the four groups of transistors, each group of transistors includes two transistors, the two transistors are of the same type, the two transistors are arranged along the first direction, and one adjacent end of the two transistors has the same pole.

[0104] In this embodiment, the transistor is a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor), also known as MOS. A MOS transistor includes three electrodes, namely a gate G, a drain D and a source S.

[0105] exist Figure 3 In the illustrated embodiment, the first direction F1 is vertically upward, and the second direction F2 is horizontally rightward.

[0106] Furthermore, one adjacent end of two transistors in each group of transistors is the same electrode, that is, the same is the drain electrode D of the transistor or the same is the source electrode S of the transistor.

[0107] Specifically, the four groups of transistors include a first group of transistors, a second group of transistors, a third group of transistors and a fourth group of transistors.

[0108] The first group of transistors includes a first P-type transistor M1 and a second P-type transistor M2.

[0109] The second group of transistors includes a third P-type transistor M3 and a fourth P-type transistor M4.

[0110] The third group of transistors includes a first N-type transistor M5 and a second N-type transistor M6.

[0111] The fourth group of transistors includes a third N-type transistor M7 and a fourth N-type transistor M8.

[0112] In some embodiments, two transistors in each group of transistors are symmetrically arranged along the second direction F2.

[0113] In some embodiments, transistors of the same type are arranged along the first direction, and transistors of different types are arranged along the second direction. Specifically, the first group of transistors and the second group of transistors are arranged along the first direction. That is, the first P-type transistor M1, the second P-type transistor M2, the third P-type transistor M3, and the fourth P-type transistor M4 are arranged on the same straight line, and the direction of the straight line is the first direction. Thus, the first group of transistors and the second group of transistors are symmetrical along the second direction.

[0114] In some embodiments, the third group of transistors and the fourth group of transistors are arranged along the first direction. That is, the first N-type transistor M5, the second N-type transistor M6, the third N-type transistor M7 and the fourth N-type transistor M8 are arranged on the same straight line, and the direction of the straight line is the first direction. Thus, the third group of transistors and the fourth group of transistors are symmetrical along the second direction.

[0115] Thus, by setting the two transistors in each group of transistors to be symmetrical, and the first group of transistors and the second group of transistors to be symmetrical, and the third group of transistors and the fourth group of transistors to be symmetrical, this symmetrical layout can reduce the effects of parasitic capacitance caused by asymmetric layout, improve the stability of the circuit, and at the same time, reduce the complexity and uncertainty in the design process and simplify the wiring process. Moreover, since the drains or sources of the two transistors are adjacent and symmetrical, it is easier to realize the layout of signal lines and power lines, reduce crossing and winding, and reduce wiring complexity and cost. When multiple components are laid out in a limited space, the symmetrical layout can make more efficient use of space and reduce unnecessary blank areas.

[0116] It should be understood that Figure 3 The configuration shown is only an example provided by the embodiment of the present invention, and the embodiment of the present invention does not limit the configuration of each transistor. For example, the two transistors in each group of transistors can be interchanged. At the same time, the adjacent ends of the two transistors in each group of transistors can be merged or not. Figure 3 The example of non-merging is used for explanation.

[0117] In this embodiment, a group of phase signal lines are connected to the gates of the plurality of groups of transistors. The group of phase signal lines includes a first phase signal line PH1 and a second phase signal line PH2. The first phase signal line PH1 is connected to the gates of the first N-type transistor M5, the second P-type transistor M2, the third P-type transistor M3, and the fourth N-type transistor M8. The second phase signal line PH2 is connected to the gates of the first P-type transistor M1, the second N-type transistor M6, the third N-type transistor M7, and the fourth P-type transistor M4.

[0118] In some embodiments, the first phase signal line PH1 and the second phase signal line PH2 extend along a first direction, the first phase signal line PH1 and the second phase signal line PH2 are arranged in parallel along a second direction, the first phase signal line PH1 is arranged on a first side, and the second phase signal line PH2 is arranged on a second side. The first side is a side opposite to the second direction, and the second side is a side identical to the second direction.

[0119] In this embodiment, a group of first transmission signal lines or a group of second transmission signal lines are connected to the drains or sources of two transistors adjacent to each other in each group of transistors.

[0120] The group of first transmission signal lines includes a first connection line L1 and a second connection line L2 , and the first connection line and the second connection line are parallel and extend along the second direction.

[0121] The group of second transmission signal lines includes a third connection line L3 and a fourth connection line L4 , and the third connection line L3 and the fourth connection line L4 are parallel and extend along the second direction.

[0122] Further, the first P-type transistor M1 and the second P-type transistor M2 are symmetrically arranged on both sides of the first connection line L1, and the first N-type transistor M5 and the second N-type transistor M6 are symmetrically arranged on both sides of the first connection line L1. In a top view, the first P-type transistor M1 and the second P-type transistor M2 are symmetrically arranged with the first connection line L1 as a symmetry axis, and the first N-type transistor M5 and the second N-type transistor M6 are symmetrically arranged with the first connection line L1 as a symmetry axis.

[0123] The third P-type transistor M3 and the fourth P-type transistor M4 are arranged on both sides of the second connection line L2, and the third N-type transistor M7 and the fourth N-type transistor M8 are arranged on both sides of the second connection line L2. That is, in a top view, the third P-type transistor M3 and the fourth P-type transistor M4 are symmetrically arranged with the second connection line L2 as a symmetry axis, and the third N-type transistor M7 and the fourth N-type transistor M8 are symmetrically arranged with the second connection line L2 as a symmetry axis.

[0124] The first group of transistors and the third group of transistors are arranged on one side of the third connection line L3 and the fourth connection line L4, and the second group of transistors and the fourth group of transistors are arranged on the other side of the third connection line L3 and the fourth connection line L4. That is, the first group of transistors and the third group of transistors are symmetrical along the center line of the third connection line L3 and the fourth connection line L4, and the second group of transistors and the fourth group of transistors are symmetrical along the center line of the third connection line L3 and the fourth connection line L4. The center line of the third connection line L3 and the fourth connection line L4 refers to the center line arranged between the third connection line L3 and the fourth connection line L4 along the second direction.

[0125] In this embodiment, the auxiliary connection lines include a first auxiliary connection line B1, a second auxiliary connection line A1, a third auxiliary connection line A2 and a fourth auxiliary connection line B2.

[0126] The first auxiliary connection line B1 extends along a first direction on a first side of the first group of transistors and the second group of transistors.

[0127] The second auxiliary connection line A1 extends along a first direction on a first side of the first auxiliary connection line B1.

[0128] The third auxiliary connection line A2 extends along the first direction on the second sides of the third and fourth groups of transistors.

[0129] The fourth auxiliary connection line B2 extends along the first direction on the second side of the third auxiliary connection line A2.

[0130] The third connection line L3 is connected to the second auxiliary connection line A1 and the third auxiliary connection line A2, and the fourth connection line L4 is connected to the first auxiliary connection line B1 and the fourth auxiliary connection line B2.

[0131] In some embodiments, the first connection line L1 and the second connection line L2 are input / output signal connection lines, and the third connection line L3 and the fourth connection line L4 are output / input signal connection lines.

[0132] The first connection line L1 is connected to the source / drain of the first P-type transistor M1 and the second P-type transistor M2, and is connected to the drain / source of the first N-type transistor M5 and the second N-type transistor M6. The second connection line L2 is connected to the source / drain of the third P-type transistor M3 and the fourth P-type transistor M4, and is connected to the drain / source of the third N-type transistor M7 and the fourth N-type transistor M8.

[0133] The second auxiliary connection line A1 is connected to the drain / source of the second P-type transistor M2 and the fourth P-type transistor M4 .

[0134] The third auxiliary connection line A2 is connected to the source / drain of the second N-type transistor M6 and the fourth N-type transistor M8.

[0135] The first auxiliary connection line B1 is connected to the drain / source of the first P-type transistor M1 and the third P-type transistor M3 .

[0136] The fourth auxiliary connection line B2 is connected to the source / drain of the first N-type transistor M5 and the third N-type transistor M7.

[0137] That is, the first connection line L1 and the second connection line L2 are input signal connection lines, and the third connection line L3 and the fourth connection line L4 are output signal connection lines; or, the first connection line L1 and the second connection line L2 are output signal connection lines, and the third connection line L3 and the fourth connection line L4 are input signal connection lines. At the same time, each auxiliary connection line is configured to be connected to the source or drain of each transistor according to the actual situation of the circuit to achieve chopping.

[0138] Specifically, the phase signal line is arranged in the lowest level metal connection layer, and the transmission signal line is arranged in the highest level metal connection layer.

[0139] The layout structure of the circuit generally includes the top layer, the inner signal layer, the inner power layer and the bottom layer. Among them, the inner signal layer can be composed of multiple levels for arranging various signal lines and signal planes. The lowest level of the metal connection layer described in the embodiment of the present invention can refer to the bottom layer or the lowest level in the internal signal layer; similarly, the highest level of the metal connection layer can refer to the top layer or the highest level in the internal signal layer.

[0140] Thus, the influence of the phase signal line on the transmission signal can be further reduced, and the parasitic capacitance of the transmission signal to the ground or the power supply can also be reduced.

[0141] It should be understood that Figure 3 In the illustrated embodiment, for a point where two lines intersect, if there is a black dot mark, it indicates that the two lines are connected; if there is no black dot mark, it indicates that the two lines are not connected.

[0142] It should be noted that Figure 3In the layout structure shown, the connection method of the body end of the MOS device, that is, the well layout, is ignored. In a MOS tube, the body end usually refers to the part connected to the source (Source) and grounded. It is mainly composed of semiconductor materials and is used to control the working mode of the MOS tube. In NMOS (N-channel MOS tube), the body end is usually a P-type semiconductor, and in PMOS (P-channel MOS tube), it is an N-type semiconductor. The well layout refers to an area with a specific conductivity type formed on a semiconductor substrate by a specific process. In the CMOS process, since both NMOS and PMOS tubes are included, different types of wells are usually required to accommodate them respectively. Due to different processes, the well layout of the embodiment of the present invention can be laid out in various ways according to the circuit design requirements, as long as it does not affect the main layout structure of the device, such as CMOS, BCD processes, etc.

[0143] In the embodiment of the present invention, two transistors in each group of transistors are arranged to be of the same type, arranged along a first direction and with adjacent ends being the same pole, transistors of the same type are arranged along the first direction, transistors of different types are arranged along the second direction, a phase signal line is connected to the gates of multiple groups of transistors, a first transmission signal line is connected to one of the drain or source of each transistor, and a second transmission signal line is connected to the other of the drain or source of each transistor. Thus, the parasitic capacitance between the phase signal line and the transmission signal line can be reduced, and the circuit performance can be improved.

[0144] Figure 4 FIG. 1 is a diagram showing a second example of the layout structure of the chopper circuit according to the first embodiment of the present invention. Figure 4 The layout structure of the chopper circuit shown is similar to Figure 3 Similarly, the layout structure of the chopper circuit when n=1 is the same as Figure 3 The difference is that in addition to 4 groups of transistors, a group of phase signal lines, a group of first transmission signal lines, a group of second transmission signal lines, auxiliary connection lines and other structures, a group of shielding lines is also provided.

[0145] In this embodiment, a group of shielding wires are arranged on both sides of the phase signal line. The group of shielding wires includes a first shielding wire SH1 and a second shielding wire SH2. The first shielding wire SH1 is arranged on the first side of the first phase signal line PH1. The second shielding wire SH2 is arranged on the second side of the second phase signal line PH2. That is, the first shielding wire SH1, the first phase signal line PH1, the second phase signal line PH2, and the second shielding wire SH2 are arranged in sequence along the second direction, so that the first phase signal line PH1 and the second phase signal line PH2 are arranged between the first shielding wire SH1 and the second shielding wire SH2 to shield the first phase signal line PH1 and the second phase signal line PH2.

[0146] In some embodiments, the first phase signal line, the second phase signal line, the first shielding line, and the second shielding line are arranged on the same metal connection layer, thereby reducing or avoiding the offset voltage generated due to the inconsistency between the phase signal and the input or output parasitic capacitance.

[0147] In some embodiments, the phase signal line and the transmission signal line are set in different metal connection layers, the phase signal line and the shielding line are set to the same metal connection layer, the transmission signal line and the auxiliary connection line can be set to the same metal connection layer or different metal connection layers. Furthermore, the level of the metal connection layer where the transmission signal line is located is higher than the level of the metal connection layer where the phase signal line belongs.

[0148] It should be understood that Figure 4 The rest of the layout structure shown is similar to Figure 3 Similarly, the embodiments of the present invention will not be described in detail here.

[0149] In the embodiment of the present invention, two transistors in each group of transistors are arranged to be of the same type, arranged along a first direction and with adjacent ends being of the same pole, a phase signal line is connected to the gates of multiple groups of transistors, shielding lines are arranged on both sides of the phase signal line, a first transmission signal line is connected to one of the drain or source of each transistor, and a second transmission signal line is connected to the other of the drain or source of each transistor. Thus, the parasitic capacitance between the phase signal line and the transmission signal line can be reduced by the shielding line, thereby improving circuit performance.

[0150] Figure 5 FIG. 1 is a diagram showing a third example of the layout structure of the chopper circuit according to the first embodiment of the present invention. Figure 5 The layout structure shown is similar to Figure 4The difference is that the layout structure also includes a shielding layer PB. The shielding layer PB is a metal connection layer arranged above the first phase signal line PH1, the second phase signal line PH2, the first shielding line SH1, and the second shielding line SH2 (the structure of SH1, SH2, PH1, and PH2 is not shown in the figure, and is arranged below the shielding layer PB). Figure 5 The rest of the layout structure shown is similar to Figure 3 and Figure 4 Similarly, the embodiments of the present invention will not be described in detail here.

[0151] In some embodiments, the shielding layer PB is connected to the first shielding wire SH1 and the second shielding wire SH2 through a through hole.

[0152] Specifically, Figure 6 Schematic diagram of the shielding structure of an embodiment of the present invention. Figure 6 As shown, the shielding layer PB is disposed on a metal connection layer above the first phase signal line PH1, the second phase signal line PH2, the first shielding line SH1, and the second shielding line SH2, and the shielding layer PB is connected to the first shielding line SH1 and the second shielding line SH2 through a through hole. Specifically, the shielding layer PB is connected to the first shielding line SH1 through a through hole HO1, and the shielding layer PB is connected to the second shielding line SH2 through a through hole HO2.

[0153] In an embodiment of the present invention, if the metal layer permits, a higher-level metal wire is covered above the first phase signal line PH1, the second phase signal line PH2, the first shielding line SH1, and the second shielding line SH2 as an upper shield. All shielding layers and shielding wires are connected together through through holes and finally connected to the grounding point of the chip. This can further reduce the impact of the phase signal line on the transmission signal, and can also reduce the parasitic capacitance of the transmission signal to the ground or power supply.

[0154] In the embodiment of the present invention, two transistors in each group of transistors are arranged to be of the same type, arranged along a first direction and with adjacent ends being the same pole, transistors of the same type are arranged along the first direction, transistors of different types are arranged along the second direction, a phase signal line is connected to the gates of multiple groups of transistors, a first transmission signal line is connected to one of the drain or source of each transistor, and a second transmission signal line is connected to the other of the drain or source of each transistor. Thus, the parasitic capacitance between the phase signal line and the transmission signal line can be reduced, and the circuit performance can be improved.

[0155] Figure 7 FIG. 4 is a schematic diagram of a layout structure of a chopper circuit according to a second embodiment of the present invention. Figure 7 The layout structure shown is similar to Figure 4 The difference is that Figure 4 There are four auxiliary connection lines in the Figure 7 There are two auxiliary connecting lines in the embodiment, and correspondingly, the configuration methods of the third connecting line and the fourth connecting line are also different.

[0156] Specifically, in Figure 7 In the illustrated embodiment, the auxiliary connection line includes a fifth auxiliary connection line A3 and a sixth auxiliary connection line B3, wherein the fifth auxiliary connection line A3 and the sixth auxiliary connection line B3 are arranged along a first direction and are parallel to each other, and are arranged on a first side of the first group of transistors and the second group of transistors or on a second side of the third group of transistors and the fourth group of transistors. Figure 7 The illustrated embodiment is described by taking the second side of the third group of transistors and the second side of the fourth group of transistors as an example.

[0157] Further, the third connection line L3 is connected to the fifth auxiliary connection line A3, and the fourth connection line L4 is connected to the sixth auxiliary connection line B3.

[0158] The first connection line L1 and the second connection line L2 are input / output signal connection lines, and the third connection line L3 and the fourth connection line L4 are output / input signal connection lines.

[0159] The first connection line L1 is connected to the source / drain of the first P-type transistor M1 and the second P-type transistor M2 , and is connected to the drain / source of the first N-type transistor M5 and the second N-type transistor M6 .

[0160] The second connection line L2 is connected to the source / drain of the third P-type transistor M3 and the fourth P-type transistor M4 , and is connected to the drain / source of the third N-type transistor M7 and the fourth N-type transistor M8 .

[0161] The fifth auxiliary connection line A3 is connected to the drain / source of the second P-type transistor M2 and the fourth P-type transistor M4 , and is connected to the source / drain of the second N-type transistor M6 and the fourth N-type transistor M8 .

[0162] The sixth auxiliary connection line B3 is connected to the drain / source of the first P-type transistor M1 and the third P-type transistor M3 , and is connected to the source / drain of the first N-type transistor M5 and the third N-type transistor M6 .

[0163] That is, the first connection line L1 and the second connection line L2 are input signal connection lines, and the third connection line L3 and the fourth connection line L4 are output signal connection lines; or, the first connection line L1 and the second connection line L2 are output signal connection lines, and the third connection line L3 and the fourth connection line L4 are input signal connection lines. At the same time, each auxiliary connection line is configured to be connected to the source or drain of each transistor according to the actual situation of the circuit to achieve chopping.

[0164] In some embodiments, the first transmission signal line and the second transmission signal line are arranged in the same metal connection layer, and are arranged in a different metal connection layer from the phase signal line, thereby reducing or avoiding the parasitic capacitance between the phase signal line and the transmission signal line, and improving the circuit performance.

[0165] In some embodiments, the auxiliary connection line and the phase signal line are arranged in the same metal connection layer, and the distance between the phase signal line and the auxiliary connection line is greater than a predetermined value, thereby reducing or avoiding the parasitic capacitance between the phase signal line and the transmission signal line, and improving the circuit performance.

[0166] In some embodiments, a shielding layer may be further provided on the layout structure, which may be specifically as follows: Figure 5-Figure 6 As shown, the embodiments of the present invention are not described in detail here.

[0167] In the embodiment of the present invention, two transistors in each group of transistors are arranged to be of the same type, arranged along a first direction and with adjacent ends being the same pole, transistors of the same type are arranged along the first direction, transistors of different types are arranged along the second direction, a phase signal line is connected to the gates of multiple groups of transistors, a first transmission signal line is connected to one of the drain or source of each transistor, and a second transmission signal line is connected to the other of the drain or source of each transistor. Thus, the parasitic capacitance between the phase signal line and the transmission signal line can be reduced, and the circuit performance can be improved.

[0168] Figure 8 is a circuit diagram of a chopper circuit according to another embodiment of the present invention. Figure 8 The chopper circuit shown is a chopper circuit corresponding to the layout structure when n=2, that is, a dual-input chopper circuit, including two channels, the input of the first channel is IN P1 and IN N1 , the output is OUT P1 and OUT N1 The second channel input is IN P2 and IN N2 , the output is OUT P2 and OUT N2 The circuit structure of each channel is the same as Figure 2 The chopper circuits shown are identical, with both channels sharing a common set of phase lines.

[0169] Fig. 9 Schematic diagram of the layout structure of the chopper circuit according to the third embodiment of the present invention. Fig. 9 The layout shown is suitable for Figure 8 The chopper circuit shown in FIG. Fig. 9The layout structure shown includes layout structures of multiple chopper circuits, and the multiple layout structures use the same phase signal line and shielding line. The layout structure of each chopper circuit can be set as follows: Figure 4 As shown, the embodiments of the present invention are not described in detail here.

[0170] Correspondingly, Fig. 9 The layout structure shown can also be made with Figure 3 , Figure 5 or Figure 7 Similar improvements, that is, not setting up shielding lines, adding shielding layers, or setting the auxiliary connection lines in each layout structure on the first side of the first and second groups of transistors or on the second side of the third and fourth groups of transistors, etc., are not described in detail in the embodiments of the present invention.

[0171] Furthermore, the embodiment of the present invention can also set three or more channels of chopper circuits according to actual needs, and the design principle is the same as Figure 8-Figure 9 similar.

[0172] In the embodiment of the present invention, two transistors in each group of transistors are arranged to be of the same type, arranged along a first direction and with adjacent ends being the same pole, transistors of the same type are arranged along the first direction, transistors of different types are arranged along the second direction, a phase signal line is connected to the gates of multiple groups of transistors, a first transmission signal line is connected to one of the drain or source of each transistor, and a second transmission signal line is connected to the other of the drain or source of each transistor. Thus, the parasitic capacitance between the phase signal line and the transmission signal line can be reduced, and the circuit performance can be improved.

[0173] Fig.10 FIG. 1 is a flow chart of a layout method of a chopper circuit layout structure according to an embodiment of the present invention. Fig.10 As shown, the layout method of the layout structure of the chopper circuit according to the embodiment of the present invention includes the following steps:

[0174] Step S100, set 4n groups of transistors, each group of transistors includes two transistors, the two transistors are of the same type, the two transistors are arranged along a first direction and the adjacent ends are the same pole, the transistors of the same type are arranged along the first direction, and the transistors of different types are arranged along the second direction, and n is greater than or equal to 1.

[0175] Step S200: Connect a set of phase signal lines to the gate of the transistor.

[0176] Step S300: Connect n groups of first transmission signal lines to one of the drain or source of each of the transistors.

[0177] Step S400: Connect n groups of second transmission signal lines to the other of the drain or the source of each of the transistors.

[0178] In the embodiment of the present invention, two transistors in each group of transistors are arranged to be of the same type, arranged along a first direction and with adjacent ends being the same pole, transistors of the same type are arranged along the first direction, transistors of different types are arranged along the second direction, a phase signal line is connected to the gates of multiple groups of transistors, a first transmission signal line is connected to one of the drain or source of each transistor, and a second transmission signal line is connected to the other of the drain or source of each transistor. Thus, the parasitic capacitance between the phase signal line and the transmission signal line can be reduced, and the circuit performance can be improved.

[0179] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A layout structure of a chopper circuit, characterized in that: The layout structure includes: 4n groups of transistors, each group of transistors includes two transistors, the two transistors are of the same type, the two transistors are arranged along a first direction and adjacent ends have the same pole; a set of phase signal lines connected to the gates of the transistors; n groups of first transmission signal lines connected to one of the drain or source of each of the transistors; n groups of second transmission signal lines connected to the other of the drain or the source of each of the transistors; The transistors of the same type are arranged along a first direction, and the transistors of different types are arranged along a second direction, and n is greater than or equal to 1.

2. The layout structure according to claim 1, characterized in that: The layout structure also includes: A group of shielding lines are arranged on both sides of the phase signal line.

3. The layout structure according to claim 2, characterized in that: n is equal to 1, and the 4n group of transistors includes: A first group of transistors including a first P-type transistor and a second P-type transistor; a second group of transistors including a third P-type transistor and a fourth P-type transistor; A third group of transistors includes a first N-type transistor and a second N-type transistor; The fourth group of transistors includes a third N-type transistor and a fourth N-type transistor.

4. The layout structure according to claim 3, characterized in that: The set of phase signal lines comprises: A first phase signal line connected to the gates of the first N-type transistor, the second P-type transistor, the third P-type transistor and the fourth N-type transistor; The second phase signal line is connected to the gates of the first P-type transistor, the second N-type transistor, the third N-type transistor, and the fourth P-type transistor.

5. The layout structure according to claim 4, characterized in that: The first phase signal line and the second phase signal line are extended along a first direction and are arranged parallel to each other.

6. The layout structure according to claim 5, characterized in that: The set of shielded wires comprises: A first shielded line and a second shielded line, wherein the first phase signal line and the second phase signal line are located between the first shielded line and the second shielded line.

7. The layout structure according to claim 6, characterized in that: The first group of transistors and the second group of transistors are arranged along a first direction on a first side of the first shielding line, and the third group of transistors and the fourth group of transistors are arranged along the first direction on a second side of the second shielding line, wherein the first side of the first shielding line is opposite to the second side, the first side and the second side of the second shielding line are opposite to each other, and the second side of the first shielding line is adjacent to the first side of the second shielding line.

8. The layout structure according to claim 1, characterized in that: The n groups of first transmission signal lines or the n groups of second transmission signal lines are connected to the drains or sources of two transistors in each group of transistors that are adjacent to each other.

9. The layout structure according to claim 3, characterized in that: A group of first transmission signal lines includes a first connection line and a second connection line, wherein the first connection line and the second connection line are parallel and arranged along a second direction, and the first direction is perpendicular to the second direction; A group of second transmission signal lines includes a third connection line and a fourth connection line, wherein the third connection line and the fourth connection line are parallel and arranged along a second direction, and the first direction is perpendicular to the second direction.

10. The layout structure according to claim 9, characterized in that: The first P-type transistor and the second P-type transistor are symmetrically arranged on both sides of the first connecting line, the first N-type transistor and the second N-type transistor are symmetrically arranged on both sides of the first connecting line, the third P-type transistor and the fourth P-type transistor are symmetrically arranged on both sides of the second connecting line, and the third N-type transistor and the fourth N-type transistor are symmetrically arranged on both sides of the second connecting line.

11. The layout structure according to claim 10, characterized in that: The first group of transistors and the third group of transistors are arranged on one side of the third connection line and the fourth connection line, and the second group of transistors and the fourth group of transistors are arranged on the other side opposite to the third connection line and the fourth connection line.

12. The layout structure according to claim 6, characterized in that: The first phase signal line, the second phase signal line, the first shielding line, and the second shielding line are arranged on the same metal connection layer.

13. The layout structure according to claim 12, characterized in that: The layout structure also includes: The shielding layer is a metal connection layer disposed above the first phase signal line, the second phase signal line, the first shielding line, and the second shielding line, and is connected to the first shielding line and the second shielding line through a through hole.

14. The layout structure according to claim 9, characterized in that: The layout structure also includes: A first auxiliary connection line and a second auxiliary connection line extending along a first direction and arranged at a first side of the first group of transistors and the second group of transistors along a second direction; A third auxiliary connection line and a fourth auxiliary connection line extending along the first direction and arranged along the second direction on the second side of the third group of transistors and the fourth group of transistors; The third connection line is connected to the second auxiliary connection line and the third auxiliary connection line, and the fourth connection line is connected to the first auxiliary connection line and the fourth auxiliary connection line.

15. The layout structure according to claim 9, characterized in that: The layout structure also includes: a fifth auxiliary connecting line extending along the first direction; a sixth auxiliary connection line extending along the first direction, arranged in parallel with the fifth auxiliary connection line, and arranged on a first side of the first and second groups of transistors or on a second side of the third and fourth groups of transistors; Wherein, the third connection line is connected to the fifth auxiliary connection line, and the fourth connection line is connected to the sixth auxiliary connection line.

16. The layout structure according to claim 14, characterized in that: The first connection line and the second connection line are input / output signal connection lines, and the third connection line and the fourth connection line are output / input signal connection lines; Wherein, the first connecting line is connected to the source / drain of the first P-type transistor and the second P-type transistor, and is connected to the drain / source of the first N-type transistor and the second N-type transistor; The second connection line is connected to the source / drain of the third P-type transistor and the fourth P-type transistor, and is connected to the drain / source of the third N-type transistor and the fourth N-type transistor; A second auxiliary connection line is connected to the drain / source of the second P-type transistor and the fourth P-type transistor; A third auxiliary connection line is connected to the source / drain of the second N-type transistor and the fourth N-type transistor; A first auxiliary connection line is connected to the drain / source of the first P-type transistor and the third P-type transistor; The fourth auxiliary connection line is connected to the source / drain of the first N-type transistor and the third N-type transistor.

17. The layout structure according to claim 15, characterized in that: The first connection line and the second connection line are input / output signal connection lines, and the third connection line and the fourth connection line are output / input signal connection lines; Wherein, the first connecting line is connected to the source / drain of the first P-type transistor and the second P-type transistor, and is connected to the drain / source of the first N-type transistor and the second N-type transistor; The second connection line is connected to the source / drain of the third P-type transistor and the fourth P-type transistor, and is connected to the drain / source of the third N-type transistor and the fourth N-type transistor; A fifth auxiliary connection line is connected to the drain / source of the second P-type transistor and the fourth P-type transistor, and is connected to the source / drain of the second N-type transistor and the fourth N-type transistor; The sixth auxiliary connection line is connected to the drain / source of the first P-type transistor and the third P-type transistor, and is connected to the source / drain of the first N-type transistor and the third N-type transistor.

18. The layout structure according to claim 1, characterized in that: The phase signal line and the transmission signal line are arranged on different metal connection layers.

19. The layout structure according to claim 18, characterized in that: The phase signal line is arranged in the lowest level metal connection layer, and the transmission signal line is arranged in the highest level metal connection layer.

20. The layout structure according to claim 15, characterized in that: The auxiliary connection line and the phase signal line are arranged in the same metal connection layer, and the distance between the phase signal line and the auxiliary connection line is greater than a predetermined value.

21. The layout structure according to claim 2, characterized in that: n is greater than 1, and the 4n group of transistors includes: n first groups of transistors, each of which includes a first P-type transistor and a second P-type transistor; n second groups of transistors, each second group of transistors comprising a third P-type transistor and a fourth P-type transistor; n third groups of transistors, each of which includes a first N-type transistor and a second N-type transistor; There are n fourth groups of transistors, each of which includes a third N-type transistor and a fourth N-type transistor.

22. A layout method for a chopper circuit layout structure, characterized in that: The method comprises: 4n groups of transistors are arranged, each group of transistors includes two transistors, the two transistors are of the same type, the two transistors are arranged along a first direction and adjacent ends are of the same pole, the transistors of the same type are arranged along the first direction, and the transistors of different types are arranged along the second direction, and n is greater than or equal to 1; connecting a set of phase signal lines to the gate of the transistor; Connecting n groups of first transmission signal lines to one of the drain or source of each of the transistors; The n groups of second transmission signal lines are connected to the other of the drain or the source of each of the transistors.

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