BCD-based integrated longitudinal field plate DMOS device and process

Abstract

The invention discloses a DMOS device and process based on a BCD integrated longitudinal field plate. The integrated longitudinal field plate DMOS device based on the BCD comprises a P-type substrate and a P-type well layer which are sequentially stacked from bottom to top in the vertical direction, and the P-type well layer is divided into a low-voltage region, a medium-voltage region and a high-voltage region which are sequentially arranged from left to right in the horizontal direction. And through integration of the low-voltage region, the medium-voltage region and the high-voltage region, the requirement of a full-voltage range within 200V is met. Under a relatively small chip area, the high-voltage driving circuit can obtain higher current density and lower on-resistance, so that the aim of improving the working efficiency of the circuit is fulfilled. Meanwhile, the full-voltage device can further expand the application range of the circuit designed by the invention.

Description

Technical Field

[0001] The present invention relates to a DMOS device, in particular to a BCD-based integrated longitudinal field plate DMOS device and process. Background Art

[0002] In a prior art BCD-based metal oxide field-effect power transistor and process (CN118471979A), the drain potential of the SGT-NMOS device is limited and can only be connected to the highest potential of the circuit. If an SGT-PMOS device is integrated, the drain of the SGT-PMOS device must be electrically short-circuited with the drain of the SGT-NMOS device, which greatly limits its use. Moreover, this solution only has low-voltage and high-voltage regions, covering the low-voltage range of 3.3V-5V and the high-voltage range of 30-200V, and cannot meet the function of the medium-voltage range of 6-30V. Summary of the Invention

[0003] To overcome the above shortcomings, an embodiment of the present invention provides a BCD-based integrated vertical field plate DMOS device and process, which meets the requirements of the full voltage range within 200V by integrating low-voltage, medium-voltage and high-voltage regions.

[0004] The present invention provides a technical solution: a BCD-based integrated longitudinal field plate DMOS device, comprising a P-type substrate and a P-type well layer stacked vertically from bottom to top, wherein the P-type well layer is divided into a low-voltage region, a medium-voltage region, and a high-voltage region arranged horizontally from left to right; a first P+ region is provided between the low-voltage region and the medium-voltage region, and the first P+ region is isolated from the low-voltage region and the medium-voltage region by a shallow trench; a second P+ region is provided between the medium-voltage region and the high-voltage region, and the second P+ region is isolated from the medium-voltage region and the high-voltage region by a shallow trench; a first N+ region and a third P+ region are further provided on the right side of the high-voltage region, and are arranged horizontally from left to right; the high-voltage region and the first N+ region are isolated by a shallow trench, the first N+ region and the third P+ region are isolated by a shallow trench, and the right side of the third P+ region is also isolated by a shallow trench; The low-voltage area includes low-voltage CMOS devices and Bipolar devices arranged in sequence from left to right along the horizontal direction; the medium-voltage area includes LDPMOS devices and LDNMOS devices arranged in sequence from left to right along the horizontal direction; and the high-voltage area includes SGT-NMOS devices and SGT-PMOS devices arranged in sequence from left to right along the horizontal direction.

[0005] Furthermore, the low-voltage CMOS device includes a PMOS device and an NMOS device arranged in sequence from left to right in the horizontal direction; the bipolar device includes an NPN device and a PNP device arranged in sequence from left to right in the horizontal direction; a fourth P+ region is provided between the low-voltage CMOS device and the bipolar device, and the fourth P+ region is isolated from the low-voltage CMOS device and the bipolar device by a shallow trench; The PMOS device and the NMOS device are isolated by a shallow trench; A fifth P+ region is provided between the NPN device and the PNP device, and the fifth P+ region is isolated from the NPN device and the PNP device by a shallow trench; A sixth P+ region is provided between the LDPMOS device and the LDNMOS device, and the sixth P+ region is isolated from the LDPMOS device and the LDNMOS device by a shallow trench; There is a seventh P+ region and a second N+ region arranged in sequence from left to right along the horizontal direction between the SGT-NMOS device and the SGT-PMOS device, and the SGT-NMOS device, the seventh P+ region, the second N+ region and the SGT-PMOS device are all isolated by shallow trenches.

[0006] Furthermore, the first P+ region, the second P+ region, the third P+ region, the fourth P+ region, the fifth P+ region, the sixth P+ region, and the seventh P+ region are all arranged in an upper portion of the P-type well layer, and the first P+ region, the second P+ region, the third P+ region, the fourth P+ region, the fifth P+ region, the sixth P+ region, and the seventh P+ region are respectively led out through the metal layer as ground terminals; The upper portion of the P-type well layer comprises a first N-well layer, a second N-well layer, a third N-well layer, a fourth N-well layer, a fifth N-well layer, a sixth N-well layer, and a seventh N-well layer in sequence from left to right in the horizontal direction; The second N+ region is disposed at an upper portion of the left side of the seventh N-well layer, and the first N+ region is disposed at an upper portion of the right side of the seventh N-well layer; There is a dielectric insulation layer above the low voltage area, the medium voltage area and the high voltage area.

[0007] Furthermore, the PMOS device includes a first N-type well region constructed in the upper part of the first N-well layer and a first N+ injection region, a first P+ injection region, and a second P+ injection region constructed in the upper part of the first N-type well region and arranged in sequence from left to right in the horizontal direction. Shallow trench isolation is provided on both sides of the first N+ injection region. A first gate dielectric layer is provided above the first N-type well region between the first P+ injection region and the second P+ injection region. A first control gate polycrystalline layer is provided above the first gate dielectric layer. First sidewall dielectric layers are provided on both sides of the first control gate polycrystalline layer and the first gate dielectric layer, and the first sidewall dielectric layers on both sides are respectively located above the first P+ injection region and the second P+ injection region; the first N+ injection region, the first P+ injection region, and the second P+ injection region are respectively led out through the metal layer.

[0008] Furthermore, the NMOS device includes a first P-type well region constructed in the upper part of the first N-well layer and a second N+ injection region, a third N+ injection region, and a third P+ injection region constructed in the upper part of the first P-type well region, which are arranged in sequence from left to right in the horizontal direction. Shallow trench isolation is provided on both sides of the third P+ injection region. A second gate dielectric layer is provided above the first P-type well region between the second N+ injection region and the third N+ injection region. A second control gate polycrystalline layer is provided above the second gate dielectric layer. Second spacer dielectric layers are provided on both sides of the second control gate polycrystalline layer and the second gate dielectric layer, and the second spacer dielectric layers on both sides are respectively located above the second N+ injection region and the third N+ injection region; the second N+ injection region, the third N+ injection region, and the third P+ injection region are respectively led out through the metal layer.

[0009] Furthermore, the NPN device includes a first N-type buried layer constructed below the second N-well layer, a first N+ type buried layer is provided in the first N-type buried layer, a second P-type well region is provided in the upper part of the second N-well layer, a fourth N+ injection region and a fifth N+ injection region are respectively provided in the upper part of the second N-well layer on both sides of the second P-type well region, shallow trench isolation is provided on both sides of the fourth N+ injection region and the fifth N+ injection region, a first N+ type diffusion layer connected to the first N-type buried layer is provided below the fourth N+ injection region, a second N+ type diffusion layer connected to the first N-type buried layer is provided below the fifth N+ injection region, a fourth P+ injection region, a sixth N+ injection region, and a fifth P+ injection region are arranged in sequence from left to right in the horizontal direction in the upper part of the second P-type well region, shallow trench isolation is provided on both sides of the sixth N+ injection region; the fourth N+ injection region, the fifth N+ injection region, the fourth P+ injection region, the sixth N+ injection region, and the fifth P+ injection region are respectively led out through the metal layer.

[0010] Furthermore, the PNP device includes a first P-type buried layer constructed below the third N-well layer, the upper part of the third N-well layer has a third P-type well region, and the upper part of the third N-well layer on both sides of the third P-type well region is respectively provided with a seventh N+ injection region and an eighth N+ injection region, and both sides of the seventh N+ injection region and the eighth N+ injection region are provided with shallow trench isolation, and the upper part of the third P-type well region has a sixth P+ injection region; the seventh N+ injection region, the eighth N+ injection region, and the sixth P+ injection region are respectively led out through the metal layer.

[0011] Furthermore, the LDPMOS device includes a fourth N-well layer, a first P-type well layer is provided on the right side of the upper portion of the fourth N-well layer, a second N-type buried layer is constructed below the fourth N-well layer, a second N+ type buried layer is provided in the second N-type buried layer, a second N-type well region is provided on the left side of the upper portion of the fourth N-well layer, a fourth P-type well region adjacent to the second N-type well region is provided in the upper portion of the first P-type well layer, a ninth N+ injection region and a seventh P+ injection region are arranged in sequence from left to right in the horizontal direction in the upper portion of the second N-type well region, and a shallow Trench isolation, a third gate dielectric layer is provided above the second N-type well region and the fourth P-type well region, a third control gate polycrystalline layer is provided above the third gate dielectric layer, and third sidewall dielectric layers are provided on both sides of the third control gate polycrystalline layer and the third gate dielectric layer; an eighth P+ injection region is provided on the upper right side of the fourth P-type well region, and shallow trench isolation is provided on the left side of the eighth P+ injection region and the area below the third sidewall dielectric layer on the right side of the third control gate polycrystalline layer, and the third sidewall dielectric layer on the left side is located above the seventh P+ injection region; the ninth N+ injection region, the seventh P+ injection region, and the eighth P+ injection region are respectively led out through metal layers.

[0012] Furthermore, the LDNMOS device includes a fifth N-well layer, the upper left side of the fifth N-well layer is a second P-type well layer, a third N-type buried layer is constructed below the fifth N-well layer, the third N-type buried layer has a third N+ type buried layer, the upper part of the second P-type well layer has a fifth P-type well region, the upper part of the fifth N-well layer has a third N-type well region adjacent to the fifth P-type well region; the upper part of the fifth P-type well region has a ninth P+ injection region and a tenth N+ injection region arranged in sequence from left to right in the horizontal direction, the ninth P+ injection region and the tenth N+ injection region are isolated by a shallow trench, and the fifth A fourth gate dielectric layer is provided above the P-type well region and the third N-type well region, a fourth control gate polycrystalline layer is provided above the fourth gate dielectric layer, and fourth spacer dielectric layers are provided on both sides of the fourth control gate polycrystalline layer and the fourth gate dielectric layer; an eleventh N+ injection region is also provided on the upper right side of the third N-type well region, and shallow trench isolation is provided below the fourth spacer dielectric layer on the left side of the eleventh N+ injection region and the right side of the fourth control gate polycrystalline layer, and the fourth spacer dielectric layer on the left side of the fourth control gate polycrystalline layer is located above the tenth N+ injection region; the ninth P+ injection region, the tenth N+ injection region, and the eleventh N+ injection region are respectively led out through metal layers.

[0013] Furthermore, the SGT-NMOS device includes a fourth N-type buried layer constructed below the sixth N-well layer, the fourth N-type buried layer has a fourth N+ type buried layer, the upper parts of both sides of the sixth N-well layer are respectively provided with a twelfth N+ injection region and a thirteenth N+ injection region, both sides of the twelfth N+ injection region and the thirteenth N+ injection region have shallow trench isolation, the lower part of the twelfth N+ injection region has a third N+ type diffusion layer connected to the fourth N-type buried layer, the lower part of the thirteenth N+ injection region has a fourth N+ type diffusion layer connected to the fourth N-type buried layer, the middle upper part of the sixth N-well layer has a first deep trench isolation, the first deep trench isolation has a first field plate polycrystalline layer and a fifth control gate polycrystalline layer, the first field plate polycrystalline layer and the fifth control gate polycrystalline layer are not in contact, the fifth control gate polycrystalline layer has a fifth gate dielectric layer on both sides, and the upper part of the sixth N-well layer on both sides of the first deep trench isolation has a symmetrically arranged sixth P-type well region and a seventh P-type well region. The upper part of the sixth P-type well region has the fourteenth N+ injection region, the tenth P+ injection region, and the fifteenth N+ injection region arranged in sequence from left to right in the horizontal direction. The upper part of the seventh P-type well region has the sixteenth N+ injection region, the eleventh P+ injection region, and the seventeenth N+ injection region arranged in sequence from left to right in the horizontal direction. There is a second deep trench isolation between the shallow trench isolation on the right side of the twelfth N+ injection region and the sixth P-type well region, and the second deep trench isolation has a second field plate polycrystalline layer. There is a third deep trench isolation between the shallow trench isolation on the left side of the thirteenth N+ injection region and the seventh P-type well region, and the third deep trench isolation has a third field plate polycrystalline layer. The twelfth N+ injection region, the thirteenth N+ injection region, and the fifth control gate polycrystalline layer are respectively led out through the metal layer; the fourteenth N+ injection region, the tenth P+ injection region, and the fifteenth N+ injection region are led out through the same metal layer; the sixteenth N+ injection region, the eleventh P+ injection region, and the seventeenth N+ injection region are led out through the same metal layer.

[0014] Furthermore, the SGT-PMOS device includes a fifth N-type buried layer constructed below the seventh N-well layer, and a second P-type buried layer buried between the seventh N-well layer and the fifth N-type buried layer. Above the second P-type buried layer is a third P-type well layer. A twelfth P+ injection region and a thirteenth P+ injection region are respectively provided on the upper parts of both sides of the third P-type well layer. Shallow trench isolation is provided on both sides of the twelfth P+ injection region and the thirteenth P+ injection region. A first P+ type diffusion layer connected to the second P-type buried layer is provided below the twelfth P+ injection region. A second P+ type diffusion layer connected to the second P-type buried layer is provided below the thirteenth P+ injection region. A fourth deep trench isolation is provided in the middle upper part of the third P-type well layer. A fourth field plate polycrystalline layer and a sixth control gate polycrystalline layer are provided in the fourth deep trench isolation. The fourth field plate polycrystalline layer and the sixth control gate polycrystalline layer are not in contact. Sixth gate dielectric layers are provided on both sides of the sixth control gate polycrystalline layer. The upper parts of the third P-type well layer on both sides of the fourth deep trench isolation have symmetrically arranged The fourth N-type well region and the fifth N-type well region, the upper portion of the fourth N-type well region has the fourteenth P+ injection region, the eighteenth N+ injection region, and the fifteenth P+ injection region arranged in sequence from left to right in the horizontal direction, the upper portion of the fifth N-type well region has the sixteenth P+ injection region, the nineteenth N+ injection region, and the seventeenth P+ injection region arranged in sequence from left to right in the horizontal direction, the fifth deep trench isolation is provided between the shallow trench isolation on the right side of the twelfth P+ injection region and the fourth N-type well region, and the fifth deep trench isolation has the fifth The field plate polycrystalline layer, the shallow trench isolation on the left side of the thirteenth P+ injection region and the fifth N-type well region have a sixth deep trench isolation, and the sixth field plate polycrystalline layer is provided in the sixth deep trench isolation; the twelfth P+ injection region, the thirteenth P+ injection region, and the sixth control gate polycrystalline layer are respectively led out through the metal layer; the fourteenth P+ injection region, the eighteenth N+ injection region and the fifteenth P+ injection region are led out through the same metal layer; the sixteenth P+ injection region, the nineteenth N+ injection region and the seventeenth P+ injection region are led out through the same metal layer.

[0015] Furthermore, the LDPMOS device also has a first metal layer as a source field plate, which is arranged on the dielectric insulation layer and located between the third sidewall dielectric layer on the right side of the third control gate polycrystalline layer and the eighth P+ injection region, thereby increasing the operating voltage of the LDPMOS device.

[0016] Furthermore, the LDNMOS device also has a second metal layer as a source field plate, which is arranged on the dielectric insulation layer and located between the fourth sidewall dielectric layer on the right side of the fourth control gate polycrystalline layer and the eleventh N+ injection region, thereby improving the operating voltage of the LDNMOS device.

[0017] Furthermore, a first field plate polycrystalline layer is provided in the lower part of the first deep trench isolation, and a fifth control gate polycrystalline layer is provided in the upper part of the first deep trench isolation, and the first field plate polycrystalline layer and the fifth control gate polycrystalline layer do not contact each other; the cross-section of the first field plate polycrystalline layer is rectangular or has stepped steps with a larger bottom and a smaller top, and the stepped steps are continuous or discontinuous.

[0018] Furthermore, a fourth field plate polycrystalline layer is provided in the lower part of the fourth deep trench isolation, and a sixth control gate polycrystalline layer is provided in the upper part of the fourth deep trench isolation, and the fourth field plate polycrystalline layer and the sixth control gate polycrystalline layer do not contact each other; the cross-section of the fourth field plate polycrystalline layer is rectangular or has stepped steps with a larger bottom and a smaller top, and the stepped steps are continuous or discontinuous.

[0019] Furthermore, the first field plate polycrystalline layer is arranged along the depth direction of the first deep trench isolation, the fifth control gate polycrystalline layer is arranged on the upper part of the first deep trench isolation and on both sides of the first field plate polycrystalline layer, and the fifth gate dielectric layer is arranged on both sides of the fifth control gate polycrystalline layer.

[0020] Furthermore, the fourth field plate polycrystalline layer is arranged along the depth direction of the fourth deep trench isolation, the sixth control gate polycrystalline layer is arranged on the upper part of the fourth deep trench isolation and on both sides of the fourth field plate polycrystalline layer, and the sixth gate dielectric layer is arranged on both sides of the sixth control gate polycrystalline layer.

[0021] Furthermore, a first field plate polycrystalline layer is disposed in the lower portion of the first deep trench isolation, and two fifth control gate polycrystalline layers are symmetrically disposed on both sides of the upper portion of the first deep trench isolation. The first field plate polycrystalline layer and the fifth control gate polycrystalline layer do not contact each other.

[0022] Furthermore, a fourth field plate polycrystalline layer is disposed in the lower portion of the fourth deep trench isolation, and two sixth control gate polycrystalline layers are symmetrically disposed on both sides of the upper portion of the fourth deep trench isolation. The fourth field plate polycrystalline layer and the sixth control gate polycrystalline layer do not contact each other.

[0023] Furthermore, a fourth P-type well layer is provided below the first deep trench isolation, and the fourth P-type well layer is in contact with the first field plate polycrystalline layer.

[0024] Furthermore, an eighth N-well layer is provided below the fourth deep trench isolation, and the eighth N-well layer is in contact with the fourth field plate polycrystalline layer.

[0025] A process for preparing the aforementioned BCD-based integrated vertical field plate DMOS device comprises the following steps: (1) On a P-type substrate, N-buried layers of NPN devices, PNP devices, LDPMOS devices, LDNMOS devices, SGT-NMOS devices, and SGT-PMOS devices, N+buried layers of NPN devices, LDPMOS devices, LDNMOS devices, and SGT-NMOS devices, and P+buried layers of PNP devices and SGT-PMOS devices are fabricated respectively; That is: a first N-type buried layer, a second N-type buried layer, a third N-type buried layer, a fourth N-type buried layer, and a fifth N-type buried layer; a first N+ type buried layer, a second N+ type buried layer, a third N+ type buried layer, and a fourth N+ type buried layer, for reducing drain resistance; a first P-type buried layer and a second P-type buried layer, for reducing drain resistance; By adopting the N-buried layer, the drain potential of the SGT-NMOS device and SGT-PMOS device is free, allowing the circuits developed using this technology to achieve more functional requirements, such as full-bridge drive circuits, DC / DC control circuits, AC / DC drive circuits and other design requirements; (2) Growing an intrinsic silicon layer or an N-type doped silicon layer or a P-type doped silicon layer with a thickness of 3-10 μm on the surface of the chip after the N- buried layer, N+ buried layer and P+ buried layer are completed; (3) Through pattern masking and ion implantation of B11, the P-well region of the entire DMOS device, the P-well region of the LDPMOS device, the P-well region of the LDNMOS device, and the P-well region of the SGT-PMOS device are produced; That is: a P-type well layer, a first P-type well layer, a second P-type well layer, and a third P-type well layer; The P-type well layer serves as a transition layer connecting to the P-type substrate; the first P-type well layer serves as an adjustment region for the potential freedom of the drain of the LDPMOS device; the second P-type well layer serves as an adjustment region for the potential freedom of the source of the LDPMOS device; and the third P-type well layer serves as a drift region of the SGT-PMOS device. (4) Through pattern mask and ion implantation of B11, the P+ type diffusion region of the SGT-PMOS device is produced; That is: the first P+ type diffusion layer, the second P+ type diffusion layer; (5) Through pattern mask and ion implantation of P, N-well regions of CMOS devices, NPN devices, PNP devices, LDPMOS devices, LDNMOS devices, SGT-NMOS devices, and SGT-PMOS devices are produced; That is: a first N-well layer, a second N-well layer, a third N-well layer, a fourth N-well layer, a fifth N-well layer, a sixth N-well layer, and a seventh N-well layer; The first N-well layer serves as an electrical isolation layer between the low-voltage CMOS device and the P-type substrate and the P-type well layer; the second N-well layer serves as the collector region of the NPN device; the third N-well layer serves as the base region of the PNP device; the fourth N-well layer serves as an electrical isolation layer between the LDPMOS device and the P-type substrate and the P-type well layer; the fifth N-well layer serves as an electrical isolation layer between the LDNMOS device and the P-type substrate and the P-type well layer; the sixth N-well layer serves as a drift region of the SGT-NMOS device; and the seventh N-well layer serves as an electrical isolation layer between the SGT-PMOS device and the P-type substrate and the P-type well layer. (6) Through pattern mask and ion implantation of P, N+ diffusion regions of NPN devices and SGT-NMOS devices are produced; That is: a first N+ type diffusion layer, a second N+ type diffusion layer, a third N+ type diffusion layer, and a fourth N+ type diffusion layer; (7) Using a pattern mask and dry etching method, silicon trenches of SGT-NMOS and SGT-PMOS devices are produced with a depth of 1-5 μm. That is: second deep trench isolation, first deep trench isolation, third deep trench isolation, fifth deep trench isolation, fourth deep trench isolation, sixth deep trench isolation; (8) Thermally oxidize the silicon trench, then deposit polysilicon, and selectively etch the polysilicon to produce the field plate polycrystalline layer of the SGT-NMOS device and the SGT-PMOS device; That is: the second field plate polycrystalline layer, the first field plate polycrystalline layer, the third field plate polycrystalline layer, the fifth field plate polycrystalline layer, the fourth field plate polycrystalline layer, and the sixth field plate polycrystalline layer; The first field plate polycrystalline layer serves as the source field plate of the SGT-NOMS device; the second field plate polycrystalline layer and the third field plate polycrystalline layer serve as the field limiting ring of the SGT-NOMS device; the fourth field plate polycrystalline layer serves as the source field plate of the SGT-POMS device; the fifth field plate polycrystalline layer and the sixth field plate polycrystalline layer serve as the field limiting ring of the SGT-POMS device; (9) Using a graphic mask and dry etching to create shallow trench isolation; (10) In the N-well region, a pattern mask is used and BF2 or B11 is ion-implanted to produce a P-type well region of an NPN device, a PNP device, an LDPMOS device, an LDNMOS device, and an SGT-NMOS device; That is: a first P-type well region, a second P-type well region, a third P-type well region, a fourth P-type well region, a fifth P-type well region, a sixth P-type well region, and a seventh P-type well region; The first P-type well region serves as the channel region of the NOMS device; the second P-type well region serves as the base region of the NPN device; the third P-type well region serves as the emitter region of the PNP device; the fourth P-type well region serves as the drift region of the LDPMOS device; the fifth P-type well region serves as the channel region of the LDNMOS device; the sixth and seventh P-type well regions serve as the channel regions of the SGT-NMOS device; (11) In the P-well region, P or As is ion-implanted through a patterned mask to produce an N-type well region of a PMOS device, a LDPMOS device, a LDNMOS device, or a SGT-PMOS device; That is: a first N-type well region, a second N-type well region, a third N-type well region, a fourth N-type well region, and a fifth N-type well region; The first N-type well region serves as the channel region of the PMOS device; the second N-type well region serves as the channel region of the LDPMOS device; the third N-type well region serves as the drift region of the LDNMOS device; the fourth N-type well region and the fifth N-type well region serve as the channel region of the SGT-PMOS device; (12) Surface sacrificial oxidation to improve silicon surface quality; (13) Forming the gate dielectric layer of PMOS devices, NMOS devices, LDPMOS devices, LDNMOS devices, SGT-NMOS devices, and SGT-PMOS devices by thermal oxidation; That is: a first gate dielectric layer, a second gate dielectric layer, a third gate dielectric layer, a fourth gate dielectric layer, a fifth gate dielectric layer, and a sixth gate dielectric layer; (14) Depositing polysilicon and forming control gate polysilicon layers of PMOS devices, NMOS devices, LDPMOS devices, LDNMOS devices, SGT-NMOS devices, and SGT-PMOS devices through pattern masking and etching; That is: a first control gate polycrystalline layer, a second control gate polycrystalline layer, a third control gate polycrystalline layer, a fourth control gate polycrystalline layer, a fifth control gate polycrystalline layer, and a sixth control gate polycrystalline layer; (15) Through the growth and etching technology of different materials, the sidewall regions of self-aligned implanted PMOS devices, NMOS devices, LDPMOS devices, and LDNMOS devices are produced; That is: a first spacer dielectric layer, a second spacer dielectric layer, a third spacer dielectric layer, and a fourth spacer dielectric layer; (16) Using a patterned mask, the P+ injection region and N+ injection region of a PMOS device, an NMOS device, an NPN device, a PNP device, an LDPMOS device, an LDNMOS device, an SGT-NMOS device, and an SGT-PMOS device are produced; That is: the first P+ region, the second P+ region, the third P+ region, the fourth P+ region, the fifth P+ region, the sixth P+ region, the seventh P+ region, the first N+ region, and the second N+ region; (17) Produce a dielectric insulating layer, and produce a lead hole layer through pattern masking and etching; (18) Make the metal lead layer.

[0026] The beneficial effects of the present invention are: By integrating low-voltage, medium-voltage, and high-voltage regions, the full voltage range up to 200V is met. With a relatively small chip area, the high-voltage drive circuit can achieve higher current density and lower on-resistance, thereby improving circuit efficiency. Furthermore, the full-voltage device can further expand the application range of the circuits designed according to this invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 This is a schematic diagram of the overall structure of the BCD integrated vertical field plate DMOS device of the present invention; Figure 2 Schematic diagram of the structure of a low-voltage CMOS device in a low-voltage region of the present invention; Figure 3 Schematic diagram of the structure of the Bipolar device in the low-voltage region of the present invention; Figure 4 Schematic diagram of the structure of the LDPMOS device and the LDNMOS device in the medium voltage region of Example 1 of the present invention; Figure 5 Schematic diagram of the structure of the SGT-NMOS device in the high voltage region of Example 1 of the present invention; Figure 6 Schematic diagram of the structure of the SGT-PMOS device in the high voltage region of Example 1 of the present invention; Figure 7 Schematic diagram of the structure of the LDPMOS device and the LDNMOS device in the medium voltage region of Example 2 of the present invention; Figure 8 Schematic diagram of the structure of the SGT-NMOS device in the high voltage region of Example 3 of the present invention; Figure 9 Schematic diagram of the structure of the SGT-PMOS device in the high voltage region of Example 3 of the present invention; Figure 10 Schematic diagram of the structure of the SGT-NMOS device in the high voltage region of Example 4 of the present invention; Figure 11 Schematic diagram of the structure of the SGT-PMOS device in the high voltage region of Example 4 of the present invention; Figure 12Schematic diagram of the structure of the SGT-NMOS device in the high voltage region of Example 5 of the present invention; Figure 13 Schematic diagram of the structure of the SGT-PMOS device in the high voltage region of Example 5 of the present invention; Figure 14 Schematic diagram of the structure of the SGT-NMOS device in the high voltage region of Example 6 of the present invention; Figure 15 Schematic diagram of the structure of the SGT-PMOS device in the high voltage region of Example 6 of the present invention; Figure 16 Schematic diagram of the structure of the SGT-NMOS device in the high voltage region of Example 7 of the present invention; Figure 17 Schematic diagram of the structure of the SGT-PMOS device in the high voltage region of Example 7 of the present invention; Among them, P-type substrate A, P-type well layer B, first P-type well layer B1, second P-type well layer B2, third P-type well layer B3, fourth P-type well layer B4, first N-well layer C1, second N-well layer C2, third N-well layer C3, fourth N-well layer C4, fifth N-well layer C5, sixth N-well layer C6, seventh N-well layer C7, eighth N-well layer C8, first P+ region a1, second P+ region a2, third P+ region a3, fourth P+ region a4, fifth P+ region a5, sixth P+ region a6, seventh P+ region a7, first N+ region b1, second N+ region b2, low voltage region 1, low voltage CMOS device 11, PMOS device 111, first N-type well region 1111, first N+ implantation region 1112, first P+ implantation region 1113, first spacer dielectric layer 1114, first control gate polycrystalline layer 1115, first gate dielectric layer 1116, second P+ implantation region 1117, NMOS device 112, first P-type well region 1121, second N+ implantation region 1122, second spacer dielectric layer 1123, second control gate polycrystalline layer 1124, second gate dielectric layer 1125, third N+ implantation region 1126, third P+ implantation region 1127, Bipolar device 12, NPN device 121, first N-type buried layer 1211, first N+ buried layer 1212, first N+ diffusion layer 1213, fourth N+ implantation region 1214, second P-type well region 1215, fourth P+ implantation region 1216, sixth N+ implantation region 1217, fifth P+ implantation region 1218, second N+ diffusion layer 1219, fifth N+ implantation region 12110, PNP device 122, first P-type buried layer 1221, third P-type well region 1222, seventh N+ implantation region 1223, sixth P+ implantation region 1224, eighth N+ implantation region 1225, medium voltage region 2, LDPMOS device 21, second N-type buried layer 211, second N+ buried layer 212, second N-type well region 213, ninth N+ implantation region 214, seventh P+ implantation region 215, third spacer dielectric layer 216, third control gate polycrystalline layer 217, third gate dielectric layer 218, fourth P-type well region 219, eighth P+ implantation region 211 0, first metal layer 2111, LDNMOS device 22, third N-type buried layer 221, third N+ type buried layer 222, fifth P-type well region 223, ninth P+ implantation region 224, tenth N+ implantation region 225, fourth spacer dielectric layer 226, fourth control gate polycrystalline layer 227, fourth gate dielectric layer 228, third N-type well region 229, eleventh N+ implantation region 2210, second metal layer 2211, high voltage region 3, SGT-NMOS device 31, fourth N-type buried layer 311, fourth N+ type buried layer 312, third N+ type diffusion layer 313, twelfth N+ implantation region 314, second deep trench isolation 315, second field plate polycrystalline layer 316, sixth P-type well region 317, fourteenth N+ implantation region 318,tenth P+ implantation region 319, fifteenth N+ implantation region 3110, first deep trench isolation 3111, first field plate polycrystalline layer 3112, fifth gate dielectric layer 3113, fifth control gate polycrystalline layer 3114, seventh P-type well region 3115, sixteenth N+ implantation region 3116, eleventh P+ implantation region 3117, seventeenth N+ implantation region 3118, third deep trench isolation 3119, third field plate polycrystalline layer 3120, fourth N+ type diffusion layer 3121, thirteenth N+ implantation region 3122, SGT-PMOS device 32, fifth N-type buried layer 321, second P-type buried layer 322, first P+ type diffusion layer 323, twelfth P+ implantation region 324, fifth deep trench isolation 325, fifth field plate polycrystalline layer 326, fourth N-type well region 327, fourteenth P+ implantation region 328, eighteenth N+ implantation region 329, fifteenth P+ implantation region 3210, fourth deep trench isolation 3211, fourth field plate polycrystalline layer 3212, sixth gate dielectric layer 3213, sixth control gate polycrystalline layer 3214, fifth N-type well region 3215, sixteenth P+ implantation region 3216, nineteenth N+ implantation region 3217, seventeenth P+ implantation region 3218, sixth deep trench isolation 3219, sixth field plate polycrystalline layer 3220, second P+ type diffusion layer 3221, thirteenth P+ implantation region 3222. DETAILED DESCRIPTION

[0028] To further illustrate the technical means and effectiveness of the present invention in achieving its intended objectives, the following, in conjunction with the accompanying drawings and preferred embodiments, details the specific implementation, structure, features, and effectiveness of the present invention. With a relatively small chip area, the high-voltage drive circuit can achieve higher current density and lower on-resistance, thereby improving circuit efficiency. Furthermore, full-voltage devices can further expand the application range of the circuits designed according to the present invention.

[0029] This application meets the requirements of the full voltage range within 200V by integrating low-voltage, medium-voltage and high-voltage areas.

[0030] The embodiments of the present invention are further described below with reference to a number of embodiments.

[0031] Example 1

[0032] like Figure 1 — Figure 6A BCD-based integrated longitudinal field plate DMOS device includes a P-type substrate A and a P-type well layer B stacked vertically from bottom to top, the P-type well layer B being divided into a low-voltage region 1, a medium-voltage region 2, and a high-voltage region 3 arranged horizontally from left to right; a first P+ region a1 is provided between the low-voltage region 1 and the medium-voltage region 2, and the first P+ region a1 is isolated from the low-voltage region 1 and the medium-voltage region 3 by a shallow trench; a second P+ region a2 is provided between the medium-voltage region 2 and the high-voltage region 3, and the second P+ region a2 is isolated from the medium-voltage region 2 and the high-voltage region 3 by a shallow trench; a first N+ region b1 and a third P+ region a3 are further provided on the right side of the high-voltage region 3, and the high-voltage region 3 is isolated from the first N+ region b1 by a shallow trench, and the first N+ region b1 and the third P+ region a3 are isolated by a shallow trench, and the right side of the third P+ region a3 also has a shallow trench isolation; The low-voltage region 1 includes a low-voltage CMOS device 11 and a bipolar device 12 arranged in sequence from left to right in the horizontal direction; the medium-voltage region 2 includes an LDPMOS device 21 and an LDNMOS device 22 arranged in sequence from left to right in the horizontal direction; and the high-voltage region 3 includes an SGT-NMOS device 31 and an SGT-PMOS device 32 arranged in sequence from left to right in the horizontal direction.

[0033] The low-voltage CMOS device 11 includes a PMOS device 111 and an NMOS device 112 arranged in sequence from left to right in the horizontal direction; the bipolar device 12 includes an NPN device 121 and a PNP device 122 arranged in sequence from left to right in the horizontal direction; a fourth P+ region a4 is provided between the low-voltage CMOS device 11 and the bipolar device 12, and the fourth P+ region a4 is isolated from the low-voltage CMOS device 11 and the bipolar device 12 by a shallow trench; The PMOS device 111 and the NMOS device 112 are isolated by a shallow trench; A fifth P+ region a4 is provided between the NPN device 121 and the PNP device 122 , and the fifth P+ region a5 is isolated from the NPN device 121 and the PNP device 122 by a shallow trench; A sixth P+ region a6 is provided between the LDPMOS device 21 and the LDNMOS device 22 , and the sixth P+ region a6 is isolated from the LDPMOS device 21 and the LDNMOS device 22 by a shallow trench; A seventh P+ region a7 and a second N+ region b2 are arranged horizontally from left to right between the SGT-NMOS device 31 and the SGT-PMOS device 32. The SGT-NMOS device 31, the seventh P+ region a7, the second N+ region b2, and the SGT-PMOS device 32 are isolated by shallow trenches. The first P+ region a1, the second P+ region a2, the third P+ region a3, the fourth P+ region a4, the fifth P+ region a5, the sixth P+ region a6 and the seventh P+ region a7 are all arranged in the upper part of the P-type well layer B, and the first P+ region a1, the second P+ region a2, the third P+ region a3, the fourth P+ region a4, the fifth P+ region a5, the sixth P+ region a6 and the seventh P+ region a7 are respectively led out through the metal layer as ground terminals; The upper part of the P-type well layer B includes the first N-well layer C1, the second N-well layer C2, the third N-well layer C3, the fourth N-well layer C4, the fifth N-well layer C5, the sixth N-well layer C6, and the seventh N-well layer C7 from left to right along the horizontal direction.

[0034] The PMOS device 111 includes a first N-type well region 1111 constructed in an upper portion of the first N-well layer C1, and a first N+ implant region 1112, a first P+ implant region 1113, and a second P+ implant region 1117 constructed in an upper portion of the first N-type well region 1111, which are arranged horizontally from left to right. Shallow trench isolation is provided on both sides of the first N+ implant region 1112. A first gate dielectric layer 1116 is provided above the first N-type well region 1111 between the first P+ implant region 1113 and the second P+ implant region 1117. A first control gate polycrystalline layer 11115 is provided above the first gate dielectric layer 1116. First spacer dielectric layers 1114 are provided on both sides of the first control gate polycrystalline layer 1115 and the first gate dielectric layer 1116, and the first spacer dielectric layers 1114 on both sides are respectively located above the first P+ implant region 1113 and the second P+ implant region 1117. The NMOS device 112 includes a first P-type well region 1121 constructed in an upper portion of the first N-well layer C1, and a second N+ implant region 1122, a third N+ implant region 1126, and a third P+ implant region 1127 constructed in an upper portion of the first P-type well region 1121, which are arranged horizontally from left to right. Shallow trench isolation is provided on both sides of the third P+ implant region 1127. A second gate dielectric layer 1125 is provided above the first P-type well region 1121 between the second N+ implant region 1122 and the third N+ implant region 1126. A second control gate polycrystalline layer 1124 is provided above the second gate dielectric layer 1125. Second spacer dielectric layers 1123 are provided on both sides of the second control gate polycrystalline layer 1124 and the second gate dielectric layer 1125. The second spacer dielectric layers 1123 on both sides are located above the second N+ implant region 1122 and the third N+ implant region 1126, respectively. The NPN device 121 includes a first N-type buried layer 1211 constructed below the second N-well layer C2, a first N+ type buried layer 1212 is provided in the first N-type buried layer 1211, a second P-type well region 1215 is provided in the upper portion of the second N-well layer C2, a fourth N+ injection region 1214 and a fifth N+ injection region 12110 are provided in the upper portion of the second N-well layer C2 on both sides of the second P-type well region 1215, and shallow grooves are provided on both sides of the fourth N+ injection region 1214 and the fifth N+ injection region 12110. Isolation: a first N+ type diffusion layer 1213 connected to the first N-type buried layer 1211 is provided below the fourth N+ injection region 1214; a second N+ type diffusion layer 1219 connected to the first N-type buried layer 1211 is provided below the fifth N+ injection region 12110; a fourth P+ injection region 1216, a sixth N+ injection region 1217, and a fifth P+ injection region 1218 are arranged horizontally from left to right in the upper portion of the second P-type well region 1215; and shallow trench isolation is provided on both sides of the sixth N+ injection region 1217; The PNP device 122 includes a first P-type buried layer 1221 constructed below the third N-well layer C3. The third P-type well region 1222 is formed in the upper portion of the third N-well layer C3. A seventh N+ implantation region 1223 and an eighth N+ implantation region 1225 are respectively provided in the upper portion of the third N-well layer C3 on both sides of the third P-type well region 1222. Shallow trench isolation is formed on both sides of the seventh N+ implantation region 1223 and the eighth N+ implantation region 1225. A sixth P+ implantation region 1224 is formed in the upper portion of the third P-type well region 1222. The LDPMOS device 21 includes a fourth N-well layer C4, a first P-type well layer B1 is provided on the right side of the upper portion of the fourth N-well layer C4, a second N-type buried layer 211 is constructed below the fourth N-well layer C4, a second N+ type buried layer 212 is provided in the second N-type buried layer 211, a second N-type well region 213 is provided on the left side of the upper portion of the fourth N-well layer C4, a fourth P-type well region 2119 adjacent to the second N-type well region 213 is provided in the upper portion of the first P-type well layer B1, a ninth N+ implantation region 215 and a seventh P+ implantation region 215, a ninth N+ implantation region 214 and a seventh P+ implantation region 215 are arranged in sequence from left to right in the horizontal direction in the upper portion of the second N-well region 213, The P+ implant regions 215 are isolated by shallow trenches. A third gate dielectric layer 218 is located above the second N-type well region 213 and the fourth P-type well region 2119. A third control gate polycrystalline layer 217 is located above the third gate dielectric layer 218. Third spacer dielectric layers 216 are located on both sides of the third control gate polycrystalline layer 217 and the third gate dielectric layer 218. An eighth P+ implant region 2110 is located on the upper right side of the fourth P-type well region 219. A shallow trench is formed between the left side of the eighth P+ implant region 2110 and the area below the third spacer dielectric layer 216 on the right side of the third control gate polycrystalline layer 217. The left side of the third spacer dielectric layer 216 is located above the seventh P+ implant region 215. The LDNMOS device 22 includes a fifth N-well layer C5, the upper left side of the fifth N-well layer C5 is the second P-type well layer B2, a third N-type buried layer 221 is constructed below the fifth N-well layer C5, the third N-type buried layer 221 has a third N+ type buried layer 222, the upper part of the second P-type well layer B2 has a fifth P-type well region 223, the upper part of the fifth N-well layer C5 has a third N-type well region 229 adjacent to the fifth P-type well region 223; the upper part of the fifth P-type well region 223 has a ninth P+ injection region 224 and a tenth N+ injection region 225 arranged in sequence from left to right in the horizontal direction, the ninth P+ injection region 224 and the tenth N+ injection region 225 are arranged in sequence from left to right in the horizontal direction, and the ninth P+ injection region 224 and the tenth N+ injection region 225 are arranged in sequence from left to right in the horizontal direction. 5 are isolated by shallow trenches, a fourth gate dielectric layer 228 is provided above the fifth P-type well region 223 and the third N-type well region 229, a fourth control gate polycrystalline layer 227 is provided above the fourth gate dielectric layer 228, and fourth spacer dielectric layers 226 are provided on both sides of the fourth control gate polycrystalline layer 227 and the fourth gate dielectric layer 228; an eleventh N+ implantation region 2210 is further provided on the upper right side of the third N-type well region 229, and shallow trench isolation is provided between the left side of the eleventh N+ implantation region 2210 and the fourth spacer dielectric layer 226 on the right side of the fourth control gate polycrystalline layer 227. The fourth spacer dielectric layer 226 on the left side of the fourth control gate polycrystalline layer 227 is located above the tenth N+ implantation region 225; The SGT-NMOS device 31 includes a fourth N-type buried layer 311 constructed below the sixth N-well layer C6, a fourth N+ type buried layer 312 is provided in the fourth N-type buried layer 311, a twelfth N+ injection region 314 and a thirteenth N+ injection region 3122 are respectively provided on both sides of the sixth N-well layer C6, shallow trench isolation is provided on both sides of the twelfth N+ injection region 314 and the thirteenth N+ injection region 3122, and a fourth N-type buried layer 312 is provided below the twelfth N+ injection region 314. 1, a fourth N+ type diffusion layer 3121 connected to the fourth N-type buried layer 311 is provided below the thirteenth N+ injection region 3122, a first deep trench isolation 3111 is provided in the middle upper portion of the sixth N-well layer C6, a first field plate polycrystalline layer 3112 and a fifth control gate polycrystalline layer 3114 are provided in the first deep trench isolation 3111, the first field plate polycrystalline layer 3112 and the fifth control gate polycrystalline layer 3114 are not in contact, and the fifth control gate polycrystalline layer 3114 has The fifth gate dielectric layer 3113 and the sixth N-well layer C6 on both sides of the first deep trench isolation 3111 have a symmetrically arranged sixth P-type well region 317 and a seventh P-type well region 3115 in the upper portion thereof. The upper portion of the sixth P-type well region 317 has a fourteenth N+ injection region 318, a tenth P+ injection region 319, and a fifteenth N+ injection region 3110 arranged in sequence from left to right in the horizontal direction. The upper portion of the seventh P-type well region 3115 has a sixteenth N+ injection region 319, and a fifteenth N+ injection region 3110 arranged in sequence from left to right in the horizontal direction. region 3116, an eleventh P+ implantation region 3117, a seventeenth N+ implantation region 3118, a second deep trench isolation 315 is provided between the shallow trench isolation on the right side of the twelfth N+ implantation region 314 and the sixth P-type well region 317, a second field plate polycrystalline layer 316 is provided in the second deep trench isolation 315, a third deep trench isolation 3119 is provided between the shallow trench isolation on the left side of the thirteenth N+ implantation region 3122 and the seventh P-type well region 3115, a third field plate polycrystalline layer 3120 is provided in the third deep trench isolation 3119; The SGT-PMOS device 32 includes a fifth N-type buried layer 321 constructed below the seventh N-well layer C7, and a second P-type buried layer 322 buried between the seventh N-well layer C7 and the fifth N-type buried layer 321. Above the second P-type buried layer 322 is a third P-type well layer B3. A twelfth P+ injection region 324 and a thirteenth P+ injection region 3222 are respectively provided on both sides of the upper portion of the third P-type well layer B3. Shallow trench isolation is provided on both sides of the twelfth P+ injection region 324 and the thirteenth P+ injection region 3222. A first P+ type diffusion layer 323 connected to the second P-type buried layer 322 is provided below the twelfth P+ injection region 324. A second P+ type diffusion layer 3221 connected to the second P-type buried layer 322 is provided below the thirteenth P+ injection region 3222. A fourth deep trench isolation 3211 is provided in the upper middle portion of the third P-type well layer B3. A fourth field plate polycrystalline layer 3212 and a sixth control gate polycrystalline layer 3214 are provided in the fourth deep trench isolation 3211. The fourth field plate polycrystalline layer 3212 and the sixth control gate polycrystalline layer 3214 do not contact each other. The sixth control gate polycrystalline layer 3214 has a sixth gate dielectric layer 3213 on both sides, the upper portion of the third P-type well layer B3 on both sides of the fourth deep trench isolation 3211 has a symmetrically arranged fourth N-type well region 327 and a fifth N-type well region 3215, the upper portion of the fourth N-type well region 327 has a fourteenth P+ injection region 328, an eighteenth N+ injection region 329, and a fifteenth P+ injection region 3210 arranged in sequence from left to right in the horizontal direction, and the upper portion of the fifth N-type well region 3215 has a fourteenth P+ injection region 328, an eighteenth N+ injection region 329, and a fifteenth P+ injection region 3210 arranged in sequence from left to right in the horizontal direction. a sixteenth P+ implant region 3216, a nineteenth N+ implant region 3217, and a seventeenth P+ implant region 3218 in the row; a fifth deep trench isolation 325 is provided between the shallow trench isolation on the right side of the twelfth P+ implant region 324 and the fourth N-type well region 327; a fifth field plate polycrystalline layer 326 is provided in the fifth deep trench isolation 325; a sixth deep trench isolation 3219 is provided between the shallow trench isolation on the left side of the thirteenth P+ implant region 3222 and the fifth N-type well region 3215; a sixth field plate polycrystalline layer 3220 is provided in the sixth deep trench isolation 3219; The second N+ region b2 is provided at the upper left portion of the seventh N-well layer C7, and the first N+ region b1 is provided at the upper right portion of the seventh N-well layer; A dielectric insulating layer D is provided above the low voltage area 1, the medium voltage area 2 and the high voltage area 3; a first N+ injection area 1112, a first P+ injection area 1113, a second N+ injection area 1122, a second P+ injection area 1117, a third N+ injection area 1126, a third P+ injection area 1127, a fourth N+ injection area 1214, a fourth P+ injection area 1216, a fifth N+ injection area 12110, a fifth P+ injection area 1218, a sixth N+ injection area 1217, a sixth P+ injection area 1224, a seventh N+ injection area 1223, a seventh P+ injection area 215, an eighth N+ injection area 1225, an eighth P+ injection area 2110, a ninth N+ injection area 214, a ninth P+ injection area 224, a tenth N+ injection area 225, an eleventh N+ injection area 2210, and a tenth The second N+ injection region 314, the twelfth P+ injection region 324, the thirteenth N+ injection region 3122, the thirteenth P+ injection region 3222, the fifth control gate polycrystalline layer 3114, and the sixth control gate polycrystalline layer 3214 are respectively led out through the metal layer; the fourteenth N+ injection region 318, the tenth P+ injection region 319 and the fifteenth N+ injection region 3110 are led out through the same metal layer; the sixteenth N+ injection region 3116, the eleventh P+ injection region 3117 and the seventeenth N+ injection region 3118 are led out through the same metal layer; the fourteenth P+ injection region 328, the eighteenth N+ injection region 329 and the fifteenth P+ injection region are led out through the same metal layer; the sixteenth P+ injection region 3216, the nineteenth N+ injection region 3217 and the seventeenth P+ injection region 3218 are led out through the same metal layer.

[0035] A first field plate polycrystalline layer 3112 is provided at the lower portion of the first deep trench isolation 3111, and a fifth control gate polycrystalline layer 3114 is provided at the upper portion of the first deep trench isolation 3111, and the first field plate polycrystalline layer 3112 and the fifth control gate polycrystalline layer 3114 are not in contact with each other; a fourth field plate polycrystalline layer 3212 is provided at the lower portion of the fourth deep trench isolation 3211, and a sixth control gate polycrystalline layer 3214 is provided at the upper portion of the fourth deep trench isolation 3211, and the fourth field plate polycrystalline layer 3212 and the sixth control gate polycrystalline layer 3214 are not in contact with each other; the cross-section of the first field plate polycrystalline layer 3212 is rectangular.

[0036] This embodiment is manufactured using the following process: A process for preparing the aforementioned BCD-based integrated vertical field plate DMOS device comprises the following steps: (1) On a P-type substrate A, N-buried layers of the NPN device 121, the PNP device 122, the LDPMOS device 21, the LDNMOS device 22, the SGT-NMOS device 31, and the SGT-PMOS device 32; N+buried layers of the NPN device 121, the LDPMOS device 21, the LDNMOS device 22, and the SGT-NMOS device 31; and P+buried layers of the PNP device 122 and the SGT-PMOS device 32 are respectively fabricated; That is, the first N-type buried layer 1211, the second N-type buried layer 211, the third N-type buried layer 221, the fourth N-type buried layer 311, and the fifth N-type buried layer 321; the first N+ type buried layer 1212, the second N+ type buried layer 212, the third N+ type buried layer 222, and the fourth N+ type buried layer 312 are used to reduce the drain resistance; the first P-type buried layer 1221 and the second P-type buried layer 322 are used to reduce the drain resistance; By adopting the N-buried layer, the drain potential of the SGT-NMOS device and SGT-PMOS device is free, allowing the circuits developed using this technology to achieve more functional requirements, such as full-bridge drive circuits, DC / DC control circuits, AC / DC drive circuits and other design requirements; (2) A 10 μm thick intrinsic silicon layer is grown on the surface of the chip after the N-buried layer, N+buried layer, and P+buried layer are formed. In some embodiments, an N-type doped silicon layer or a P-type doped silicon layer may also be used. In some embodiments, the thickness may also be other values ​​between 3 μm and 10 μm, which may be selected based on actual needs. (3) Through pattern masking and ion implantation B11, the P-well region of the entire DMOS device, the P-well region of the LDPMOS device 21, the P-well region of the LDNMOS device 22, and the P-well region of the SGT-PMOS device 32 are produced; That is: P-type well layer B, first P-type well layer B1, second P-type well layer B2, third P-type well layer B3; P-type well layer B serves as a transition layer connected to P-type substrate A; first P-type well layer B1 serves as an adjustment region for the potential freedom of the drain of LDPMOS device 21; second P-type well layer B2 serves as an adjustment region for the potential freedom of the source of LDPMOS device 22; third P-type well layer B3 serves as a drift region of SGT-PMOS device 32; (4) Using a patterned mask and ion implantation B11, a P+ type diffusion region of the SGT-PMOS device 32 is produced; That is: a first P+ type diffusion layer 323, a second P+ type diffusion layer 3221; (5) Using a patterned mask and ion implanting P, N-well regions of the CMOS device 11, NPN device 121, PNP device 122, LDPMOS device 21, LDNMOS device 22, SGT-NMOS device 31, and SGT-PMOS device 32 are produced; That is, there are: a first N-well layer C1, a second N-well layer C2, a third N-well layer C3, a fourth N-well layer C4, a fifth N-well layer C5, a sixth N-well layer C6, and a seventh N-well layer C7; the first N-well layer C1 serves as an electrical isolation layer between the low-voltage CMOS device 11 and the P-type substrate A and the P-type well layer B; the second N-well layer C2 serves as a collector region of the NPN device 121; the third N-well layer C3 serves as a base region of the PNP device 122; the fourth N-well layer C4 serves as an electrical isolation layer between the LDPMOS device 21 and the P-type substrate A and the P-type well layer B; the fifth N-well layer C5 serves as an electrical isolation layer between the LDNMOS device 22 and the P-type substrate A and the P-type well layer B; the sixth N-well layer C6 serves as a drift region of the SGT-NMOS device 31; and the seventh N-well layer C7 serves as an electrical isolation layer between the SGT-PMOS device 32 and the P-type substrate A and the P-type well layer B. (6) Using a patterned mask and ion implanting P, N+ diffusion regions of the NPN device 121 and the SGT-NMOS device 31 are produced; That is: a first N+ type diffusion layer 1213 , a second N+ type diffusion layer 1219 , a third N+ type diffusion layer 313 , and a fourth N+ type diffusion layer 3121 ; (7) Using a pattern mask and dry etching method, silicon trenches of 5 μm in depth are produced for the SGT-NMOS device 31 and the SGT-PMOS device 32; That is, the second deep trench isolation 315, the first deep trench isolation 3111, the third deep trench isolation 3119, the fifth deep trench isolation 325, the fourth deep trench isolation 3211, and the sixth deep trench isolation 3219. In some embodiments, the depth may be other values ​​between 1-5 μm, which may be selected according to actual needs. (8) Thermally oxidizing the silicon trench, depositing polysilicon, and selectively etching the polysilicon to produce the field plate polycrystalline layer of the SGT-NMOS device 31 and the SGT-PMOS device 32; That is, the second field plate polycrystalline layer 316, the first field plate polycrystalline layer 3112, the third field plate polycrystalline layer 3120, the fifth field plate polycrystalline layer 326, the fourth field plate polycrystalline layer 3212, and the sixth field plate polycrystalline layer 3220; the first field plate polycrystalline layer 3112 serves as the source field plate of the SGT-NOMS device 31; the second field plate polycrystalline layer 316 and the third field plate polycrystalline layer 3120 serve as the field limiting ring of the SGT-NOMS device 31; the fourth field plate polycrystalline layer 3212 serves as the source field plate of the SGT-POMS device 32; the fifth field plate polycrystalline layer 326 and the sixth field plate polycrystalline layer 3220 serve as the field limiting ring of the SGT-POMS device 32; (9) Using a graphic mask and dry etching to create shallow trench isolation; (10) In the N-well region, a pattern mask is formed and BF2 is ion-implanted to form the P-type well regions of the NPN device 121, the PNP device 122, the LDPMOS device 21, the LDNMOS device 22, and the SGT-NMOS device 31; That is: the first P-type well region 1121, the second P-type well region 1215, the third P-type well region 1222, the fourth P-type well region 219, the fifth P-type well region 223, the sixth P-type well region 317, and the seventh P-type well region 3115; in some embodiments, B11 may also be used; the first P-type well region 1121 serves as the channel region of the NOMS device 112; the second P-type well region 1215 serves as the base region of the NPN device 121; the third P-type well region 1222 serves as the emitter region of the PNP device 122; the fourth P-type well region 219 serves as the drift region of the LDPMOS device 21; the fifth P-type well region 223 serves as the channel region of the LDNMOS device 22; the sixth P-type well region 317 and the seventh P-type well region 3115 serve as the channel region of the SGT-NMOS device 31; (11) Using a patterned mask in the P-well region and ion implanting P, an N-type well region of the PMOS device 111, the LDPMOS device 21, the LDNMOS device 22, and the SGT-PMOS device 32 is produced; That is, the first N-type well region 1111, the second N-type well region 213, the third N-type well region 229, the fourth N-type well region 327, and the fifth N-type well region 3215. In some embodiments, As may also be used. The first N-type well region 1111 serves as the channel region of the PMOS device 111; the second N-type well region 213 serves as the channel region of the LDPMOS device 21; the third N-type well region 229 serves as the drift region of the LDNMOS device 22; the fourth N-type well region 327 and the fifth N-type well region 3215 serve as the channel region of the SGT-PMOS device 32. (12) Surface sacrificial oxidation to improve silicon surface quality; (13) forming gate dielectric layers of the PMOS device 111, the NMOS device 112, the LDPMOS device 21, the LDNMOS device 22, the SGT-NMOS device 31, and the SGT-PMOS device 32 by thermal oxidation; That is: a first gate dielectric layer 1116 , a second gate dielectric layer 1125 , a third gate dielectric layer 218 , a fourth gate dielectric layer 228 , a fifth gate dielectric layer 3113 , and a sixth gate dielectric layer 3213 ; (14) Depositing polysilicon and forming control gate polycrystalline layers of the PMOS device 111, the NMOS device 112, the LDPMOS device 21, the LDNMOS device 22, the SGT-NMOS device 31, and the SGT-PMOS device 32 by pattern masking and etching; That is: a first control gate polycrystalline layer 1115 , a second control gate polycrystalline layer 1124 , a third control gate polycrystalline layer 217 , a fourth control gate polycrystalline layer 227 , a fifth control gate polycrystalline layer 3114 , and a sixth control gate polycrystalline layer 3214 ; (15) By using different material growth and etching techniques, the sidewall regions of the self-aligned implanted PMOS device 111, NMOS device 112, LDPMOS device 21, and LDNMOS device 22 are manufactured; That is: a first spacer dielectric layer 1114 , a second spacer dielectric layer 1123 , a third spacer dielectric layer 216 , and a fourth spacer dielectric layer 226 ; (16) Using a pattern mask, the P+ implantation region and the N+ implantation region of the PMOS device 111, the NMOS device 112, the NPN device 121, the PNP device 122, the LDPMOS device 21, the LDNMOS device 22, the SGT-NMOS device 31, and the SGT-PMOS device 32 are manufactured; That is: first P+ region a1, second P+ region a2, third P+ region a3, fourth P+ region a4, fifth P+ region a5, sixth P+ region a6, seventh P+ region a7, first N+ region b1, second N+ region b2; (17) Produce a dielectric insulating layer D, and produce a lead hole layer by pattern masking and etching; (18) Make the metal lead layer.

[0037] Example 2

[0038] like Figure 1 — Figure 3 、 Figure 5-Figure 7 This embodiment is basically the same as embodiment 1, except for the structure of the medium pressure zone, which is as follows: The LDPMOS device 21 also includes a first metal layer 2111, which serves as a source field plate and is disposed on the dielectric insulating layer D and between the third spacer dielectric layer 216 to the right of the third control gate polycrystalline layer 217 and the eighth P+ implantation region 2110. This increases the operating voltage of the transistor. The LDNMOS device 22 also includes a second metal layer 2211, which serves as a source field plate and is disposed on the dielectric insulating layer D and between the fourth spacer dielectric layer 226 to the right of the fourth control gate polycrystalline layer 227 and the eleventh N+ implantation region 2210. This increases the operating voltage of the LDNMOS device 22. By providing a metal layer serving as a source field plate on the drain side of the LDPMOS device 21 and the LDNMOS device 22, higher voltage requirements (e.g., 700V) can be achieved.

[0039] Example 3

[0040] like Figure 1 — Figure 4 、 Figure 8-Figure 9 This embodiment is basically the same as embodiment 1, except for the structure of the high-voltage region, which is as follows: The first field plate polycrystalline layer 3112 is arranged along the depth direction of the first deep trench isolation 3111, the fifth control gate polycrystalline layer 3114 is arranged on the upper part of the first deep trench isolation 3111 and located on both sides of the first field plate polycrystalline layer 3112, and the fifth gate dielectric layer 3113 is arranged on both sides of the fifth control gate polycrystalline layer 3114; the fourth field plate polycrystalline layer 3212 is arranged along the depth direction of the fourth deep trench isolation 3211, the sixth control gate polycrystalline layer 3114 is arranged on the upper part of the fourth deep trench isolation 3211 and located on both sides of the fourth field plate polycrystalline layer 3212, and the sixth gate dielectric layer 3213 is arranged on both sides of the sixth control gate polycrystalline layer 3214.

[0041] Example 4

[0042] like Figure 1 — Figure 4 、 Figure 10-11 This embodiment is basically the same as embodiment 1, except for the structure of the high-voltage region, which is as follows: A first field plate polycrystalline layer 3112 is provided at the lower portion of the first deep trench isolation 3111, and a fifth control gate polycrystalline layer 3114 is provided at the upper portion of the first deep trench isolation 3111, and the first field plate polycrystalline layer 3112 and the fifth control gate polycrystalline layer 3114 are not in contact with each other; a fourth field plate polycrystalline layer 3212 is provided at the lower portion of the fourth deep trench isolation 3211, and a sixth control gate polycrystalline layer 3214 is provided at the upper portion of the fourth deep trench isolation 3211, and the fourth field plate polycrystalline layer 3212 and the sixth control gate polycrystalline layer 3214 are not in contact with each other; the cross-sections of the first field plate polycrystalline layer 3212 and the fourth field plate polycrystalline layer 3212 are stepped steps with a larger bottom and a smaller top, and the stepped steps are continuous.

[0043] Example 5

[0044] like Figure 1 — Figure 4 、 Figure 12-13 This embodiment is basically the same as embodiment 1, except for the structure of the high-voltage region, which is as follows: A first field plate polycrystalline layer 3112 is provided at the lower portion of the first deep trench isolation 3111, and a fifth control gate polycrystalline layer 3114 is provided at the upper portion of the first deep trench isolation 3111, and the first field plate polycrystalline layer 3112 and the fifth control gate polycrystalline layer 3114 are not in contact with each other; a fourth field plate polycrystalline layer 3212 is provided at the lower portion of the fourth deep trench isolation 3211, and a sixth control gate polycrystalline layer 3214 is provided at the upper portion of the fourth deep trench isolation 3211, and the fourth field plate polycrystalline layer 3212 and the sixth control gate polycrystalline layer 3214 are not in contact with each other; the cross-sections of the first field plate polycrystalline layer 3212 and the fourth field plate polycrystalline layer 3212 are stepped steps with a larger bottom and a smaller top, and the stepped steps are discontinuous.

[0045] Example 6

[0046] like Figure 1 — Figure 4 、 Figure 14-15 This embodiment is basically the same as embodiment 1, except for the structure of the high-voltage region, which is as follows: A first field plate polycrystalline layer 3112 is provided in the lower portion of the first deep trench isolation 3111, and two fifth control gate polycrystalline layers 3114 are symmetrically provided on both sides of the upper portion of the first deep trench isolation 3111, and the first field plate polycrystalline layer 3112 and the fifth control gate polycrystalline layer 3114 are not in contact with each other; a fourth field plate polycrystalline layer 3212 is provided in the lower portion of the fourth deep trench isolation 3211, and two sixth control gate polycrystalline layers 3214 are symmetrically provided on both sides of the upper portion of the fourth deep trench isolation 3211, and the fourth field plate polycrystalline layer 3214 and the sixth control gate polycrystalline layer 3212 are not in contact with each other.

[0047] Example 7

[0048] like Figure 1 — Figure 4 、 Figure 16-17 This embodiment is basically the same as embodiment 1, except for the structure of the high-voltage region, which is as follows: A fourth P-type well layer B4 is provided under the first deep trench isolation 3111 and contacts the first field plate polycrystalline layer 3112 . An eighth N-well layer C8 is provided under the fourth deep trench isolation 3211 and contacts the fourth field plate polycrystalline layer 3211 .

[0049] In this application, Examples 3 to 6 are different methods of manufacturing or implementing different source field plates.

[0050] In the present application, the fourth P-type well layer B4 and the eighth N-well layer C8 can be arranged in the same manner as in Example 7 in all of Examples 1 to 6. Specifically, the fourth P-type well layer B4 is provided below the first deep trench isolation 3111 and contacts the first field plate polycrystalline layer 3112. The eighth N-well layer C8 is provided below the fourth deep trench isolation 3211 and contacts the fourth field plate polycrystalline layer 3211. The fourth P-type well layer B4 serves as a depletion layer extension region between the source and drain of the SGT-NMOS device 31, further increasing the operating voltage of the SGT-NMOS device 31. The eighth N-well layer C8 serves as a depletion layer extension region between the source and drain of the SGT-NMOS device 31, further increasing the operating voltage of the SGT-NMOS device 31.

[0051] The above description is merely a preferred embodiment of the present invention and does not constitute any form of limitation to the present invention. Although the present invention has been disclosed as above in terms of a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can, without departing from the scope of the technical solution of the present invention, make some changes or modifications to equivalent embodiments using the technical contents disclosed above. However, any brief modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention are still within the scope of the technical solution of the present invention.

Claims

1. A BCD-based integrated vertical field plate DMOS device, It is characterized in that It includes a P-type substrate and a P-type well layer stacked in sequence from bottom to top in the vertical direction, wherein the P-type well layer is divided into a low-voltage region, a medium-voltage region and a high-voltage region arranged in sequence from left to right in the horizontal direction; a first P+ region is provided between the low-voltage region and the medium-voltage region, and the first P+ region is isolated from the low-voltage region and the medium-voltage region by a shallow trench; a second P+ region is provided between the medium-voltage region and the high-voltage region, and the second P+ region is isolated from the medium-voltage region and the high-voltage region by a shallow trench; the right side of the high-voltage region also includes a first N+ region and a third P+ region arranged in sequence from left to right in the horizontal direction, the high-voltage region and the first N+ region are isolated by a shallow trench, the first N+ region and the third P+ region are isolated by a shallow trench, and the right side of the third P+ region also has a shallow trench isolation; The low-voltage region includes low-voltage CMOS devices and Bipolar devices arranged in sequence from left to right along the horizontal direction, the medium-voltage region includes LDPMOS devices and LDNMOS devices arranged in sequence from left to right along the horizontal direction; the high-voltage region includes SGT-NMOS devices and SGT-PMOS devices arranged in sequence from left to right along the horizontal direction.

2. The BCD integrated vertical field plate DMOS device according to claim 1, It is characterized in that The low-voltage CMOS device includes a PMOS device and an NMOS device arranged in sequence from left to right in the horizontal direction; the Bipolar device includes an NPN device and a PNP device arranged in sequence from left to right in the horizontal direction; a fourth P+ region is provided between the low-voltage CMOS device and the Bipolar device, and the fourth P+ region is isolated from the low-voltage CMOS device and the Bipolar device by a shallow trench; The PMOS device and the NMOS device are isolated by a shallow trench; A fifth P+ region is provided between the NPN device and the PNP device, and the fifth P+ region is isolated from the NPN device and the PNP device by a shallow trench; A sixth P+ region is provided between the LDPMOS device and the LDNMOS device, and the sixth P+ region is isolated from the LDPMOS device and the LDNMOS device by a shallow trench; A seventh P+ region and a second N+ region are arranged in sequence from left to right along the horizontal direction between the SGT-NMOS device and the SGT-PMOS device, and the SGT-NMOS device, the seventh P+ region, the second N+ region and the SGT-PMOS device are all isolated by shallow trenches.

3. The BCD integrated vertical field plate DMOS device according to claim 2, It is characterized in that The first P+ region, the second P+ region, the third P+ region, the fourth P+ region, the fifth P+ region, the sixth P+ region and the seventh P+ region are all arranged in the upper part of the P-type well layer, and the first P+ region, the second P+ region, the third P+ region, the fourth P+ region, the fifth P+ region, the sixth P+ region and the seventh P+ region are respectively led out through the metal layer as ground terminals; The upper part of the P-type well layer has a first N-well layer, a second N-well layer, a third N-well layer, a fourth N-well layer, a fifth N-well layer, a sixth N-well layer, and a seventh N-well layer in sequence from left to right along the horizontal direction; The second N+ region is disposed at an upper portion of a left side in the seventh N-well layer, and the first N+ region is disposed at an upper portion of a right side in the seventh N-well layer; There is a dielectric insulation layer above the low voltage area, the medium voltage area and the high voltage area.

4. The BCD integrated vertical field plate DMOS device according to claim 3, It is characterized in that The PMOS device includes a first N-type well region constructed in the upper part of the first N-well layer and a first N+ injection region, a first P+ injection region, and a second P+ injection region constructed in the upper part of the first N-type well region and arranged in sequence from left to right in the horizontal direction. Shallow trench isolation is provided on both sides of the first N+ injection region. A first gate dielectric layer is provided above the first N-type well region between the first P+ injection region and the second P+ injection region. A first control gate polycrystalline layer is provided above the first gate dielectric layer. First sidewall dielectric layers are provided on both sides of the first control gate polycrystalline layer and the first gate dielectric layer, and the first sidewall dielectric layers on both sides are respectively located above the first P+ injection region and the second P+ injection region; the first N+ injection region, the first P+ injection region, and the second P+ injection region are respectively led out through the metal layer.

5. The BCD integrated vertical field plate DMOS device according to claim 3, It is characterized in that The NMOS device includes a first P-type well region constructed at the upper part of a first N-well layer, and a second N+ injection region, a third N+ injection region, and a third P+ injection region constructed at the upper part of the first P-type well region, which are arranged in sequence from left to right along the horizontal direction, and shallow trench isolation is provided on both sides of the third P+ injection region. A second gate dielectric layer is provided above the first P-type well region between the second N+ injection region and the third N+ injection region, and a second control gate polycrystalline layer is provided above the second gate dielectric layer. Second sidewall dielectric layers are provided on both sides of the second control gate polycrystalline layer and the second gate dielectric layer, and the second sidewall dielectric layers on both sides are respectively located above the second N+ injection region and the third N+ injection region; the second N+ injection region, the third N+ injection region, and the third P+ injection region are respectively led out through the metal layer.

6. The BCD integrated vertical field plate DMOS device according to claim 3, It is characterized in that The NPN device includes a first N-type buried layer constructed below the second N-well layer, the first N-type buried layer has a first N+ type buried layer, the upper part of the second N-well layer has a second P-type well region, the upper part of the second N-well layer on both sides of the second P-type well region is respectively provided with a fourth N+ injection region and a fifth N+ injection region, both sides of the fourth N+ injection region and the fifth N+ injection region have shallow trench isolation, the lower part of the fourth N+ injection region has a first N+ type diffusion layer connected to the first N-type buried layer, the lower part of the fifth N+ injection region has a second N+ type diffusion layer connected to the first N-type buried layer, the upper part of the second P-type well region has a fourth P+ injection region, a sixth N+ injection region, and a fifth P+ injection region arranged in sequence from left to right along the horizontal direction, and both sides of the sixth N+ injection region have shallow trench isolation; the fourth N+ injection region, the fifth N+ injection region, the fourth P+ injection region, the sixth N+ injection region, and the fifth P+ injection region are respectively led out through the metal layer.

7. The BCD integrated vertical field plate DMOS device according to claim 3, It is characterized in that The PNP device includes a first P-type buried layer constructed below a third N-well layer, the upper portion of the third N-well layer has a third P-type well region, a seventh N+ injection region and an eighth N+ injection region are respectively arranged in the upper portion of the third N-well layer on both sides of the third P-type well region, shallow trench isolation is provided on both sides of the seventh N+ injection region and the eighth N+ injection region, a sixth P+ injection region is provided in the upper portion of the third P-type well region; the seventh N+ injection region, the eighth N+ injection region, and the sixth P+ injection region are respectively led out through metal layers.

8. The BCD integrated vertical field plate DMOS device according to claim 3, It is characterized in that The LDPMOS device includes a fourth N-well layer, a first P-type well layer is provided on the right side of the upper portion of the fourth N-well layer, a second N-type buried layer is constructed below the fourth N-well layer, a second N+ type buried layer is provided in the second N-type buried layer, a second N-type well region is provided on the left side of the upper portion of the fourth N-well layer, a fourth P-type well region adjacent to the second N-type well region is provided in the upper portion of the first P-type well layer, a ninth N+ injection region and a seventh P+ injection region are arranged in sequence from left to right in the horizontal direction in the upper portion of the second N-type well region, and the ninth N+ injection region is provided in the lower portion of the second N-well region. The area between the second N-type well area and the seventh P+ injection area is isolated by a shallow trench, a third gate dielectric layer is provided above the second N-type well area and the fourth P-type well area, a third control gate polycrystalline layer is provided above the third gate dielectric layer, and third sidewall dielectric layers are provided on both sides of the third control gate polycrystalline layer and the third gate dielectric layer; an eighth P+ injection area is provided on the right side of the upper part of the fourth P-type well area, a shallow trench is provided on the left side of the eighth P+ injection area and the area below the third sidewall dielectric layer on the right side of the third control gate polycrystalline layer, and the third sidewall dielectric layer on the left side is located above the seventh P+ injection area; The ninth N+ injection region, the seventh P+ injection region, and the eighth P+ injection region are respectively led out through the metal layer.

9. The BCD integrated vertical field plate DMOS device according to claim 3, It is characterized in that The LDNMOS device comprises a fifth N-well layer, the upper left part of the fifth N-well layer is a second P-type well layer, a third N-type buried layer is constructed below the fifth N-well layer, a third N+ type buried layer is provided in the third N-type buried layer, a fifth P-type well region is provided in the upper part of the second P-type well layer, and a third N-type well region adjacent to the fifth P-type well region is provided in the upper part of the fifth N-well layer; The upper part of the fifth P-type well region has a ninth P+ injection region and a tenth N+ injection region arranged in sequence from left to right in the horizontal direction, the ninth P+ injection region and the tenth N+ injection region are isolated by a shallow trench, a fourth gate dielectric layer is provided above the fifth P-type well region and the third N-type well region, a fourth control gate polycrystalline layer is provided above the fourth gate dielectric layer, and fourth sidewall dielectric layers are provided on both sides of the fourth control gate polycrystalline layer and the fourth gate dielectric layer; The third N-type well region also has an eleventh N+ injection region on the upper right side, and a shallow trench isolation is formed between the left side of the eleventh N+ injection region and the fourth sidewall dielectric layer on the right side of the fourth control gate polycrystalline layer, and the fourth sidewall dielectric layer on the left side of the fourth control gate polycrystalline layer is located above the tenth N+ injection region; The ninth P+ implantation region, the tenth N+ implantation region, and the eleventh N+ implantation region are respectively led out through the metal layer.

10. The BCD integrated vertical field plate DMOS device according to claim 3, It is characterized in that The SGT-NMOS device includes a fourth N-type buried layer constructed below the sixth N-well layer, the fourth N-type buried layer has a fourth N+ type buried layer, the sixth N-well layer is provided with a twelfth N+ injection region and a thirteenth N+ injection region at the upper parts of both sides, shallow trench isolation is provided at both sides of the twelfth N+ injection region and the thirteenth N+ injection region, a third N+ type diffusion layer connected to the fourth N-type buried layer is provided below the twelfth N+ injection region, a fourth N+ type diffusion layer connected to the fourth N-type buried layer is provided below the thirteenth N+ injection region, the sixth N-well layer has a first deep trench isolation at the upper middle part, the first deep trench isolation has a first field plate polycrystalline layer and a fifth control gate polycrystalline layer, the first field plate polycrystalline layer and the fifth control gate polycrystalline layer are not in contact, the fifth control gate polycrystalline layer has a fifth gate dielectric layer at both sides, the sixth N-well layer has a symmetrically arranged sixth P-type well region and a seventh P-type well region at the upper part of both sides of the first deep trench isolation, The upper part of the sixth P-type well region has a fourteenth N+ injection region, a tenth P+ injection region, and a fifteenth N+ injection region arranged in sequence from left to right in the horizontal direction. The upper part of the seventh P-type well region has a sixteenth N+ injection region, an eleventh P+ injection region, and a seventeenth N+ injection region arranged in sequence from left to right in the horizontal direction. There is a second deep trench isolation between the shallow trench isolation on the right side of the twelfth N+ injection region and the sixth P-type well region, and a second field plate polycrystalline layer is provided in the second deep trench isolation. There is a third deep trench isolation between the shallow trench isolation on the left side of the thirteenth N+ injection region and the seventh P-type well region, and a third field plate polycrystalline layer is provided in the third deep trench isolation; the twelfth N+ injection region, the thirteenth N+ injection region, and the fifth control gate polycrystalline layer are respectively led out through the metal layer; the fourteenth N+ injection region, the tenth P+ injection region, and the fifteenth N+ injection region are led out through the same metal layer; the sixteenth N+ injection region, the eleventh P+ injection region, and the seventeenth N+ injection region are led out through the same metal layer.

11. The BCD integrated vertical field plate DMOS device according to claim 3, It is characterized in that The SGT-PMOS device includes a fifth N-type buried layer constructed below the seventh N-well layer, and a second P-type buried layer buried between the seventh N-well layer and the fifth N-type buried layer, a third P-type well layer is located above the second P-type buried layer, a twelfth P+ injection region and a thirteenth P+ injection region are respectively arranged at the upper parts of both sides in the third P-type well layer, shallow trench isolation is provided on both sides of the twelfth P+ injection region and the thirteenth P+ injection region, a first P+ type diffusion layer connected to the second P-type buried layer is provided below the twelfth P+ injection region, a second P+ type diffusion layer connected to the second P-type buried layer is provided below the thirteenth P+ injection region, a fourth deep trench isolation is provided at the middle upper part of the third P-type well layer, a fourth field plate polycrystalline layer and a sixth control gate polycrystalline layer are provided in the fourth deep trench isolation, the fourth field plate polycrystalline layer and the sixth control gate polycrystalline layer are not in contact, a sixth gate dielectric layer is provided on both sides of the sixth control gate polycrystalline layer, and the upper part of the third P-type well layer on both sides of the fourth deep trench isolation has a symmetrically arranged fourth N-type well region and the fifth N-type well region, the upper part of the fourth N-type well region has the fourteenth P+ injection region, the eighteenth N+ injection region, and the fifteenth P+ injection region arranged in sequence from left to right in the horizontal direction, the upper part of the fifth N-type well region has the sixteenth P+ injection region, the nineteenth N+ injection region, and the seventeenth P+ injection region arranged in sequence from left to right in the horizontal direction, the shallow trench isolation on the right side of the twelfth P+ injection region has a fifth deep trench isolation with the fourth N-type well region, the fifth deep trench isolation has a fifth field plate polycrystalline layer, the shallow trench isolation on the left side of the thirteenth P+ injection region has a sixth deep trench isolation with the fifth N-type well region, the sixth deep trench isolation has a sixth field plate polycrystalline layer; the twelfth P+ injection region, the thirteenth P+ injection region, and the sixth control gate polycrystalline layer are respectively led out through the metal layer; the fourteenth P+ injection region, the eighteenth N+ injection region, and the fifteenth P+ injection region are led out through the same metal layer; the sixteenth P+ injection region, the nineteenth N+ injection region, and the seventeenth P+ injection region are led out through the same metal layer.

12. The BCD integrated vertical field plate DMOS device according to claim 8, It is characterized in that The LDPMOS device also has a first metal layer as a source field plate which is arranged on the dielectric insulating layer and located between the third sidewall dielectric layer on the right side of the third control gate polycrystalline layer and the eighth P+ injection region.

13. The BCD integrated vertical field plate DMOS device according to claim 9, It is characterized in that The LDNMOS device also has a second metal layer as a source field plate which is arranged on the dielectric insulating layer and located between the fourth sidewall dielectric layer and the eleventh N+ implantation region on the right side of the fourth control gate polycrystalline layer.

14. The BCD integrated vertical field plate DMOS device according to claim 10, It is characterized in that A first field plate polycrystalline layer is arranged at the lower part of the first deep trench isolation, and a fifth control gate polycrystalline layer is arranged at the upper part of the first deep trench isolation, and the first field plate polycrystalline layer and the fifth control gate polycrystalline layer are not in contact with each other; the cross-section of the first field plate polycrystalline layer is rectangular or has a stepped shape with a larger bottom and a smaller top, and the stepped shape is continuous or discontinuous.

15. The BCD integrated vertical field plate DMOS device according to claim 11, It is characterized in that A fourth field plate polycrystalline layer is arranged at the lower part of the fourth deep trench isolation, and a sixth control gate polycrystalline layer is arranged at the upper part of the fourth deep trench isolation, and the fourth field plate polycrystalline layer and the sixth control gate polycrystalline layer are not in contact with each other; the cross-section of the fourth field plate polycrystalline layer is rectangular or has a stepped shape with a larger bottom and a smaller top, and the stepped shape is continuous or discontinuous.

16. The BCD integrated vertical field plate DMOS device according to claim 10, It is characterized in that The first field plate polycrystalline layer is arranged along the depth direction of the first deep trench isolation, the fifth control gate polycrystalline layer is arranged on the upper part of the first deep trench isolation and on both sides of the first field plate polycrystalline layer, and the fifth gate dielectric layer is arranged on both sides of the fifth control gate polycrystalline layer.

17. The BCD integrated vertical field plate DMOS device according to claim 11, It is characterized in that The fourth field plate polycrystalline layer is arranged along the depth direction of the fourth deep trench isolation, the sixth control gate polycrystalline layer is arranged on the upper part of the fourth deep trench isolation and on both sides of the fourth field plate polycrystalline layer, and the sixth gate dielectric layer is arranged on both sides of the sixth control gate polycrystalline layer.

18. The BCD integrated vertical field plate DMOS device according to claim 10, It is characterized in that A first field plate polycrystalline layer is disposed at the lower portion of the first deep trench isolation, and two fifth control gate polycrystalline layers are symmetrically disposed on both sides of the upper portion of the first deep trench isolation. The first field plate polycrystalline layer and the fifth control gate polycrystalline layer are not in contact.

19. The BCD integrated vertical field plate DMOS device according to claim 11, It is characterized in that A fourth field plate polycrystalline layer is disposed at the lower portion of the fourth deep trench isolation, and two sixth control gate polycrystalline layers are symmetrically disposed on both sides of the upper portion of the fourth deep trench isolation. The fourth field plate polycrystalline layer and the sixth control gate polycrystalline layer are not in contact.

20. The BCD integrated vertical field plate DMOS device according to any one of claims 10, 14, 16 and 18, It is characterized in that A fourth P-type well layer is provided below the first deep trench isolation, and the fourth P-type well layer is in contact with the first field plate polycrystalline layer.

21. The BCD integrated vertical field plate DMOS device according to any one of claims 11, 15, 17 and 19, It is characterized in that An eighth N-well layer is disposed below the fourth deep trench isolation, and the eighth N-well layer is in contact with the fourth field plate polycrystalline layer.

22. A process for preparing the BCD integrated vertical field plate DMOS device according to claim 2, It is characterized in that The steps include: (1) On a P-type substrate, N-buried layers of NPN devices, PNP devices, LDPMOS devices, LDNMOS devices, SGT-NMOS devices, and SGT-PMOS devices, N+ buried layers of NPN devices, LDPMOS devices, LDNMOS devices, and SGT-NMOS devices, and P+ buried layers of PNP devices and SGT-PMOS devices are respectively manufactured; (2) Growing an intrinsic silicon layer or an N-type doped silicon layer or a P-type doped silicon layer with a thickness of 3-10um on the surface of the chip after the N-buried layer, N+buried layer, and P+buried layer are manufactured; (3) Through pattern masking and ion implantation of B11, the P-well region of the entire DMOS device, the P-well region of the LDPMOS device, the P-well region of the LDNMOS device, and the P-well region of the SGT-PMOS device are produced; (4) Through pattern masking and ion implantation of B11, the P+ type diffusion region of the SGT-PMOS device is produced; (5) Through pattern masking and ion implantation of P, N-well regions of CMOS devices, NPN devices, PNP devices, LDPMOS devices, LDNMOS devices, SGT-NMOS devices, and SGT-PMOS devices are produced; (6) Through pattern masking and ion implantation of P, N+ diffusion regions of NPN devices and SGT-NMOS devices are produced; (7) Using pattern mask and dry etching method, silicon trenches of SGT-NMOS and SGT-PMOS devices are produced with a depth of 1-5um; (8) Thermally oxidize the silicon trench, then deposit polysilicon, and selectively etch the polysilicon to produce the field plate polycrystalline layer of the SGT-NMOS device and the SGT-PMOS device; (9) Using a graphic mask and dry etching to produce shallow trench isolation; (10) In the N-well region, a P-type well region of an NPN device, a PNP device, a LDPMOS device, a LDNMOS device, and a SGT-NMOS device is produced by patterning a mask and ion implanting BF2 or B11; (11) In the P-well region, P or As is ion-implanted through a patterned mask to produce an N-well region of a PMOS device, an LDPMOS device, an LDNMOS device, or an SGT-PMOS device; (12) Surface sacrificial oxidation to improve silicon surface quality; (13) Forming the gate dielectric layer of PMOS devices, NMOS devices, LDPMOS devices, LDNMOS devices, SGT-NMOS devices, and SGT-PMOS devices by thermal oxidation; (14) Depositing polysilicon and forming control gate polycrystalline layers of PMOS devices, NMOS devices, LDPMOS devices, LDNMOS devices, SGT-NMOS devices, and SGT-PMOS devices through pattern masking and etching; (15) Through the growth and etching technology of different materials, the sidewall regions of self-aligned implanted PMOS devices, NMOS devices, LDPMOS devices, and LDNMOS devices are produced; (16) Using a patterned mask, the P+ implantation region and the N+ implantation region of a PMOS device, an NMOS device, an NPN device, a PNP device, an LDPMOS device, an LDNMOS device, an SGT-NMOS device, and an SGT-PMOS device are manufactured; (17) Produce a dielectric insulating layer, and produce a lead hole layer by pattern masking and etching; (18) Make a metal lead layer.

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