Control device of PFC circuit and electronic equipment

Abstract

The embodiment of the invention discloses a control device of a PFC circuit and electronic equipment, and relates to the field of power supplies. According to the technical scheme, an auxiliary winding, a signal clamping circuit, a reference voltage circuit, a comparator, a diode, a resistor and a control chip with a complex logic function are integrated, wherein the control chip comprises a second comparator, an event module, a first counter module and a second counter module; fine control over the working frequency and the switching time of a switching tube in the PFC circuit is achieved, and especially optimization under a CRM (critical conduction mode) is achieved.

Description

Technical Field

[0001] The present invention relates to the field of power supplies, and in particular to a control device and electronic equipment for a PFC circuit. Background Art

[0002] With the continuous evolution of digital power technology, PFC (power factor correction) has become one of the most widely used topologies in the field of AC / DC conversion. According to the characteristics of the inductor current, PFC can be clearly divided into three basic operating modes: continuous conduction mode (CCM), discontinuous conduction mode (DCM) and critical conduction mode (CRM). Among them, CRM is favored in PFC control in the small and medium power range due to its unique advantages. The core feature of the CRM mode is that the switch tube achieves zero current conduction, and the boost diode avoids the reverse recovery process. This mechanism significantly reduces system losses and improves overall efficiency.

[0003] Under the CRM control strategy, the switching frequency of the switch tube is not fixed like CCM or DCM, but is adjusted in real time according to a variety of dynamic factors, including input voltage fluctuations, desired output voltage levels, specific parameters of the inductor, and the length of the on-time of each switching cycle. This feature gives the CRM mode extremely high flexibility and adaptability, especially in the face of complex and changing power environments.

[0004] However, the CRM mode also faces some challenges. Especially when the input voltage is low, in order to maintain a stable output voltage, the switch tube needs to switch frequently, resulting in a sharp increase in the switching frequency, which may cause higher switching losses. In addition, in the transient process of rapid switching from light load to heavy load, especially in the period from the trough to the peak of the input voltage, the discharge process also increases accordingly due to the relatively prolonged conduction time of the MOS tube. The direct consequence is that the operating frequency of the switch tube is significantly reduced. This significant change in frequency not only exacerbates the switching loss problem, but may also have an adverse effect on the current waveform, causing waveform distortion, affecting the stability and output quality of the system. Summary of the invention

[0005] The control device and electronic device of the FC circuit provided in the embodiment of the present application can solve the problems of excessive switching loss and current waveform distortion in the operation process of the PFC circuit working in the CRM mode. The technical solution is as follows:

[0006] In a first aspect, an embodiment of the present application provides a control device for a PFC circuit, including:

[0007] Auxiliary winding, signal clamping circuit, first reference voltage circuit, first comparator, sixth resistor, third diode, fourth diode, seventh resistor and control chip; the control chip includes: second reference voltage circuit, second comparator, event module, first counter module and second counter module;

[0008] Wherein, the first end of the auxiliary winding is grounded, the second end of the auxiliary winding is connected to the input end of the signal clamping circuit, the output end of the signal clamping circuit is connected to the negative input pin of the first comparator, the positive input pin of the first comparator is connected to the first reference voltage circuit, the output pin of the first comparator is connected to the first end of the sixth resistor, the second end of the sixth resistor is connected to the anode of the third diode, the cathode of the diode is respectively connected to the anode of the fourth diode, the positive input pin of the second comparator in the control chip, and the first end of the seventh resistor; the cathode of the fourth diode is connected to the output end of the second counter module, and the second end of the seventh resistor is grounded;

[0009] In the control chip, the negative input pin of the second comparator is connected to the second reference voltage circuit, the output pin of the second comparator is connected to the input end of the event module, the output end of the event module is respectively connected to the input ends of the first counter module and the second counter module, and the output end of the first counter module is connected to the switch tube in the PFC circuit;

[0010] The first counter module and the second counter module are provided with a first threshold CMPA, a second threshold CMPB, a third threshold CMPC, and a fourth threshold CMPD; the counting cycle value of the first counter module and the second counter module is equal to the inverse of the lowest switching frequency of the PFC circuit;

[0011] The event module E1 is used to output a counting event signal to the first counter module and the second counter module when detecting that the output signal of the second comparator U2 has a rising edge; wherein, when the current count value of the event module is equal to between 0 and the first threshold CMPA, the counting event signal is stopped from being output to the first counter module and the second counter module;

[0012] The first counter module PWM1 and the second counter module PWM2 are used to count based on the counting event signal output by the event module; when the current count value reaches the second threshold CMPB, a high level signal is output to the switch tube of the PFC circuit; when the current count value reaches the fourth threshold CMPD, a low level is output to the switch tube of the PFC circuit; when the current count value is equal to the counting cycle value, a count reset operation is performed.

[0013] In a second aspect, the present application provides an electronic device, including a PFC circuit and the above-mentioned control device.

[0014] The beneficial effects brought about by the technical solutions provided by some embodiments of the present application include at least:

[0015] The zero-crossing signal of the inductor current is accurately captured by the auxiliary winding and the signal clamp circuit, and the dynamic adjustment of the operating frequency of the switch tube is realized by combining the complex logic inside the control chip. This adjustment mechanism can automatically optimize the switching frequency according to the changes in the input voltage, output voltage and load conditions, effectively avoiding the problem of too high or too low switching frequency when the input voltage is low or the load changes greatly, thereby reducing the switching loss and improving the system efficiency. By accurately controlling the on and off time of the switch tube, especially using the multiple thresholds (CMPA, CMPB, CMPC, CMPD) set by the first counter module and the second counter module, the fine management of the working state of the switch tube is realized. This helps to reduce the current waveform distortion caused by the change of the switching frequency and improves the output quality of the power supply. The control chip in this technical solution integrates a variety of functional modules, such as event modules, counter modules, etc. These modules work together to quickly respond to changes in the system state and take corresponding control measures. This highly integrated control method improves the stability and reliability of the system and reduces system abnormalities caused by component failures or parameter mismatches. In view of the characteristics of the CRM mode, this technical solution achieves zero current conduction of the switch tube and no reverse recovery process of the boost diode by dynamically adjusting the switching frequency and switching time, thereby further reducing system losses. This optimization is particularly suitable for small and medium power PFC control, which helps to improve overall energy efficiency. The design of this technical solution has high flexibility and scalability. By adjusting the parameters and logic inside the control chip, it can adapt to the PFC circuit requirements of different power levels and application scenarios. At the same time, this solution also facilitates subsequent function upgrades and performance optimization. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0017] Figure 1 is a structural diagram of a PFC circuit provided in an embodiment of the present application;

[0018] Figure 2 and Figure 3is a circuit diagram of a control device for a PFC circuit provided in an embodiment of the present application;

[0019] Figure 4 4 is a signal timing diagram of a control device for a PFC circuit provided in an embodiment of the present application. DETAILED DESCRIPTION

[0020] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0021] See also Figure 1 The embodiment of the present invention provides a schematic diagram of the structure of a PFC circuit, including: a rectifier circuit, an inductor L1, a switch tube Q1, a diode D5 and a filter capacitor C1. The rectifier circuit is composed of four diode groups D1 to D4. The connection relationship of the above components can refer to Figure 1 As shown, no further description is given here. It should be noted that Figure 1 The structure of the PFC circuit is only an example. The specific implementation can be based on the actual situation. Figure 1 Add or modify components based on the PFC circuit.

[0022] See also Figure 2 and Figure 3 The embodiment of the present invention provides a control device for a PFC circuit, comprising: an auxiliary winding T1, a signal clamping circuit, a first reference voltage circuit, a first comparator U1, a sixth resistor R6, a third diode D3, a fourth diode D4, a seventh resistor R7 and a control chip P1; the control chip P1 comprises: a second reference voltage circuit, a second comparator U2, an event module E1, a first counter module PWM1 and a second counter module PWM2, the auxiliary winding T1 is arranged on an inductor in the PFC circuit, and is used to measure a voltage signal of a change on the inductor; the signal clamping circuit is used to clamp the voltage signal measured by the auxiliary winding T1. The first reference voltage circuit is used to provide a reference voltage signal for the first comparator U1, and the second reference voltage circuit is used to provide a reference voltage signal for the second comparator U2.

[0023] Wherein, a first end of the auxiliary winding T1 is grounded, a second end of the auxiliary winding T1 is connected to an input end of a signal clamping circuit, an output end of the signal clamping circuit is connected to a negative input pin of a first comparator U1, a positive input pin of the first comparator U1 is connected to a first reference voltage circuit, an output pin of the first comparator U1 is connected to a first end of a sixth resistor D6, a second end of the sixth resistor D6 is connected to an anode of a third diode D3, a cathode of the diode D3 is respectively connected to an anode of a fourth diode D4, a positive input pin of a second comparator U2 in a control chip P1, and a first end of a seventh resistor R7; a cathode of the fourth diode D4 is connected to an output end of a second counter module PWM2, and a second end of the seventh resistor R7 is grounded;

[0024] In the control chip P1, the negative input pin of the second comparator U2 is connected to the second reference voltage circuit, the output pin of the second comparator U2 is connected to the input end of the event module E1, the output end of the event module E1 is respectively connected to the input ends of the first counter module PWM1 and the second counter module PWM2, and the output end of the first counter module PWM1 is connected to the switch tube in the PFC circuit.

[0025] In some embodiments of the present application, the signal clamping circuit includes: a first resistor R1, a second resistor R2, a first diode D1, a second diode D2, and a third resistor R3.

[0026] Among them, the first end of the first resistor R1 is connected to the second end of the auxiliary winding T1, and the second end of the first resistor R1 is respectively connected to the first end of the second resistor R2 and the cathode of the first diode D1; the second end of the second resistor R2 is connected to the negative input pin of the first comparator U1; the anode of the first diode D1 is grounded; the cathode of the second diode D2 is connected to the negative input pin of the first comparator U1, and the anode of the second diode D2 is grounded; the first end of the third resistor R3 is connected to the negative input pin of the second comparator U2, and the second end of the third resistor R3 is grounded.

[0027] In some embodiments of the present application, the first reference voltage circuit includes: a fourth resistor R4 and a fifth resistor R5. The first end of the fifth resistor R5 is connected to the power supply VCC, the first end of the fourth resistor R4 is grounded, and the second end of the fifth resistor R5 is respectively connected to the second end of the fourth resistor R4 and the positive input pin of the first comparator U1.

[0028] See also Figure 2 and Figure 3 , the working principle of the control device of the PFC circuit of the present application is explained below.

[0029] The inductor of the PFC circuit is provided with an auxiliary winding T1, which measures the voltage signal at both ends of the inductor. The first end of the auxiliary winding T1 is grounded, and the second end is connected to the first end of the first resistor R1. The first resistor R1, the second resistor R2, the third resistor R3, the first diode D1, and the second diode D2 constitute a signal clamping circuit. The model of the first diode D1 can be IN4148, and the second diode D2 is a voltage regulator. For example, the voltage regulator value is 3V. The signal clamping circuit processes the voltage signal measured by the auxiliary winding to obtain the signal S0. When the switch tube Q1 in the PFC circuit is turned on, the voltage value of the signal S0 is 0V; when the switch tube Q1 is turned off, the level of the signal S0 is clamped at 3V; when the current of the inductor L1 is less than 0, the voltage value of the signal S0 is clamped at 0V. That is, the signal clamping circuit clamps the voltage of the signal S0 between 0V and 3V.

[0030] The first reference voltage circuit provides a reference voltage signal for the first comparator. For example, the first comparator U1 is powered by a single power supply, and the power supply voltage is 3.3V. The fourth resistor R4 and the fifth resistor R5 form the first reference voltage circuit, and the power supply voltage signal of the power supply VCC is divided into a reference voltage signal of 2.8V. The reference voltage signal is input to the positive input pin of the simulated first comparator U1, and the signal S0 is input to the negative input pin of the first comparator U1. The output result of the first comparator U1 is the signal S1, and the signal S1 is a high level signal or a low level signal. The signal S1 passes through the sixth resistor R6 and the third diode D3 to obtain the signal S3. When the current of the inductor L1 in the PFC circuit is positive, the voltage value of the signal S0 is 3V, and the signal S3 is a high level signal, otherwise the signal S3 is a low level signal.

[0031] Among them, the control chip P1 is provided with a second comparator U2, the positive input pin of the second comparator U2 is input with a signal S3, and the negative input pin is connected with a second reference voltage circuit, which can be a digital-to-analog converter for providing a reference voltage signal. For example, the bit width of the DAC is 12 bits, and the value output by the DAC is configured to be 2048, that is, a reference voltage signal of 1.5V is loaded on the negative input pin of the second comparator U2. The output signal of the second comparator U2 is a signal S6, and the signal S6 is a high level signal or a low level signal.

[0032] Among them, the first counter module PWM1 and the second counter module PWM2 are set with a first threshold CMPA, a second threshold CMPB, a third threshold CMPC, and a fourth threshold CMPD; the counting cycle value of the first counter module PWM1 and the second counter module PWM2 is equal to the inverse of the lowest switching frequency of the PFC circuit PEROID_MAX_VAULE, and the inverse of the highest switching frequency of the PFC circuit is PEROID_MIN_VAULE.

[0033] Event module E1 is used to capture the rising edge of signal S6. When the rising edge of the output signal of the second comparator U2 is detected, it outputs a counting event signal to the first counter module PWM1 and the second counter module PWM2. Among them, when the current count value of the event module E1 is equal to any value between 0 and the first threshold CMPA, the output of the counting event signal to the first counter module and the second counter module is stopped. The event module starts counting from 0. Every time a rising edge is detected, the current count value is incremented by 1. When the current count value is equal to the count period value PEROID_MAX_VAULE, a count reset operation is performed, that is, counting starts from 0 again.

[0034] The first counter module PWM1 and the second counter module PWM2 are used to count based on the counting event signal output by the event module. When the current count value reaches the second threshold CMPB, a high-level signal is output to the switching tube of the PFC circuit. When the current count value reaches the fourth threshold CMPD, a low-level signal is output to the switching tube of the PFC circuit. When the current count value is equal to the count period value, a count reset operation is performed.

[0035] Among them, when the second counter module PWM2 outputs a low-level signal when the current count value reaches the second threshold CMPB and outputs a high-level signal when the current count value reaches the fourth threshold CMPD, the output signal S2 is used to forcibly pull down the ZCD input signal for frequency limiting use.

[0036] The second threshold CMPB of the first count value module PWM1 is set to 0. The setting of the fourth threshold CMPD: Take the smaller value of the loop calculation result and the maximum conduction value DATA_MAX calculated by the volt-second product formula when the switching tube operates at the lowest frequency as the value of the fourth threshold CMPD, denoted as PWM1_CMPD_LOAD.

[0037] The setting of the first threshold CMPA of the first counter module PWM1 and the second counter module PWM2 is as follows: The first threshold CMPA of the two counter modules is the same. When PWM1_CMPD_LOAD + DATA1 < PEROID_MIN_VAULE, the value of the first threshold CMPA is PEROID_MIN_VAULE; otherwise, the value of the first threshold CMPA is PWM1_CMPD_LOAD + DATA1, and the value of the first threshold CMPA is denoted as CMPA_LOAD. Among them, DATA1 is the count value from the turn-off of the switching tube Q1 to the first threshold CMPA, which is used to eliminate the jitter caused by the turn-off of the switching tube Q1. This ensures that the ZCD signal occurs after the count value reaches PEROID_MIN_VAULE, limiting the highest operating frequency.

[0038] The value of the second threshold CMPB of the second counter module PWM2 is set to CMPA_LOAD, and the value of the fourth threshold CMPD is set to CMPA_LOAD+DATA2, where DATA2 is the pulse width of the low level of the signal S2.

[0039] Signal S3 is generated by signal S1 and signal S2. When signal S2 is a low level signal, the ZCD signal is a low level. When signal S2 is a high level, the level of the ZCD signal is the same as that of signal S1. Therefore, the ZCD signal will be pulled down when the current count value reaches CMPA_LOAD. At this time, even if the current of the inductor L1 reaches the zero crossing point before the current count value reaches CMPA_LOAD, it will also generate a rising edge when the current count value of the second counter module PWM2 reaches the fourth threshold CMPD. This ensures that the switch tube Q1 operates at a higher switching frequency, rather than the lowest frequency, and can avoid jitter caused by frequency mutation.

[0040] See also Figure 4 As shown, it is a signal timing diagram of the control device of the application, and the user describes the relationship between various signals of the control device of the PFC circuit under three working conditions.

[0041] The first case is t0~t3, the current zero crossing point of the switch tube Q1 occurs after the signal S2 is pulled down by t2, and t0~t2 is the shortest switching period PEROID_MIN_VAULE corresponding to the switch tube Q1. The signal S2 does not affect the switch tube. At the current zero crossing point t3, the first counter module PWM1 and the second counter module PWM2 are reset.

[0042] The second situation is t3~t5, the current zero point of the switch tube Q1 occurs before the signal S2 is pulled low by t4, the on-time t3~t4 is less than the shortest switching period PEROID_MIN_VAULE corresponding to the switch tube Q1, and the rising edge of the signal S2 resets the first counter module PWM1 and the second counter module PWM2, limiting the switch tube Q1 to operate at the highest frequency.

[0043] The third situation is from t5 to t8, the current zero-crossing point of the switch tube Q1 occurs after the signal S2 is pulled low by t6, and the on-time of the switch tube Q1 is greater than the shortest switching period PEROID_MIN_VAULE, the rising edge of the signal S2 occurs after t6, the signal S2 does not affect the switch tube Q1, and the first counter module PWM1 and the second counter module PWM2 are reset at the current zero-crossing point t8.

[0044] In the embodiments of the present application, the application of the auxiliary winding makes the current detection more direct and real-time, especially in the PFC circuit, the current waveform may fluctuate due to load changes. The signal obtained by the auxiliary winding, combined with the signal clamping circuit and the comparator, can accurately capture the zero crossing point of the current. This not only helps to achieve more accurate current control, but also improves the response speed and stability of the system.

[0045] Optimize power factor: Accurate current zero-crossing detection is the key to achieving high power factor correction. In the PFC circuit, the input current waveform is controlled to follow the input voltage waveform as much as possible by controlling the on and off of the switch tube, thereby reducing harmonic distortion and improving the power factor. Accurate current zero-crossing signals help achieve a smoother current waveform and further improve the power factor.

[0046] Prevent inductor saturation and overcurrent protection: By limiting the on-time of the switch tube through volt-second calculation, the inductor saturation and overcurrent problems caused by the inductor working in continuous conduction mode (CCM) can be effectively prevented. In CCM mode, the inductor current may continue to rise, exceed its rated value, and damage the inductor or switch tube. Limiting the maximum on-time can ensure that the inductor works in a safer and more efficient discontinuous conduction mode (DCM).

[0047] Improve system efficiency and reliability: Limiting the maximum operating frequency can reduce switching losses, because high-frequency switching operations generate more heat and electromagnetic interference. At the same time, by preventing inductor saturation and overcurrent through protection mechanisms, the service life of the entire PFC circuit can be extended and the reliability of the system can be improved.

[0048] Enhance system flexibility and adaptability: By introducing control methods such as signal S2, the system can dynamically adjust the operating frequency and opening time of the switch tube according to different load conditions and input voltage conditions to adapt to different working environments and needs. This flexibility makes the PFC circuit more adaptable to complex power systems and changing load conditions.

[0049] The electronic device provided in the embodiment of the present application includes a PFC circuit and the above-mentioned control device. The electronic device is not limited to communication equipment, terminal equipment, computer equipment, etc. In addition to the above-mentioned PFC circuit, the electronic device may also include: a housing for accommodating various components, a display screen and an input device (for example: a keyboard, a mouse or a touch screen), etc.

[0050] The above-described implementation methods do not constitute a limitation on the protection scope of the technical solution. Any modification, equivalent replacement and improvement made within the spirit and principle of the above-described implementation methods shall be included in the protection scope of the technical solution.

Claims

1. A control device for a PFC circuit, It is characterized in that include: Auxiliary winding, signal clamping circuit, first reference voltage circuit, first comparator, sixth resistor, third diode, fourth diode, seventh resistor and control chip; the control chip includes: second reference voltage circuit, second comparator, event module, first counter module and second counter module; Wherein, the first end of the auxiliary winding is grounded, the second end of the auxiliary winding is connected to the input end of the signal clamping circuit, the output end of the signal clamping circuit is connected to the negative input pin of the first comparator, the positive input pin of the first comparator is connected to the first reference voltage circuit, the output pin of the first comparator is connected to the first end of the sixth resistor, the second end of the sixth resistor is connected to the anode of the third diode, the cathode of the diode is respectively connected to the anode of the fourth diode, the positive input pin of the second comparator in the control chip, and the first end of the seventh resistor; the cathode of the fourth diode is connected to the output end of the second counter module, and the second end of the seventh resistor is grounded; In the control chip, the negative input pin of the second comparator is connected to the second reference voltage circuit, the output pin of the second comparator is connected to the input end of the event module, the output end of the event module is respectively connected to the input ends of the first counter module and the second counter module, and the output end of the first counter module is connected to the switch tube in the PFC circuit; The first counter module and the second counter module are provided with a first threshold CMPA, a second threshold CMPB, a third threshold CMPC, and a fourth threshold CMPD; the counting cycle value of the first counter module and the second counter module is equal to the inverse of the lowest switching frequency of the PFC circuit; The event module E1 is used to output a counting event signal to the first counter module and the second counter module when detecting that the output signal of the second comparator U2 has a rising edge; wherein, when the current count value of the event module is equal to between 0 and the first threshold CMPA, the counting event signal is stopped from being output to the first counter module and the second counter module; The first counter module PWM1 and the second counter module PWM2 are used to count based on the counting event signal output by the event module; when the current count value reaches the second threshold CMPB, a high level signal is output to the switch tube of the PFC circuit; when the current count value reaches the fourth threshold CMPD, a low level is output to the switch tube of the PFC circuit; when the current count value is equal to the counting cycle value, a count reset operation is performed.

2. The control device according to claim 1, It is characterized in that The signal clamping circuit comprises: a first resistor, a second resistor, a first diode, a second diode, and a third resistor; Wherein, the first end of the first resistor is connected to the second end of the auxiliary winding, and the second end of the first resistor is connected to the first end of the second resistor and the cathode of the first diode respectively; The second end of the second resistor is connected to the negative input pin of the first comparator; The anode of the first diode is grounded; The cathode of the second diode is connected to the negative input pin of the first comparator, and the anode of the second diode is grounded; A first end of the third resistor is connected to the negative input pin of the second comparator, and a second end of the third resistor is grounded.

3. The control device according to claim 1 or 2, It is characterized in that The first reference voltage circuit includes: a fourth resistor and a fifth resistor; The first end of the fifth resistor is connected to a power supply, the first end of the fourth resistor is grounded, and the second end of the fifth resistor is respectively connected to the second end of the fourth resistor and the positive input pin of the first comparator.

4. The control device according to claim 3, It is characterized in that The second reference voltage circuit includes a DAC analog-to-digital converter with a bit width of 12.

5. An electronic device, It is characterized in that The invention comprises a PFC circuit and a control device as claimed in any one of claims 1 to 4.

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