Switching converter and power stage thereof

Abstract

The present application provides a switching converter comprising: a power stage for driving a current through an inductance value within a duration specified by a periodic control signal; the phase controller is used for generating the period control signal so as to enable the power stage to generate a stabilized power supply voltage; wherein the power stage is configured to communicate with the phase controller on a line; the power stage comprises a first sub-stage and a second sub-stage, the first sub-stage and the second sub-stage respond to the period control signal to respectively drive a first sub-current and a second sub-current through a plurality of corresponding inductors, and the plurality of corresponding inductors jointly provide the inductance value; the circuit is used for communication between the first sub-stage and the phase controller and then communication between the second sub-stage and the phase controller in the conversion period of the period control signal.

Description

Technical Field

[0001] The present application relates to the technical field of power supply circuits, and in particular to a switching converter and a power level thereof. Background Art

[0002] In the relevant technical field, it is well known that a switching converter refers to a device that generates a stable DC (direct current) voltage from an input power supply by using one or more switches. Switching converters are used in devices such as computers and mobile phones, and are also well known in the technical field.

[0003] The power stage is an essential module of the switching converter, which includes a pair of power switches for driving the inductor. Each power switch (switch) is usually a transistor (e.g., MOSFET), and the pair of switches are connected in series between the input power supply and the reference terminal (e.g., ground). The switch in the pair of switches close to the input power supply (i.e., the input power supply of the switching converter) is called a high-side switch, and the other switch is called a low-side switch.

[0004] The pair of switches is controlled by a control circuit that controls the transistor to conduct in consecutive and non-overlapping time periods, so that the currently conducting switch drives the inductor in the corresponding time period. In fact, the switching converter converts the voltage of the input power supply (input power supply voltage) into a pulse voltage by operating a number of switches, and then stabilizes and smoothes the pulse voltage using capacitors and / or other components to generate a stable DC voltage.

[0005] Switching converters often require power stages that can deliver higher current amplitudes. However, such power stages may need to be backward compatible with phase controllers that already have pre-set signals / pins. Summary of the invention

[0006] In view of this, the present application provides a switching converter and a power stage thereof that provide a higher amplitude current.

[0007] In a first aspect, the present application provides a switching converter, comprising: a power stage and a phase controller. The power stage is used to drive current through inductance within the duration specified by a periodic control signal; the phase controller is used to generate the periodic control signal so that the power stage generates a regulated power supply voltage; wherein the power stage is configured to communicate with the phase controller on a line; the power stage comprises a first sub-stage and a second sub-stage, the first sub-stage and the second sub-stage respectively drive a first sub-current and a second sub-current through a plurality of corresponding inductors in response to the periodic control signal, and the plurality of corresponding inductors jointly provide the inductance; the line is used for the first sub-stage to communicate with the phase controller first, and then for the second sub-stage to communicate with the phase controller during the conversion period of the periodic control signal.

[0008] In a second aspect, the present application provides a power stage, which is used to drive current through inductance within a duration specified by a periodic control signal; wherein the periodic control signal is generated by an external phase controller, so that the power stage generates a regulated power supply voltage, wherein the power stage is configured to communicate with the phase controller on a line; the power stage includes a first sub-stage and a second sub-stage, and the first sub-stage and the second sub-stage drive a first sub-current and a second sub-current respectively through a number of corresponding inductors in response to the periodic control signal, and the number of corresponding inductors jointly provide the inductance; within the conversion period of the periodic control signal, the line is first used for the first sub-stage to communicate with the phase controller, and then used for the second sub-stage to communicate with the phase controller.

[0009] The switching converter and power stage described above enable each sub-stage to drive the corresponding sub-current to twice the amplitude on one line through the corresponding inductor, thereby obtaining a current with a higher amplitude. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Exemplary embodiments disclosed in the present application will be briefly described below with reference to the accompanying drawings.

[0011] Figure 1 It is a schematic diagram of the structure of an example system provided by an embodiment of the present application that can implement several aspects of the present application.

[0012] Figure 2 Detailed block diagram of a voltage regulation module (VRM) provided in accordance with an embodiment of the present application.

[0013] Figure 3A is a block diagram of a power stage configured to provide a higher current according to an embodiment of the present application.

[0014] Figure 3BIt is a timing diagram of the way in which two sub-stages of a power stage transmit sensing currents provided in an embodiment of the present application.

[0015] Figure 4 It is a schematic diagram of the implementation details of the "current imbalance detector" in the sub-stage provided by an embodiment of the present application.

[0016] Figure 5 It is a block diagram of a power stage sub-stage provided in an embodiment of the present application.

[0017] Figure 6 It is a diagram of implementation details of the arbitration module provided in one embodiment of the present application.

[0018] Figure 7 Detailed information of a resynchronization circuit in a sub-stage current detection module provided in an embodiment of the present application is shown in FIG.

[0019] Figure 8 Detailed information of a PWM interface module provided in one embodiment of the present application is shown in FIG.

[0020] In the drawings, like reference numbers generally indicate identical, functionally similar, and / or structurally similar elements. The drawing in which an element first appears is indicated by the leftmost digit(s) in the corresponding reference number. DETAILED DESCRIPTION

[0021] 1. Overview

[0022] On one hand, the present application provides a switching converter, which includes a power stage and a phase controller. The power stage is used to drive current through inductance within the duration specified by a periodic control signal; the phase controller is used to generate the periodic control signal so that the power stage generates a regulated power supply voltage; wherein the power stage is configured to communicate with the phase controller on a line; the power stage includes a first sub-stage and a second sub-stage, the first sub-stage and the second sub-stage respectively drive a first sub-current and a second sub-current through a number of corresponding inductors in response to the periodic control signal, and the number of corresponding inductors jointly provide the inductance; the line is used for the first sub-stage to communicate with the phase controller first, and then for the second sub-stage to communicate with the phase controller during the conversion period of the periodic control signal.

[0023] In one embodiment, the line transmission provides a current amplitude for the power stage, wherein, within a transformation period corresponding to the periodic control signal, the first sub-stage and the second sub-stage are respectively configured to: drive the first sub-current and the second sub-current on the line to twice the amplitude of their respective currents.

[0024] On the other hand, the present application also describes that the first sub-stage and the second sub-stage both include a comparison circuit and a modulation circuit, the comparison circuit is used to compare twice the amplitude of the first sub-current driven by the first sub-stage and twice the amplitude of the second sub-current driven by the second sub-stage; the modulation circuit is used to receive the periodic control signal and generate an adjustment control signal based on the comparison result of the comparison circuit, the adjustment control signal includes an adjustment duration, which is used to balance the amplitudes of the first sub-current and the second sub-current; wherein the adjustment control signals of the first sub-stage and the second sub-stage cause the first sub-stage and the second sub-stage to respectively respond to the periodic control signal to drive the first sub-current and the second sub-current through the corresponding inductors.

[0025] The following lists multiple embodiments to describe the present application from multiple aspects. However, it should be understood by those skilled in the art that the present application can be implemented without using one or more of these specific examples, or by other methods, components, or materials. In addition, some well-known structures, materials, or operations are not described in detail to avoid repeating the features disclosed in the present application. In addition, for the sake of brevity of description, this application only describes some combinations of features / characteristics, but the features / characteristics described in the present application can be combined in any way.

[0026] 2. System Implementation

[0027] Figure 1 1 is a block diagram of a system provided in an embodiment of the present application. The system 100 includes a power supply 110, a central processing unit (CPU) 120, a memory 130, a network interface 140, and a peripheral device 150. In one embodiment, the system 100 corresponds to a computer (a desktop computer, a laptop computer, etc.). In other embodiments, the system 100 may be other types of systems. It is understood that the modules of the system 100 may be more Figure 1 There are more or fewer modules in the .

[0028] The CPU 120 is typically a processor or a system on a chip (SoC), and is shown in the figure as receiving a pair of power supply voltages (Va and Vb) provided by the power supply 110 through corresponding lines 112A and 112B. For example, Va can be less than the voltage of Vb and can be used to power the core components of the CPU, which may include an arithmetic logic unit (ALU), a microprogram sequencer, registers, etc. Vb can be used to power the remaining components of the CPU 120, such as input / output (I / O) units, I / O buffers, on-chip peripherals, etc. The CPU 120 provides various signals to the power supply 110 through a bidirectional line / bus 121 (all signals are considered to be included in the bidirectional line / bus 121), which specify the power supply requirements for the power supply 110. Examples of these signals can be signals that specify a specific operating mode (in terms of power consumption), such as PS1, PS2, PS3, etc., which refer to "power saving states for improving efficiency". The CPU 120 receives operating status information of the power stage from the phase controller 210 through the bidirectional line / bus 121.

[0029] The memory 130 may be a memory including volatile and non-volatile memory. For example, in a personal computer, the memory may include magnetic memory (hard disk) and solid-state memory (RAM, flash memory, etc.). As shown in the figure, the memory 130 receives a power supply voltage through line 113 for powering various circuits and modules therein.

[0030] The network interface 140 is used to provide two-way communication between the system 100 and a computer network, or the Internet as it is generally referred to. The network interface 140 implements the electronic circuits required to communicate using a specific physical layer and data link layer standard, such as Ethernet or Wi-Fi™. The network interface 140 may also include a network protocol stack to allow communication with other computers on the same local area network (LAN) and other computers that communicate on a large scale network through routing protocols, such as the Internet Protocol (IP). The network interface 140 receives power via line 114 for powering internal circuits and modules. The network interface 140 receives / sends with an external system and CPU 120 via line 141 and line 124, respectively.

[0031] Peripheral device 150 represents one or more peripheral circuits, such as a speaker, a microphone, a user interface device, etc. Peripheral device 150 receives power through line 115 and communicates with external devices through line 151 .

[0032] The power supply 110 receives power from one or more energy sources (e.g., a battery) on line 101 and is used to provide the required power supply voltages for lines 112A, 112B, 113, 114, and 115. In one embodiment, the power supply 110 is configured to include one or more multi-phase DC-DC converters to generate the power supply voltages. The power supply 110 receives signals from the CPU 120 on line 121, which can be used to indicate the power mode to be run for a specific duration, wherein the power mode indicates the amount of power required / consumed by the CPU 120. The power supply 110 controls the multi-phase converter to reduce / increase the current output based on specific power consumption mode signals (e.g., PS1, PS2, and PS3).

[0033] In one embodiment, the power supply 110 is a voltage regulator module (VRM), sometimes also referred to as a processor power module (PPM), and includes one or more step-down switching (buck) converters for generating one or more smaller voltages from a higher voltage power supply. However, in other embodiments, the power supply 110 may also be other types of DC-DC converters, such as step-up, step-down, hysteresis converters, etc. In addition, the power supply 110 may be a stand-alone switching converter with only one power stage (thus not a multi-phase converter). Using a VRM, multiple devices / chips that require different power supply voltages can be installed on the same platform, such as a computer motherboard of a personal computer (PC).

[0034] The following will continue to describe Figure 2 Internal details of the VRM are shown.

[0035] 3. Voltage Regulator Module (VRM)

[0036] Figure 2 FIG. 1 is a specific block diagram of a VRM in one embodiment of the present application. Figure 1 ) is a voltage regulation module that generates two regulated voltages implemented by a multi-phase switching converter, namely two power supply lines (power lines), namely Va (240) (line-A) and Vb (250) (line-B). Nodes 240 and 250 can also be regarded as power lines. Figure 2 In the figure, the power supply for driving / generating Va and Vb is marked as 201 and has a voltage "Vin". In the VRM 110 of this embodiment, the value of Vi is about 21 volts (V). Similarly, the power supply voltage Vcc (202) shown in the figure can be provided by the phase controller 210 and can be used to power the modules in each power stage.

[0037] Although the technical features of the present application are described in the context of a multi-phase switching converter, it should be understood that these technical features can also be implemented in a single-phase switching converter as described above.

[0038] like Figure 2 As shown, VRM 110 includes phase controller 210, smart power stage (SPS) (or "power stage") SPSA-1 (220-1) ~ SPSA-3 (220-3), SPSB-1 ​​(230-1)) ~ SPSB-4 (230-4), inductors 225A-1 ~ 225A-3, and 227B-1 ~ 227B-4 and capacitors 226A-1 ~ 226A-3 and 228B-1 ~ 228B-4. Power supply Va (240) / (circuit-A) is generated by a three-phase buck converter (there are three SPS220-1 ~ 220-3), and power supply Vb (250) / (circuit-B) is generated by a four-phase buck converter (there are four SPS230-1 ~ 230-4). Nodes / lines 240 and 250 may correspond to Figure 1 For simplicity of description, Figure 2 Not shown are other power supply circuits that generate power on lines 113, 114, and 115. In other embodiments, VRM 110 may have more or fewer power supply lines and more or fewer power levels per power supply line.

[0039] In one embodiment of the present application, each power stage and phase controller may be a separate integrated circuit (IC). However, in other embodiments, the implementation of the power stage and phase controller may be different.

[0040] Phase controller 210 works in conjunction with one or more power stages of a power supply line to generate a regulated voltage as an output. Figure 2As shown, the phase controller 210 works in conjunction with one or more of the power stages SPSA-1 to SPSA-3 to generate a regulated voltage Va (240). Similarly, the phase controller 210 works in conjunction with one or more of the power stages SPSB-1 ​​to SPSB-4 to generate a regulated voltage Vb (250). Therefore, Va (240) and Vb (250) can be shown as inputs to the phase controller 210 to enable one or more feedback loops within the phase controller 210 to regulate the voltages Va and Vb. The phase controller 210 also receives inductor current information (regarding the current flowing through each inductor) from each SPS to perform various operations, such as current mode control for voltage regulation, current limiting, short circuit protection, and balancing the current generated by each SPS of the same converter (or "circuit") so that the currents of each SPS of the same circuit are substantially equal in magnitude. Other signals flowing between the phase controller 210 and the SPSs will be described below.

[0041] The phase controller 210 (with corresponding circuits therein), the SPS and corresponding inductors and capacitors combine to form a "phase" of a power supply line. Thus, for example, power stage SPSA-1, inductor 225A-1, capacitor 226A-1 and corresponding portions within phase controller 210 form a single buck converter, as well as one phase of a three-phase buck converter. It should be noted that although each phase is shown as having its own independent capacitor (e.g., 226A-1), in another embodiment, only a single larger capacitor (larger capacitance) can be used at node 240 (and 250). In other embodiments, multiple capacitors are placed near loads powered by corresponding supply voltages. For simplicity, a single SPS is also referred to as a phase of a power supply line.

[0042] Each SPS (or "power stage" as it is often called) can be implemented to include a high-side switch, a low-side switch, gate drive circuits for both switches, a temperature monitoring circuit, and an inductor current sensing circuit / module to provide information indicative of the magnitude of the inductor current to the phase controller 210. The current provided by the SPS, and therefore the corresponding inductor current, generally depends on the load current drawn from the supply voltage, although the high-side switch and the low-side switch of the SPS can be considered as elements that "drive" the inductor. Each SPS receives as input a power supply (they can all be the same power supply) that is connected to the high-side switch (shown in detail in the following section).

[0043] Each SPS communicates with the phase controller 210 via respective signals PWM, SYNC, CS and TEMPA. Thus, the power stage SPSA-1 is connected to the phase controller 210 via signals / lines PWMA-1 (211), SYNC-A (212), CSA-1 (213) and TEMPA (214). Figure 2 , the corresponding connections of signals PWMA-6, SYNC-A, and CSA-6 to phase controller 210 are not shown, but power stage SPSA-6 communicates with phase controller 210 via signals PWMA-6, SYNC-A, CSA-6, and TEMPA (214). Similarly, power stage SPSB-1 ​​is connected to phase controller 210 via signals / lines PWMB-1 (216), SYNC-B (217), CSB-1 (218), and TEMPB (219). Although in Figure 2 , the corresponding connections of the signals PWMB-3, SYNC-A and CSB-3 to the phase controller 210 are not shown, but the power stage SPSB-3 communicates with the phase controller 210 via the signals PWMB-3, SYNC-B, CSB-3 and TEMPB (219). The other SPSs are connected to the phase controller 210 in a similar manner. Typically, when the SPS is implemented as an integrated circuit, each SPS has PWM, SYNC, CS and TEMP pins for the above corresponding connections, and the corresponding signals from the phase controller 210 to the power stage can be generally referred to as the PWM, SYNC, CS and TEMP signals corresponding to the power stage.

[0044] Signal PWM is an input signal of the SPS from the phase controller 210, and represents a pulse width modulation (PWM) signal. The PWM signal can be generated to have a logic high state, a logic low state, or a high impedance (Hi-Z) state. Typically, the logic high state and the logic low state of the PWM signal correspond to the positive line voltage and the negative line voltage (within the error / noise tolerance) of the circuit power supply that generates the PWM signal, respectively, and the Hi-Z state corresponds to the middle line voltage of the power supply (or the voltage window around the middle line voltage), which is well known in the relevant art. However, other conventions may be used for these three states of the PWM signal, which will be apparent to those skilled in the art.

[0045] The PWM signal controls the opening and closing of the high-side switch and the low-side switch of the phase / power stage through the logic high state and the logic low state. Generally, the logic high state is used to connect (i.e. close) the high-side switch and disconnect the low-side switch (i.e. open) (the corresponding duration can be referred to as the "first interval"), while the logic low state is used to connect the low-side switch and disconnect the high-side switch (the corresponding duration can be referred to as the "second interval"). Each cycle of the PWM signal has a corresponding "first interval" and "second interval".

[0046] The Hi-Z state of the PWM signal indicates that the power stage will not work when generating the output voltage, that is, it is in an "inactive" state. Therefore, when the PWM is in the Hi-Z state, both the high-side switch and the low-side switch of the power stage are turned off, and the power stage can enter a low power consumption / power-off mode. Typically, the phase controller 210 is configured to generate the PWM signal in a manner that can represent three states, one of which indicates that the corresponding power stage will be in an inactive state. It can be appreciated by those skilled in the art that this three-state capability can be implemented in other ways. For example, the phase controller 210 can generate the PWM signal in the form of a traditional binary signal, and if the PWM signal is turned off (i.e., not generated at all), the power stage is implemented to recognize the Hi-Z state.

[0047] The duty cycle of the PWM signal is set by the phase controller 210 and is set to generate the required supply voltage and / or control / change the current provided by the phase. For example, the signal PWMB-1 has an amplitude of Vb and a duty cycle required by the current provided by the power stage SPSB-1. The magnitude of the current flowing through the inductor corresponding to the power stage depends on the conduction duration of the high-side switch and the low-side switch of the power stage and is set by the PWM input (or generally the control signal) of the power stage.

[0048] It is well known in the art that the PWM signals of each SPS of the same converter can be staggered, i.e., delayed in phase relative to each other, so that under normal circumstances, no two high-side switches of the line (i.e., in each SPS) are turned on at the same time. The reason for adopting this technical solution is to ensure that the peak instantaneous current drawn from Vin is always relatively low.

[0049] The signal SYNC is a common (single) input (e.g., SYNC-B (217)) of all SPSs of the power supply line, and the phase controller 210 can use this signal to wake up the corresponding SPS when the power supply 110 is powered on, and to indicate the power mode (e.g., PS2, PS3) of the multi-phase converter, i.e., the output current requirement. The signal SYNC is set to a high impedance (Hi-Z) state to indicate that the SPS will be turned off, i.e., all SPSs will be turned inactive and will not generate the corresponding power. In one embodiment, the Hi-Z state is a voltage level / bandwidth between the logic high level and the logic low level voltage levels of the SYNC signal.

[0050] The signal CS (current sense) is an input signal from the SPS / phase input to the phase controller 210 and contains information about the inductor current amplitude of the phase. This information can be in the form of current, voltage, digital value, etc., depending on the specific implementation of the power stage and the phase controller 210. The CS module (current sensing module) in the SPS implements the current sensing operation and sends the signal CS to the phase controller 210.

[0051] In one embodiment of the present application, the current sensing module of the power stage sends the sensed inductor current information to the phase controller 210 in the form of a current, which may have the same magnitude as the inductor current, or (more commonly) a reduced value (in terms of magnitude) of the inductor current. Accordingly, in this embodiment, the phase controller 210 is configured to receive information in the form of a current, and when the reduction method is used, the scaling factor is known to both the phase controller 210 and the (corresponding) power stage.

[0052] like Figure 2 As shown, the TEMP pins (or nodes) of all the stages of the power supply line are connected together and only a single TEMP input is provided to the phase controller 210. For example, for line B, a single connection TEMPB (219) is provided to the phase controller 210 based on the temperature feedback from each power stage of line B. This approach is generally adopted to minimize the number of wires / PCB (printed circuit board) traces (signals) from the power stages of the line to the phase controller 210, as well as to reduce the pin count (pin count) of the phase controller 210. The temperature of the power stage is directly proportional to (positively correlated with) the magnitude of the inductor current of the power stage.

[0053] As described above, the power stage is generally required to have the ability to provide a larger current. For example, it may be necessary to double the available power of line B (e.g., double the total current source capability while keeping the voltage Vb constant). This requirement can be met by doubling the number of power stages / phases of line B to eight. However, doubling the number of power stages to eight may require increasing the size of the board (printed circuit board / PCB) on which the components / modules of VRM 110 are assembled, and more importantly, the phase controller 210 may need to be redesigned / modified to support a larger number of power stages. For example, the phase controller 210 may require more pins and corresponding circuits.

[0054] The power capability of the line can be increased (e.g., doubled) by using a current doubling power stage configuration. In this configuration, two power stages are configured / connected in a "parallel" manner. Both power stages in this current doubling configuration receive and use the same PWM / control signal from the phase controller and provide a combined (single) current information to the phase controller.

[0055] However, one problem with this configuration is that there is an imbalance (inequality) between the respective currents provided by each power stage of the current doubling configuration. This imbalance may result because the phase controller receives only a single (combined) current information from the current doubling configuration and there is only one PWM signal used to control each power stage of the configuration.

[0056] As described below, the present application can achieve higher current (eg, current doubling) while also achieving current balancing. Furthermore, current balancing is achieved without increasing the number of pins for one or two power stages with doubled current.

[0057] 4. Power level

[0058] Figure 3A 300 is a block diagram of a power stage that can provide higher current in one embodiment of the present application. The power stage 300 includes two sub-stages 310 and 320. If higher current / power capability is required, the power stage 300 can be used instead of Figure 2 For example, by replacing the corresponding instance of power level 300 Figure 2 Each power stage of SPSB-1 ​​to SPSB-4 can be Figure 2 Alternatively, if doubled power is not required, only some of the power stages in SPSB-1 ​​to SPSB-4 may be replaced with corresponding instances of power stage 300. As will be apparent from the following description, power stage 300 and phase controller 210 (eg, Figure 2 The interface between Figure 2 The interface between the power stage and the phase controller 210 shown in FIG. 2 is the same.

[0059] Each sub-stage 310 and 320 is connected with Vin (201), Vcc (202), PWMB-1 (216) and SYNC-B (217) (such as Figure 2 “GND” stands for ground pin.

[0060] The "TMON" pin / node of each sub-stage provides temperature information. The TMON outputs are connected to each other and to the phase controller 210 via line TEMPB (219).

[0061] The "SW" (switch) pins / nodes of sub-stages 310 and 320 are connected to one end of the corresponding inductors 330 and 340, respectively. Each SW node is the connection node for the corresponding high-side and low-side power switches in the sub-stage. The other ends of inductors 330 and 340 are connected to node 250 (Vb), through which the regulated voltage of Rail-B is provided.

[0062] The "CS" pin / node of each sub-stage provides inductor current information. Generally, the inductor current information can take any suitable form, such as current, voltage, or digital value. In one embodiment of the present application, the inductor current information provided takes the form of a corresponding current (referred to herein as "sense current").

[0063] Therefore, the current SS1-cs (350) provided by the CS pin of sub-stage 310 represents the magnitude of the current flowing in inductor 330, while the current SS2-cs (360) provided by the CS pin of sub-stage 320 represents the magnitude of the current flowing in inductor 340. The two CS pins are connected to each other and to phase controller 210 via line CSB-1 (218).

[0064] Since sub-stages 310 and 320 each receive the same control signal PWMB-1, the respective output currents of the two sub-stages (the currents in inductor 330 and inductor 340, respectively) are nominally the same, and thus the total current provided to supply node Vb by the two sub-stages is Figure 2 The medium power stage SPSB-1 ​​provides twice the current. Therefore, the power stage 300 is a current doubling stage.

[0065] However, as discussed above, several factors may cause significant differences in the currents in inductor 330 and inductor 340. These causes of such current imbalances may be related to timing differences and component-to-component variations associated with the handling of PWM input heating in the sub-stages.

[0066] According to the content disclosed in an embodiment of the present application, sub-stage 310 and sub-stage 320 are configured to balance / equalize or at least minimize the difference in the magnitude of the corresponding currents in inductor 330 and inductor 340. In addition, this current balance is achieved without adding additional pins or additional output nodes to sub-stages 310 and 320, for example, pins for transmitting the respective inductor current amplitudes to each other. The terms "equalization" or "balance" used herein are intended to refer to the exact equality of currents as well as a smaller degree of inequality (for example, the maximum degree of inequality of the larger of the two currents is 5%). In one embodiment, the operation of the sub-stage is to minimize the difference in the average values ​​of the two currents within corresponding intervals (for example, a pair of consecutive PWM cycles).

[0067] According to one aspect of an embodiment of the present application, by designing and operating the sub-stages 310 and 320, current balancing is achieved by multiplying the corresponding sense current (amplitude) by two on the line CSB-1 (218) during the alternating cycles of the control signal PWMB-1 (216) without adding additional pins to the sub-stages 310 and 320. Figure 3B Example waveforms are shown for signal PWMB-1, sense current (SS1-cs 350) output by sub-stage 310, sense current (SS2-cs 360) output by sub-stage 320, and the signal on line CSB-1 (218).

[0068] Figure 3B Three cycles of the signal PWMB-1 are shown. In the example, it is assumed that the sub-stage 310 and the sub-stage 320 transmit their respective sense currents to the phase controller 210 in odd and even cycles, respectively. The signal PWMB-1 is a logic high level in the interval t31-t32 of the first cycle, and a logic low level in the interval t32-t33 of the first cycle. The signal PWMB-1 is a logic high level in the intervals t33-t34 and t35-t36 of the subsequent two cycles, and a logic low level in the intervals t34-t35 and t36-t37 of the subsequent two cycles. As shown in the figure, the sub-stage 310 provides twice the sense current SS1-cs in the first cycle and the third cycle of the signal PWMB-1, and the sub-stage 320 provides twice the sense current SS2-cs in the second cycle of the signal PWMB-1. From Figure 5 As can be observed in FIG. 1 , the sub-stages provide the corresponding information in alternating cycles. Thus, waveform SS1-cs is represented as zero in interval t33-t35, while waveform SS2-cs is represented as zero in intervals t31-t33 and t35-t37. The current on line CSB-1 is the sum of currents SS1-cs and SS2-cs.

[0069] As described above, the sensed current provided by each sub-stage represents twice its actual inductor current. Thus, for example, the waveform of SS1-cs in the interval t31-t33 represents twice the inductor current through the inductor 330 in that interval, while the waveform of SS2-cs in the interval t33-t35 represents twice the inductor current through the inductor 340 in that interval. This technical solution ensures that the total inductor current provided by the power stage 300 is indicated to the phase controller 210. In addition, the technology enables each of the two sub-stages to obtain the inductor current amplitude of the other sub-stage without the need for a separate pin or line to transmit the inductor current amplitude, thereby correcting the imbalance / inequality (if any) of the two inductor currents IL-330 (the current through the inductor 330 - the "first sub-current") and IL-340 (the current through the inductor 340 - the "second sub-current"). How this is achieved will be described below.

[0070] 5. Balance the inductor current

[0071] Figure 4 4 is a schematic diagram of the implementation details of the “current imbalance detector” in the sub-stage of an embodiment of the present application. The current imbalance detector 400 can be implemented in each of the sub-stages 310 and 320, and as shown in the figure, it includes a resistor 420, switches 430 and 440, capacitors 450 and 460, and a comparator 470. Figure 4 The pin / node "CS" in Figure 3A The “CS” pin / node of each sub-stage 310 and 320 is shown in FIG. 4. Line 421 shows connecting the CS pin / node to one end of resistor 420.

[0072] Switches 430 and 440 are closed only in alternating cycles of signal PWMB-1, and remain open otherwise. Figure 3B Referring to the "odd" and "even" conventions mentioned in the description of , switch 430 is closed (switch 440 is open) during odd cycles of signal PWMB-1 (when sub-stage 310 sends its sense current on its CS pin), and switch 440 is closed (switch 430 is open) during even cycles of signal PWMB-1 (when sub-stage 320 sends its sense current on its CS pin). Figure 3B, in the intervals t31-t33 and t35-t37, the switches 430 in the current imbalance detectors 400 in the sub-stages 310 and 320 will be closed (while the switches 440 of the two sub-stages are open), and in the intervals t33-t35, the switches 440 in the current imbalance detectors 400 in the sub-stages 310 and 320 will be closed (while the switches 430 of the two sub-stages are open). Therefore, the corresponding sense currents provided by the sub-stages are filtered through their respective RC filters (resistor 420 plus capacitor 450 and resistor 420 plus capacitor 460) and stored as corresponding voltages in capacitors 450 and 460, respectively. The voltage across each capacitor represents the average value of the corresponding current in the corresponding interval. Which sub-stage transmits its sense current to the phase controller in the odd cycles and which sub-stage transmits its sense current to the phase controller in the even cycles is determined according to the example techniques described below.

[0073] Comparator 470 (or generally "comparison circuit") compares the respective voltages across capacitors 450 and 460 and generates a comparison result, which in one embodiment is a binary signal, at its output 471. Depending on the comparison result, one or both sub-stages internally modify their respective copies of the (internal) signal PWMB-1. For example, if the voltage across capacitor 450 is greater than the voltage across capacitor 460, it means that the current provided by sub-stage 310 is greater than the current provided by sub-stage 320, and signal 471 is a logic high level in both sub-stages.

[0074] Therefore, the sub-stage 310 will reduce its inductor current IL-330 by reducing the pulse width (logic high duration) of its internal copy of the signal PWMB-1. In addition, or alternatively, the sub-stage 330 will increase its inductor current IL-340 by increasing the pulse width (logic high duration) of its internal copy of the signal PWMB-1. The extent of the increase or decrease of the internal copy of the signal PWMB-1 is predetermined and implemented in the circuit / module used for this purpose in the sub-stage, as shown in the example section below. In addition, the increase and / or decrease of the internal copy can be performed at the end of every two cycles of the signal PWMB-1 or other even multiples of a cycle of the signal PWMB-1. Alternatively, the increase and / or decrease of the internal copy of the signal PWMB-1 can also be performed at other rates, which will be obvious to those skilled in the art after reading the disclosure of this article. In general, the range from maximum increase to maximum decrease is limited by the expected current mismatch.

[0075] The "current balancing loop" consisting of module 400 and PWMB-1 "pulse regulator" is used to balance / equalize the two inductor currents IL-330 and IL-340. When balance is reached, the loop will stop further adjustment or correction of signal PWMB-1 (or alternate between minimum increase and minimum decrease in pulse width). Alternatively, comparator 470 can be implemented to include a dead band with a predetermined voltage range of about 0V, so that signal 471 is at either of the two logic levels only when the voltage difference between capacitors 450 and 460 exceeds the predetermined voltage range, otherwise signal 471 is tri-state (high impedance).

[0076] The implementation details of the sub-level in the embodiment of the present disclosure are described below.

[0077] 6. Child

[0078] Figure 5 It is a block diagram showing the implementation details of the sub-level in an embodiment of the present application. Figure 3A Each of the sub-stages 310 and 320 can be implemented as follows Figure 5 The sub-stage 500 is shown. The sub-stage 500 includes a gate driver 510, a high-side (HS) switch 520, a low-side (LS) switch 530, a current sensing module 550, a current imbalance detector 400, an arbitration module 560 and a PWM interface 570. Figure 5 Also shown is an inductor 580 (corresponding to Figure 3A Inductor 330 or inductor 340) and capacitor 228B-1 ( Figure 2 When the sub-stage 500 is implemented as an integrated circuit (IC), P51 to P55 represent pins SW, CS, Vin, Vcc, and PWM ( Figure 3A Any of the sub-stages 310 and 320 shown). In an alternative implementation (e.g., in discrete form), P31 to P35 represent corresponding circuit nodes. Vcc (202) is used to power the internal modules of sub-stage 500. The drain of HS switch 520 is connected to Vin (201), and the source of LS switch 530 is grounded. Although for the sake of simplicity, Figure 5 Not shown, but sub-stage 500 may include various other modules / circuits, such as a level shifter for gate driver 510, a temperature sensor, etc.

[0079] The current imbalance detector 400 is implemented as follows Figure 4 Line 421 is the connection from CS pin P52 to module 400, specifically, to resistor 420 ( Figure 4 ) connection.

[0080] The PWM interface 570 receives the PWM signal PWMB-1 (216) (from the phase controller 210) and the pulse width adjustment signal 471 (from the current imbalance detector 400). The internal inverter generates the inverse signal of the signal 471. The signal 471 can be regarded as an "increase pulse width" or UP signal (575), while its inverse signal can be regarded as a "decrease pulse width" or DN signal (576). Depending on the logic level of the signal 471 (UP / increase, or DN / decrease), the PWM interface 570 increases or decreases the pulse width (logic high level duration) of the signal PWMB-1 and forwards the adjusted signal PWMB-1 to the gate driver 510. When the signal PWMB-1 is in the Hi-Z (high impedance) state (the voltage of the signal PWMB-1 is approximately between the state representing the logic high level and the logic low level), the PWM interface 570 forwards the signal PWMB-1 without any adjustment / change. The PWM interface 570 can be regarded as a "modulator" for modulating the pulse width of the signal PWMB-1 according to the signal 471. Refer to the following Figure 8 An example implementation of the PWM interface 570 in an embodiment is described.

[0081] The gate driver 510 receives the adjusted signal PWMB-1, generates a corresponding voltage according to the logic level of the adjusted signal PWMB-1, and connects and disconnects the HS switch 520 and the LS switch 530 at corresponding intervals. Therefore, the gate driver 510 connects the HS switch 520 and disconnects the LS switch 530 during the logic high level duration of the adjusted signal PWMB-1. During the logic low level period of the adjusted signal PWMB-1, the gate driver 510 disconnects the HS switch 520 and connects the LS switch 530.

[0082] The HS switch 520 and the LS switch 530 are implemented as N-channel MOSFETs (metal oxide semiconductor field effect transistors), respectively, and the gate driver 510 drives the gates of the MOSFETs. Of course, there are other ways to implement the switches. Figure 5 In the example of FIG. 5 , when the adjusted signal PWMB-1 is logic high, the gate driver 510 generates appropriate voltages on lines 512 (en-HS) and 513 (en-LS) to connect MOSFET 520 and disconnect MOSFET 530, respectively. When the adjusted signal PWMB-1 is logic low, the gate driver 510 generates appropriate voltages on lines 512 and 513 to disconnect MOSFET 520 and connect MOSFET 530, respectively. When the signal PWMB-1 is in a Hi-Z (high impedance or intermediate level) state, the gate driver 510 generates appropriate voltages on lines 512 and 513 to disconnect MOSFET 520 and 530, respectively. The gate driver 510 can be implemented in a known manner.

[0083] The current sensing module 550 determines the magnitude (e.g., instantaneous magnitude) of the inductor current through the inductor 580 and provides a sense current indicative of the magnitude of the inductor current at a node 551 connected to a pin P52 (CS). The pin P52 is connected to the phase controller 210 via line CSB-1 (218). The current sensing module 550 may determine the magnitude of the inductor current using one of several known methods. For example, in Figure 5 , the current sensing module 550 receives input signals 525 and 535 from the HS switch 520 and the LS switch 530, respectively. In one embodiment, the signals 525 and 535 represent the voltage drop across the HS and LS switches when the corresponding switches are in the on state and the current flows through the HS and LS switches and the inductor 227B-1. The current sensing module 550 obtains the instantaneous amplitude of the inductor current (or a scaled-down version thereof) based on the voltage drop. In one embodiment, the current sensing module 550 provides / reports the inductor current amplitude in the form of a (replicated) current (sense current) whose amplitude is scaled-down relative to the instantaneous inductor current amplitude. However, in alternative embodiments, the current sensing module 550 can be implemented to provide information in the form of a voltage or a digital value.

[0084] As described above, the two sub-stages of the power stage 300 should transmit corresponding sense currents only during alternating cycles of the PWM signal. Therefore, the current detection module 550 of one of the sub-stages must be designated to transmit its sense current only during odd cycles, while the current detection module 550 of the other sub-stage must be designated to transmit its sense current only during even cycles. The current detection module 550 is implemented to include an internal switch (or other suitable "disabling circuit") that electrically connects its output node (the node providing the sense current) to line 551, and thereby to pin P52, only during odd cycles of signal PWMB-1 or even cycles of signal PWMB-1, depending on the above designation. This capability also allows the current imbalance detector 400 to receive the sense current transmitted by the current detection module of the other sub-stage of the pair during the corresponding cycle, thereby achieving the comparison and current balancing described herein.

[0085] In one embodiment of the present application, after power-on / reset, the two sub-stages are allowed to start normal operation to generate the voltage Vb (i.e., the power switches HS switch and LS switch start switching based on the signal PWMB-1, providing corresponding sensing currents on their respective CS pins, etc.), and only when the two sub-stages transmit their respective sensing currents within the same cycle of the signal PWMB-1, one sub-stage is forced to "resynchronize", that is, its sensing current is offset by one cycle of the signal PWMB-1, and then its sensing current is transmitted every other cycle of the signal PWMB-1, while the other sub-stage continues to transmit its sensing current in the previous manner without any changes. This forcing is achieved by assigning a logic 1 to one sub-stage and a logic 0 to the other sub-stage, and by convention, the sub-stage assigned with the logic 1 will perform the above-mentioned transmission and recovery transitions.

[0086] In one embodiment, the current detection module of each sub-stage includes a detection circuit (not shown) for detecting the respective sensed currents transmitted simultaneously in the same PWM cycle. The detection circuit compares the voltage difference ( Figure 4 ), and the voltage difference is compared to a threshold voltage. When the two sub-stages transmit their respective sense currents simultaneously in the same cycle, the voltage difference between capacitors 450 and 460 will be large (typically, much larger than the voltage difference when the sub-stages transmit sense currents only in alternating cycles). If the voltage difference is greater than the threshold voltage, the detection circuit issues a logic signal to indicate simultaneous transmission (i.e., in the same cycle). The state of the logic signal is used to cause the sub-stage assigned a logic 1 to shift its transmission of sense current by one cycle. The detection circuit can be implemented in a known manner, and the threshold voltage can be preset according to, for example, the specifications and / or operating parameters of the sub-stages. Figure 7 The circuit of (described below) illustrates an example circuit for causing such a transmission offset (which can be considered a "resynchronization"), which will be described next.

[0087] Figure 7Detailed circuit diagram showing the "re-synchronization circuit" in the current detection module 550 in the embodiment of the present application. The circuit includes a flip-flop 710, an inverter 720 and an XNOR gate 730. The output terminal 735 of the XNOR gate 730 is connected to the data input terminal (D) of the flip-flop 710. The output terminal (Q) of the flip-flop 710 is connected to the XNOR gate 730 and the inverter 720 as an input. The output 721 of the inverter 720 is used to close or open the switch between the internal node and the line 551 of the current detection module 550 according to its logic level (as described above). Signal 731 (Re-sync) is the logical AND result of the output of the detection circuit and the logic level assigned to the sub-stage by its arbitration module. Therefore, if the detection circuit detects the simultaneous transmission of the respective sensed currents from the two sub-stages in the same PWM cycle, and the logic level assigned to the sub-stage is a logic high level / 1, then the signal 731 is a high level, otherwise, the signal 731 is a low level. The flip-flop 710 receives the signal PWMB- 1 at its clock terminal CLK and receives an enable signal 711 (en-CB) for enabling / disabling current balancing at its reset input terminal (rst\).

[0088] Now describe Figure 7 The operation of the circuit shown in the sub-stage assigned a logic 1. When current balancing is enabled and the Re-sync signal 731 is a logic 0 (indicating that the two sub-stages are not "simultaneously transmitting" sense current in the same PWM cycle), the output terminal Q (and the signal 721) switches at each rising edge of the signal PWMB-1. Therefore, the sense current output of the sub-stage 500 is provided on the line 551 every other cycle (for example, odd cycles, the other sub-stage sends its sense current in even cycles). However, if the Re-sync signal 731 is a logic 1, then the output terminal Q also maintains its current logic level (i.e., the logic level in the current PWM cycle) in the next PWM cycle. Therefore, the signal 721 also maintains its current value in the next PWM cycle. Therefore, the sense current transmitted from the two sub-stages is forced to be in the alternating cycles of the signal PWMB-1 starting from the next PWM cycle, which also causes the detection circuit to set the Re-sync signal to a logic 0 in the next PWM cycle. The child assigned a logic 0 will not change the duration of its sense current transmission because its resynchronization signal 731 will be a logic 0, thus continuing to transmit its sense current during every other PWM cycle.

[0089] In another embodiment of the present application, the assignment of logic 1 and logic 0 to the above-mentioned sub-stages is performed at power-on / reset and before starting the above-mentioned normal operation (including the transmission of the sense current). At the beginning of normal operation, the sub-stage assigned with logic 1 transmits its sense current only in the odd cycles of the signal PWMB-1, and the sub-stage assigned with logic 0 transmits its sense current only in the even cycles of the signal PWMB-1. In an alternative embodiment, the current detection module 550 can be designed in a known manner to support such a feature. In such an embodiment, the above-mentioned resynchronization is not required.

[0090] Assigning a logic 1 to one child and a logic 0 to another child can be accomplished in one of several known ways. In one embodiment of the present application, this assignment is performed by arbitration module 560, which is described below in conjunction with Figure 6 Give a description.

[0091] In another embodiment, this assignment is not performed by arbitration module 560. Instead, two modes of sub-stages are manufactured (e.g., with different part numbers). One mode is configured with a non-volatile memory (NVM) that is pre-programmed to store a logic 1, and the other mode is configured with a non-volatile memory (NVM) that is pre-programmed to store a logic 0. The user then uses one sub-stage in each of the two modes. In another embodiment of the present application, instead of pre-programmed bits in the NVM, each sub-stage is configured with an input pin that the user can connect to a logic high voltage or a logic low voltage to assign a logic 1 or logic 0.

[0092] The implementation details of the arbitration module 560 in the embodiment of the present application will be described below.

[0093] 7. Arbitration module

[0094] Figure 6 Schematic diagram showing implementation details of the arbitration module in the embodiment of the present application. The arbitration modules 560A and 560B are implemented in the same manner and are included in the sub-stages 310 and 320 respectively ( Figure 3A ). As shown in the figure, arbitration module 560A / 560B includes noise generator 610A / 610B, middle line sensor 620A / 620B, clock generator 612A / 612B, switch 630A / 630B, switch 650A / 650B, resistor 640A / 640B and resistor 660A / 660B. Only the implementation and operation of the internal modules of arbitration module 560A are described below. The corresponding internal modules of arbitration module 560B are implemented and operated in a similar manner.

[0095] The clock generator 612A generates a clock signal (also referred to herein by the numeral 612A).

[0096] Noise generator 610A represents a random noise sequence generator in bit form and receives clock 612A. Noise generator 610A generates a corresponding bit of the random sequence and the logical complement of the bit on lines 613A and 615A respectively on each clock cycle (e.g., rising edge) of clock 612A, and each bit causes switches 630A and 650A to close or open respectively. The implementation of noise generator 610A makes the probability that the output bits of 610A and 610B are different at the clock edge non-zero. In one embodiment, noise generator 610A is an analog noise generator.

[0097] The mid-line sensor 620A receives the clock 612A. At each clock cycle (e.g., rising edge), the mid-line sensor 620A measures the voltage on pin P52A. If the measured voltage is approximately 1.7V (mid-line voltage, Vcc is 3.3V), the mid-line sensor 620A sends a command to the noise generator 610 on line 621A to stop further operations and sends the current bit (on 615A) on line 561A.

[0098] The resistance values ​​of resistors 640A and 660A are substantially equal. Switches 630A and 650A are closed or open according to the logic level control of the bits on lines 613A and 615A, respectively.

[0099] Pin P52A is connected to the junction of switches 630A and 650A via line 562A.

[0100] The clock frequencies of the two arbitration modules may be the same, and the phases of the clocks may be synchronized in a known manner.

[0101] In one embodiment of the present application, arbitration modules 560A and 560B operate together in the manner described below to assign corresponding logic levels to the two sub-stages after VRM 110 (and its sub-stages) is powered up and before the switching operation of the corresponding power switches (520 and 530) in each sub-stage (thereby transmitting the sense current on line CSB-1). Once the logic levels are assigned, both arbitration modules can be powered down and all switches 630A, 630B, 650A and 650B can be opened. Alternatively, pin P52A and pin P52B are disconnected from lines 562A and 562B, respectively, such as using switches (not shown).

[0102] Each arbitration module 560A and 560B pulls line CSB-1 up (to Vcc) or down (to ground) depending on the output of the corresponding noise generator (i.e., the bit on lines 613A / 615A and 613B / 615B). If both modules 560A and 560B pull CSB-1 up, the corresponding mid-line sensor will detect a voltage approximately equal to Vcc. If both modules 560A and 560B pull CSB-1 down, the corresponding mid-line sensor will detect a voltage approximately equal to 0V (ground).

[0103] However, if one module pulls CSB-1 up and the other module pulls CSB-1 down, each mid-line sensor will detect a voltage approximately midway between Vcc and ground (1.7V). When this detection occurs, the arbitration operation stops and the corresponding mid-line sensor sends a command to the corresponding noise generator to freeze operation (i.e., generate the next noise bit). Now, one of the lines 561A and 561B will have a logic 1 and the other a logic 0. This achieves the assignment of a logic 1 to one child and a logic 0 to the other child. The corresponding logic levels are retained within the child as long as the child is powered.

[0104] Figure 8 5 is a diagram showing the details of the PWM interface 570 (modulator) in an embodiment of the present application. The PWM interface 570 includes current sources 810 and 820, a P-channel MOSFET (PMOS) 830, an N-channel MOSFET (NMOS) 840, and an inverter 850. The currents of the current sources 810 and 820 are determined by the signals UP (575) and DN (576) generated within the PWM interface 570, respectively (as described above). When UP is a logic high level (DN is a logic low level), the current through the current source 810 increases (and is therefore greater than the current through the current source 820). Therefore, the falling edge of the signal PWMB-1 is delayed by a corresponding duration, thereby increasing the pulse width of the signal 571 (here, the logic high duration). On the other hand, when DN is a logic high level (UP is a logic low level), the current through the current source 820 increases (and is therefore greater than the current through the current source 810). Therefore, the rising edge of the signal PWMB- 1 is delayed by a corresponding duration, thereby reducing the pulse width (here, the logic high duration) of the signal 571 .

[0105] 8. Conclusion

[0106] References in this specification to "one embodiment", "an embodiment" or similar language mean that a particular feature, structure or characteristic described in conjunction with the embodiment is included in at least one embodiment of the present disclosure. Therefore, the phrases "in one embodiment", "in an embodiment" and similar language appearing in this specification may, but do not necessarily, all refer to the same embodiment.

[0107] And in Figure 1 , 2 , 3A, 4, 5, 6, 7 and 8, although the terminals / nodes are shown as being directly connected (i.e., "connected to") to various other terminals, it should be understood that there may be other components in the circuit (as appropriate to the particular environment), so these connections can be considered to be "electrically coupled" to the same connection terminal.

[0108] It should be understood that the specific types of transistors described above (e.g., NMOS, PMOS, etc.) are for illustration purposes only. However, alternative embodiments using different configurations and transistors will be apparent to those skilled in the art by reading the disclosure provided herein. For example, NMOS transistors may be replaced with PMOS (P-channel MOS) transistors, and the connections of the power and ground terminals may also be swapped.

[0109] Therefore, in this application, the power supply and ground terminals are referred to as constant reference potential points, the source (emitter) and drain (collector) terminals of the transistor (although providing a current path when turned on and an open path when turned off) are referred to as current terminals, and the gate (base) terminal is referred to as the control terminal.

[0110] The above examples are only preferred embodiments of the present application, and certainly cannot be used to limit the scope of the present application. Therefore, the breadth and scope of the present disclosure should not be limited by any of the above examples, but should only be defined according to the following claims and their equivalents.

Claims

1. A switching converter, characterized in that: include: a power stage for driving current through the inductor for a duration specified by a periodic control signal; a phase controller for generating the periodic control signal so that the power stage generates a regulated power supply voltage; The power stage is configured to communicate with the phase controller on a line; the power stage includes a first sub-stage and a second sub-stage, the first sub-stage and the second sub-stage respectively drive a first sub-current and a second sub-current through a plurality of corresponding inductors in response to the periodic control signal, and the plurality of corresponding inductors jointly provide the inductance; within a conversion period of the periodic control signal, the line is first used for the first sub-stage to communicate with the phase controller, and then used for the second sub-stage to communicate with the phase controller.

2. The switching converter according to claim 1, wherein: The line transmission provides a current amplitude for the power stage, wherein, within a conversion period corresponding to the periodic control signal, the first sub-stage and the second sub-stage are respectively configured to: drive the first sub-current and the second sub-current on the line to twice the amplitude of their respective currents.

3. The switching converter according to claim 2, characterized in that: The first sub-level and the second sub-level both include: a current imbalance detector for comparing twice the magnitude of a first sub-current driven by the first sub-stage and twice the magnitude of a second sub-current driven by the second sub-stage; A modulation circuit is used to receive the periodic control signal and generate an adjustment control signal based on the comparison result of the current imbalance detector, wherein the adjustment control signal includes an adjustment duration and is used to balance the amplitudes of the first sub-current and the second sub-current; wherein the adjustment control signals of the first sub-stage and the second sub-stage enable the first sub-stage and the second sub-stage to respectively respond to the periodic control signal to drive the first sub-current and the second sub-current through the corresponding inductor.

4. The switching converter according to claim 3, wherein: The first sub-stage and the second sub-stage each include a high-side switch and a low-side switch, and the high-side switch and the low-side switch periodically control the corresponding inductor at a first interval and a second interval respectively based on the adjustment control signal, wherein the current amplitude flowing through the corresponding inductor is determined by the turn-on duration of the high-side switch and the turn-on duration of the low-side switch in the adjustment control signal.

5. The switching converter according to claim 4, characterized in that The first sub-stage and the second sub-stage include a first arbitration module and a second arbitration module coupled to the line, respectively; wherein, when the power stage is powered on and before the corresponding high-side switches and low-side switches in the first sub-stage and the second sub-stage perform switching operations, the first arbitration module and the second arbitration module cooperate to assign one of the first logic level and the second logic level to the first sub-stage, and assign the other of the first logic level and the second logic level to the second sub-stage; Among them, the sub-stage assigned with the first logic level drives the corresponding sub-current to twice the amplitude only in the odd cycles of the periodic control signal, and the sub-stage assigned with the second logic level indicates twice the amplitude of the corresponding sub-current only in the even cycles of the periodic control signal.

6. The switching converter according to claim 5, characterized in that The first arbitration module and the second arbitration module both include: A clock generator, used for generating a clock signal; A noise generator, configured to receive the clock signal and generate a binary bit and the inverse of the binary bit in a random binary noise sequence in each cycle of the clock signal; A first resistor and a first switch are connected in series between the line and a first constant reference potential point, wherein the opening and closing of the first switch is controlled by the binary bit; a second resistor and a second switch connected in series between the line and a second constant reference potential point, wherein the opening and closing of the second switch is controlled by the inverse code of the binary bit; and An intermediate line sensor is used to receive the clock signal. The intermediate line sensor is also coupled to the line. The intermediate line sensor determines the voltage on the line during each cycle of the clock signal.

7. The switching converter according to claim 6, wherein: When the switching converter is powered on and before the corresponding high-side switch and low-side switch start switching operations, the first arbitration module and the second arbitration module are configured in each cycle of the clock signal as follows: generating binary output and complement of the random binary noise sequence by respective noise generators; Closing and opening corresponding switches according to the binary output and the complement code; The voltage on the line is measured using a corresponding intermediate line sensor, wherein if the voltage is not an intermediate voltage between the first constant reference potential point and the second constant reference potential point, the steps of generating, closing and opening, and measuring are repeated, wherein if the voltage is an intermediate voltage between the first constant reference potential point and the second constant reference potential point, corresponding logic levels are assigned to the first sub-stage and the second sub-stage according to the current binary output values ​​of the first arbitration module and the second arbitration module, and the operation is stopped; wherein the assigned logic level is one of the first logic level and the second logic level.

8. The switching converter according to claim 3, wherein: The current imbalance detector comprises: a third resistor, a third switch, a fourth switch, a first capacitor, a second capacitor and a comparator; wherein: A first end of the third resistor is coupled to the line, and a second end of the third resistor is coupled to first ends of each of the third switch and the fourth switch; The first capacitor is coupled between the second end of the third switch and the second constant reference potential point; The second capacitor is coupled between the second end of the fourth switch and the second constant reference potential point; and A connection node between the first capacitor and the second end of the third switch is coupled to a first input terminal of the comparator, a connection node between the second capacitor and the second end of the fourth switch is coupled to a second input terminal of the comparator, and an output terminal of the comparator provides a logic signal representing the comparison result.

9. The switching converter according to claim 8, characterized in that: The modulation circuit comprises: A P-channel metal oxide semiconductor field effect transistor (PMOS), an N-channel metal oxide semiconductor field effect transistor (NMOS), a first current source and a second current source, a first inverter and a second inverter; wherein: The first inverter is used to receive the logic signal and generate a logical inversion of the logic signal; The magnitudes of the currents flowing through the first current source and the second current source are determined by the logic signal and the logical inverse of the logic signal, respectively; The first current source is coupled between the first constant reference potential point and the first current terminal of the PMOS; The second current source is coupled between the second constant reference potential point and the first current terminal of the NMOS; The second current terminal of the PMOS and the second current terminal of the NMOS are connected to a connection node, and the connection node is also coupled to the input terminal of the second inverter; The control terminals of the PMOS and NMOS are used to receive the periodic control signal, and The output terminal of the second inverter provides the regulation control signal.

10. The switching converter according to claim 9, characterized in that The first sub-stage and the second sub-stage each further include a detection circuit for comparing a voltage difference between the first capacitor and the second capacitor with a threshold voltage; If the voltage difference is greater than the threshold voltage, the detection circuit sends a second logic signal to indicate that the first sub-stage and the second sub-stage drive the first sub-current to twice the amplitude and the second sub-current to twice the amplitude respectively in the same cycle of the periodic control signal; wherein: The first sub-stage and the second sub-stage each further include: a flip-flop, a third inverter, and an exclusive-OR (XNOR) gate; an output terminal (Q) of the flip-flop is coupled to an input terminal of the third inverter and a first input terminal of a pair of input terminals of the XNOR gate, wherein the output terminal of the third inverter enables or disables the line communication according to a logic level of the output; A second input terminal of the pair of input terminals of the XNOR gate is used to receive a resynchronization signal representing a logical AND of the second logic signal and a logic level assigned to a corresponding sub-stage; The output of the XNOR gate is coupled to the data (D) input of the flip-flop; The clock input terminal of the trigger is used to receive the period control signal, and the reset input terminal of the trigger is used to receive an enable signal indicating whether to perform current balancing; If the resynchronization signal is at a logic high level, the output terminal of the third inverter maintains the current state in the next cycle of the control signal, so that the sub-stage with a logic level of 1 is assigned to drive the corresponding sub-current to twice the amplitude through one cycle of the periodic control signal.

11. A power stage, characterized in that Used to drive current through inductance within the duration specified by a periodic control signal; wherein the periodic control signal is generated by an external phase controller, so that the power stage generates a regulated power supply voltage, wherein the power stage is configured to communicate with the phase controller on a line; the power stage comprises a first sub-stage and a second sub-stage, wherein the first sub-stage and the second sub-stage drive a first sub-current and a second sub-current respectively through a plurality of corresponding inductors in response to the periodic control signal, and the plurality of corresponding inductors jointly provide the inductance; within the conversion period of the periodic control signal, the line is first used for the first sub-stage to communicate with the phase controller, and then for the second sub-stage to communicate with the phase controller.

12. The power stage of claim 11, wherein: The line transmission provides a current amplitude for the power stage, wherein, within a conversion period corresponding to the periodic control signal, the first sub-stage and the second sub-stage are respectively configured to: drive the first sub-current and the second sub-current on the line to twice the amplitude of their respective currents.

13. The power stage of claim 12, wherein: The first sub-level and the second sub-level both include: a current imbalance detector for comparing twice the magnitude of a first sub-current driven by the first sub-stage and twice the magnitude of a second sub-current driven by the second sub-stage; A modulation circuit is used to receive the periodic control signal and generate an adjustment control signal based on the comparison result of the current imbalance detector, wherein the adjustment control signal includes an adjustment duration and is used to balance the amplitudes of the first sub-current and the second sub-current; wherein the adjustment control signals of the first sub-stage and the second sub-stage enable the first sub-stage and the second sub-stage to respectively respond to the periodic control signal to drive the first sub-current and the second sub-current through the corresponding inductor.

14. The power stage of claim 13, wherein: The first sub-stage and the second sub-stage each include a high-side switch and a low-side switch, wherein the high-side switch and the low-side switch periodically control the corresponding inductor at a first interval and a second interval, respectively, based on the regulation control signal, wherein the current amplitude flowing through the corresponding inductor is determined by the on-time duration of the high-side switch and the on-time duration of the low-side switch in the regulation control signal.

15. The power stage of claim 14, wherein: The first sub-stage and the second sub-stage include a first arbitration module and a second arbitration module coupled to the line, respectively; wherein: When the power stage is powered on and before the high-side switch and the low-side switch in the first sub-stage and the second sub-stage perform a switching operation, the first arbitration module and the second arbitration module cooperate to assign one of a first logic level and a second logic level to the first sub-stage, and assign the other of the first logic level and the second logic level to the second sub-stage; The sub-stages assigned the first logic level drive the corresponding sub-currents to twice the amplitude only in odd cycles of the periodic control signal, and the sub-stages assigned the second logic level drive the corresponding sub-currents to twice the amplitude only in even cycles of the periodic control signal.

16. The power stage of claim 15, wherein: The first arbitration module and the second arbitration module both include: A clock generator, used for generating a clock signal; A noise generator, configured to receive the clock signal and generate a binary bit and the inverse of the binary bit in a random binary noise sequence in each cycle of the clock signal; A first resistor and a first switch are connected in series between the line and a first constant reference potential point, wherein the opening and closing of the first switch is controlled by the binary bit; a second resistor and a second switch connected in series between the line and a second constant reference potential point, wherein the opening and closing of the second switch is controlled by the inverse code of the binary bit; and An intermediate line sensor is used to receive the clock signal. The intermediate line sensor is also coupled to the line. The intermediate line sensor determines the voltage on the line in each cycle of the clock signal.

17. The power stage of claim 16, wherein: When the switching converter is powered on and before the corresponding high-side switch and low-side switch start switching operations, the first arbitration module and the second arbitration module are configured in each cycle of the clock signal as follows: generating binary output and complement of the random binary noise sequence by respective noise generators; Closing and opening corresponding switches according to the binary output and the complement code; Use the corresponding intermediate line sensor to measure the voltage on the line, wherein, if the voltage is not the intermediate voltage between the first constant reference potential point and the second constant reference potential point, repeat the steps of generating, closing and opening, and measuring, wherein, if the voltage is the intermediate voltage between the first constant reference potential point and the second constant reference potential point, assign corresponding logic levels to the first sub-stage and the second sub-stage according to the current binary output values ​​of the first arbitration module and the second arbitration module, and stop the next step of operation; wherein the assigned logic level is one of the first logic level and the second logic level.

18. The power stage of claim 13, wherein: in: A first end of the third resistor is coupled to the line, and a second end of the third resistor is coupled to first ends of each of the third switch and the fourth switch; The first capacitor is coupled between the second end of the third switch and the second constant reference potential point; The second capacitor is coupled between the second end of the fourth switch and the second constant reference potential point; and A connection node between the first capacitor and the second end of the third switch is coupled to a first input terminal of the comparator, a connection node between the second capacitor and the second end of the fourth switch is coupled to a second input terminal of the comparator, and an output terminal of the comparator provides a logic signal representing the comparison result.

19. The power stage of claim 18, wherein: The modulation circuit comprises: A P-channel metal oxide semiconductor field effect transistor (PMOS), an N-channel metal oxide semiconductor field effect transistor (NMOS), a first current source and a second current source, a first inverter and a second inverter; wherein: The first inverter is used to receive the logic signal and generate a logical inversion of the logic signal; The magnitudes of the currents flowing through the first current source and the second current source are determined by the logic signal and the logical inverse of the logic signal, respectively; The first current source is coupled between the first constant reference potential point and the first current terminal of the PMOS; The second current source is coupled between the second constant reference potential point and the first current terminal of the NMOS; The second current terminal of the PMOS and the second current terminal of the NMOS are connected to a connection node, and the connection node is also coupled to the input terminal of the second inverter; The control terminals of the PMOS and NMOS are used to receive the periodic control signal, and The output terminal of the second inverter provides the regulation control signal.

20. The power stage of claim 19, wherein: The first sub-stage and the second sub-stage each further include a detection circuit for comparing a voltage difference between the first capacitor and the second capacitor with a threshold voltage; If the voltage difference is greater than the threshold voltage, the detection circuit sends a second logic signal to indicate that the first sub-stage and the second sub-stage drive the first sub-current to twice the amplitude and the second sub-current to twice the amplitude respectively in the same cycle of the periodic control signal; wherein: The first sub-stage and the second sub-stage each further include: a flip-flop, a third inverter, and an exclusive-OR (XNOR) gate; an output terminal (Q) of the flip-flop is coupled to an input terminal of the third inverter and a first input terminal of a pair of input terminals of the XNOR gate, wherein the output terminal of the third inverter enables or disables the line communication according to a logic level of the output; A second input terminal of the pair of input terminals of the XNOR gate is used to receive a resynchronization signal representing a logical AND of the second logic signal and a logic level assigned to a corresponding sub-stage; The output of the XNOR gate is coupled to the data (D) input of the flip-flop; The clock input terminal of the trigger is used to receive the period control signal, and the reset input terminal of the trigger is used to receive an enable signal indicating whether to perform current balancing; If the resynchronization signal is at a logic high level, the output terminal of the third inverter maintains the current state in the next cycle of the control signal, so that the sub-stage with a logic level of 1 is assigned to drive the corresponding sub-current to twice the amplitude through one cycle of the periodic control signal.

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