Formation method of memory structure
By forming a protective structure on the sidewall surface of the memory gate structure during the formation of the memory structure, the problem of rounding of the floating gate sharp corners is solved, the erasing efficiency of the memory is improved, the process flow is simplified, and the cost is reduced.
Patent Information
- Application Number
- CN202310671283.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-06-07
- Publication Date
- 2024-12-10
AI Technical Summary
In the process of integrating embedded flash memory with monolithic devices, the high-temperature oxidation process leads to rounding of the floating gate sharp corners, reducing the interface electric field strength and erasing efficiency.
During the formation of the memory structure, a protective structure is formed on the sidewall surface of the memory gate structure to avoid floating gate oxidation, and oxidation is performed in the logic region, the modified region and the protection structure to form a gate oxygen layer and erased gate oxidation. simplifies process flow and reduces costs.
Protect the floating gate surface to avoid oxidation, maintain local electric field strength, improve the erasing efficiency of the memory, simplify the process flow, and reduce process costs.
Smart Images
Figure CN119110587A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor manufacturing technology, and in particular to a method for forming a memory structure. Background Art
[0002] Embedded or non-volatile flash memory is a non-volatile memory widely used in the automotive, consumer and other fields. With the rapid increase in the market demand for new energy vehicles in recent years, the performance and cost requirements have also increased rapidly. The design of integrating microcontroller units (MCUs) with flash memory has emerged. Semiconductor development focuses on the layout and development of a process platform that combines embedded flash memory with monolithic device integration. This platform integrates memory, power devices and logic operation devices on the same wafer.
[0003] Currently, most of the charges in stacked-gate flash memories are stored in the floating gate (FG), and are erased using the tunneling effect (Fowler-Nordheim, FN). The efficiency of tunneling mainly depends on the interface electric field strength between the floating gate and the erase gate. Therefore, it is necessary to form a sharp angle between the floating gate and the erase gate to enhance the local electric field strength and increase the erasure efficiency.
[0004] However, in the process of combining embedded flash memory with monolithic device integration, a high temperature and high pressure process for monolithic device integration is required after the flash memory is formed. The high temperature oxidation process of monolithic device integration will cause the floating gate corners to be rounded, significantly reducing the interface electric field. Summary of the invention
[0005] The technical problem solved by the present invention is to provide a method for forming a memory structure to improve the performance of the memory structure.
[0006] In order to solve the above technical problems, the present invention provides a method for forming a memory structure, comprising: providing a substrate, the substrate comprising a plurality of storage areas and logic areas; forming two separate storage gate structures on each storage area, the storage gate structure comprising a floating gate and a control gate structure located on the surface of each floating gate; forming a modified area in the storage area between the two storage gate structures; forming a protection structure on the side wall surface of the storage gate structure; after forming the protection structure, oxidizing the surface of the logic area, the modified area and the protection structure, forming a gate oxide layer on the surface of the logic area, forming an erase gate oxide layer in the modified area, oxidizing the protection structure into a first oxidized side wall, and the oxidation rate of the oxidation treatment on the surface of the modified area is higher than the oxidation rate on the surface of the logic area.
[0007] Optionally, the protection structure comprises a multi-layer structure, comprising: a first protection layer located on the substrate surface, the sidewall surface of the storage gate structure, and the top surface of the storage gate structure, and a second protection layer located on the sidewall surface of the first protection layer.
[0008] Optionally, the material of the first protective layer includes silicon oxide; the material of the second protective layer includes silicon nitride; and the thickness range of the first protective layer is: The thickness range of the second protective layer is:
[0009] Optionally, the method for forming a protective structure includes: forming a first protective layer and an initial second protective layer located on the surface of the first protective layer on the top surface of the storage gate structure, the side wall surface of the storage gate structure and the substrate surface; etching back the initial second protective layer using the first protective layer as a stop layer, removing the initial second protective layer in a direction parallel to the substrate surface, and forming a second protective layer.
[0010] Optionally, the method for forming the protection structure includes: forming an initial protection structure on the top surface of the storage gate structure, the sidewall surface of the storage gate structure, and the substrate surface; etching back the initial protection structure until the top surface of the storage gate structure and the substrate surface are exposed to form a protection structure.
[0011] Optionally, the protection structure includes a single-layer structure located on the sidewall surface of the storage gate structure, and the material of the protection structure includes silicon nitride.
[0012] Optionally, the method further includes: forming an interface oxide layer on the surface of the substrate before forming the storage gate structure.
[0013] Optionally, before forming the modified region and after forming two separate storage gate structures, the method further includes: forming a sidewall oxide layer on the interface oxide layer, the top surface of the storage gate structure and the sidewall surface of the storage gate structure.
[0014] Optionally, the method for forming the modified area includes: forming a first mask layer on the surface of the substrate and the surface of the sidewall oxide layer, the top of the first mask layer is higher than the top of the storage gate structure and the first mask layer exposes the substrate surface between the two storage gate structures in each storage area; modifying the substrate of the storage area exposed by the first mask layer to form a modified area in the storage area between the two storage gate structures.
[0015] Optionally, the modification process is ion implantation.
[0016] Optionally, the parameters of the ion implantation process include: the energy of the ion implantation is 20keV to 70keV; the ion implantation dose is 1E15 ions / cm 2 ~1E16 ions / cm 2 .
[0017] Optionally, after forming the modified region and before forming the protection structure, the method further includes: removing the sidewall oxide layer and the second sidewall spacer of the sidewalls of the storage gate structure on both sides of the modified region.
[0018] Optionally, the method of removing the sidewall oxide layer and the second sidewall of the storage gate structure on both sides of the modified area includes: wet etching; the etching solution of the wet etching is hydrofluoric acid.
[0019] Optionally, it also includes: a control gate side wall; the control gate side wall includes: a first side wall located on the first side wall of the control gate structure and a second side wall structure located on the second side wall of the control gate structure; the second side wall structure includes a first side wall located on the surface of the second side wall of the control gate structure and a second side wall located on the surface of the first side wall; the first side wall is a side wall facing the adjacent control gate structure, and the second side wall is another side wall opposite to the first side wall.
[0020] Optionally, the floating gate includes a third sidewall and a fourth sidewall, the third sidewall is a sidewall facing the adjacent floating gate, and the fourth sidewall is another sidewall opposite to the third sidewall; the sidewall of the floating gate protrudes from the sidewall of the control gate structure.
[0021] Optionally, a method for forming a storage gate structure includes: forming a floating gate dielectric layer on the surface of the storage area; forming a floating gate material layer on the surface of the floating gate dielectric layer; forming two separate control gate structures on the floating gate material layer, the control gate structure including a control gate dielectric layer and a control gate located on the surface of the control gate dielectric layer, and having an opening between adjacent control gate structures, the opening exposing the control gate sidewalls, the control gate dielectric layer sidewalls and the floating gate material layer surface; forming control gate sidewalls on the control gate sidewalls and the control gate dielectric layer sidewall surfaces; using the control gate sidewalls as a mask, etching the floating gate material layer until the surface of the floating gate dielectric layer is exposed to form a floating gate, wherein the sidewalls of the floating gate protrude from the sidewalls of the control gate structure.
[0022] Optionally, the method for forming a control gate dielectric layer and a control gate includes: forming a control gate dielectric material layer and a control gate material layer located on the surface of the control gate dielectric material layer on the floating gate material layer; forming a second mask layer on the control gate material layer, the second mask layer exposing a portion of the surface of the control gate material layer; using the second mask layer as a mask, etching the control gate material layer and the control gate dielectric material layer until the surface of the floating gate material layer is exposed to form a control gate and a control gate dielectric layer.
[0023] Optionally, the control gate structure includes: a control gate dielectric layer and a control gate located on the control gate dielectric layer.
[0024] Optionally, the control gate dielectric layer includes: a first silicon oxide layer, a silicon nitride layer located on a surface of the first silicon oxide layer, and a second silicon oxide layer located on a surface of the silicon nitride layer.
[0025] Optionally, the oxidation treatment process includes a furnace tube high temperature treatment process; the oxidation treatment temperature is greater than 950° C.; the thickness of the gate oxide layer ranges from greater than
[0026] Compared with the prior art, the technical solution of the present invention has the following advantages:
[0027] In the method for forming a memory structure of the technical solution of the present invention, on the one hand, the protection structure is located on the side wall surface of the storage gate structure, which can protect the floating gate surface from being oxidized. When the logic area surface, the modified area and the protection structure are oxidized, the floating gate side wall will not be oxidized to cause the floating gate corner to be rounded, thereby ensuring the local electric field strength of the floating gate and the erasing efficiency of the memory; on the other hand, when the logic area surface, the modified area and the protection structure are oxidized, while a gate oxide layer is formed on the logic area surface, the protection structure simultaneously forms an erase gate oxide layer and a first oxide side wall after the oxidation treatment, thereby simplifying the process flow and reducing the process cost. BRIEF DESCRIPTION OF THE DRAWINGS
[0028] Figures 1 to 12 It is a cross-sectional structural schematic diagram of the formation process of the memory structure of an embodiment of the present invention. DETAILED DESCRIPTION
[0029] As mentioned in the background art, there are still many problems in the process of integrating embedded flash memory with monolithic devices in the prior art.
[0030] In an embodiment of a flash memory, a high temperature and high pressure process for monolithic device integration is required after the flash memory is formed. The high temperature oxidation process of the monolithic device integration will cause the floating gate corners to be rounded, significantly reducing the interface electric field and reducing the erase efficiency.
[0031] In order to solve the above technical problems, the technical solution of the present invention proposes a method for forming a memory structure, in which a protection structure is formed on the side wall surface of the storage gate structure. On the one hand, the floating gate surface can be protected to prevent the floating gate from being oxidized. When the logic area surface, the modified area and the protection structure are oxidized, the floating gate side wall will not be oxidized to cause the floating gate corner to be rounded, thereby ensuring the local electric field strength of the floating gate and the erasure efficiency of the memory; on the other hand, when the logic area surface, the modified area and the protection structure are oxidized, a gate oxide layer is formed on the logic area surface, and the protection structure simultaneously forms an erase gate oxide layer and a first oxide side wall after the oxidation treatment, thereby simplifying the process flow and reducing the process cost.
[0032] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.
[0033] Figures 1 to 12It is a cross-sectional structural schematic diagram of the formation process of the memory structure of an embodiment of the present invention.
[0034] Please refer to Figure 1 , a substrate 100 is provided, and the substrate 100 includes a plurality of storage areas I and a logic area II.
[0035] The material of the substrate 100 includes silicon, silicon germanium, silicon carbide, silicon on insulator (SOI), germanium on insulator (GOI), etc. Specifically, in the present embodiment, the material of the substrate 100 is silicon.
[0036] The substrate 100 includes a fin-type substrate structure or a planar substrate structure.
[0037] The storage area I provides a platform for a flash memory device formed subsequently, and the logic area II provides a platform for a logic device formed subsequently.
[0038] In this embodiment, the storage area I includes a lightly doped layer 101. The material of the lightly doped layer 101 includes silicon, and the doped ions include P-type ions and N-type ions; the purpose of the lightly doped layer 101 is to increase the oxidation rate.
[0039] In other embodiments, the storage region does not include a lightly doped layer.
[0040] Please refer to Figure 2 , an interface oxide layer 102 is formed on the surface of the substrate 100 .
[0041] The material of the interface oxide layer 102 includes silicon oxide.
[0042] Specifically, in the present embodiment, the process of forming the interface oxide layer 102 includes a rapid thermal treatment process, an in-situ water vapor generation process, and a furnace tube high temperature deposition process.
[0043] Specifically, in this embodiment, the thickness range of the interface oxide layer 102 is:
[0044] The function of the interface oxide layer 102 is to protect the substrate 100 and repair the damage of the shallow trench isolation layer in the logic region II caused by etching.
[0045] After the interface oxide layer 102 is formed, two separate storage gate structures 105 are formed on each storage area I. The storage gate structure 105 includes a floating gate 103 and a control gate structure 104 located on the surface of each floating gate 103. Figures 3 to 6 .
[0046] Please refer to Figure 3 , a floating gate dielectric layer (not labeled) is formed on the surface of the storage area I; and a floating gate material layer 106 is formed on the surface of the floating gate dielectric layer (not labeled).
[0047] In this embodiment, the material of the floating gate dielectric layer (not labeled) includes silicon oxide.
[0048] The process of forming the floating gate dielectric layer (not labeled) includes deposition. Specifically, in this embodiment, the deposition process is chemical vapor deposition.
[0049] The process of forming the floating gate material layer 106 includes deposition. Specifically, in this embodiment, the deposition process is chemical vapor deposition.
[0050] The thickness range of the floating gate material layer 106 is:
[0051] The floating gate material layer 106 provides a structural basis for the subsequently formed floating gate 103. Specifically, in this embodiment, the material of the floating gate material layer 106 includes polysilicon.
[0052] Please refer to Figure 4 , a control gate dielectric material layer 107 and a control gate material layer 108 located on the surface of the control gate dielectric material layer 107 are formed on the floating gate material layer 106; a second mask layer (not marked) is formed on the control gate material layer 108, and the second mask layer (not marked) exposes a portion of the surface of the control gate material layer 108.
[0053] The process of forming the control gate dielectric material layer 107 includes deposition. The deposition process is: chemical vapor deposition.
[0054] The thickness range of the control gate dielectric material layer 107 is:
[0055] Specifically, in this embodiment, the control gate dielectric material layer 107 includes a first silicon oxide material layer (unlabeled), a silicon nitride material layer (unlabeled) located on the surface of the first silicon oxide material layer (unlabeled), and a second silicon oxide material layer (unlabeled) located on the surface of the silicon nitride material layer (unlabeled).
[0056] The control gate dielectric material layer 107 provides a structural basis for the control gate dielectric layer 110 to be formed subsequently.
[0057] The process of forming the control gate material layer 108 includes deposition. Specifically, in this embodiment, the deposition process is chemical vapor deposition.
[0058] The thickness range of the control gate material layer 108 is:
[0059] Specifically, in this embodiment, the material of the control gate material layer 108 includes polysilicon.
[0060] The control gate material layer 108 provides a structural basis for the control gate 109 to be formed subsequently.
[0061] Please refer to Figure 5 , using the second mask layer (not labeled) as a mask, etching the control gate material layer 108 (such as Figure 4 as shown) and the control gate dielectric material layer 107 (as shown Figure 4 As shown), until the surface of the floating gate material layer 106 is exposed, so as to form a control gate 109 and a control gate dielectric layer 110.
[0062] The thickness range of the control gate dielectric layer 110 is:
[0063] Specifically, in this embodiment, the control gate dielectric layer 110 includes: a first silicon oxide layer (not labeled), a silicon nitride layer (not labeled) located on the surface of the first silicon oxide layer (not labeled), and a second silicon oxide layer (not labeled) located on the surface of the silicon nitride layer (not labeled).
[0064] The thickness range of the control grid 109 is:
[0065] Specifically, in this embodiment, the material of the control gate 109 includes polysilicon.
[0066] The control gate structure 104 includes a control gate dielectric layer 110 and a control gate 109 located on the control gate dielectric layer 110 .
[0067] Specifically, in this embodiment, there is an opening (not labeled) between adjacent control gate structures 104, and the opening (not labeled) exposes the sidewalls of the control gate 109, the sidewalls of the control gate dielectric layer 110, and the surface of the floating gate material layer 106. In this embodiment, the opening (not labeled) provides space for the subsequent formation of an erase gate.
[0068] Please refer to Figure 6 , forming a control gate sidewall 111 on the sidewall of the control gate 109 and the sidewall surface of the control gate dielectric layer 110; using the control gate sidewall 111 as a mask, etching the floating gate material layer 106 (such as Figure 5 As shown) until the surface of the floating gate dielectric layer (not labeled) is exposed, a floating gate 103 is formed, and the sidewalls of the floating gate 103 protrude from the sidewalls of the control gate structure 104.
[0069] The control gate spacer 111 protects the control gate structure 104 on the one hand and serves as a substrate for etching the floating gate material layer 106 (such as Figure 5 The mask layer used when forming the floating gate 103 (as shown in FIG. 1 ) limits the size of the floating gate 103 parallel to the surface of the substrate 100.
[0070] Specifically, in the present embodiment, the control gate sidewall 111 includes: a first sidewall 112 located on the first sidewall of the control gate structure 104 and a second sidewall structure 113 located on the second sidewall of the control gate structure 104; the second sidewall structure 113 includes the first sidewall 112 located on the surface of the second sidewall of the control gate structure 104 and the second sidewall 114 located on the surface of the first sidewall 112; the first sidewall is a sidewall facing the adjacent control gate structure 104, and the second sidewall is another sidewall opposite to the first sidewall.
[0071] The floating gate 103 includes a third sidewall and a fourth sidewall, wherein the third sidewall is a sidewall facing the adjacent floating gate 103, and the fourth sidewall is another sidewall opposite to the third sidewall. Specifically, in the present embodiment, the size range of the sidewall of the floating gate 103 protruding from the sidewall of the control gate structure 104 is:
[0072] Specifically, in this embodiment, the thickness range of the first sidewall 112 is: The thickness range of the second sidewall 114 is:
[0073] In this embodiment, the material of the first spacer 112 includes silicon nitride; and the material of the second spacer 114 includes silicon oxide.
[0074] In this embodiment, the method for forming the control gate spacer 111 includes: forming a floating gate material layer 106 (such as Figure 5 As shown), the side wall surface of the control gate structure 104 and the top surface of the control gate structure 104 form an initial first sidewall (not marked), and an initial second sidewall located on the surface of the initial first sidewall (not marked); a third mask layer is formed on the surface of the initial second sidewall, and the third mask layer exposes a portion of the surface of the initial second sidewall; using the third mask layer as a mask, the initial second sidewall is etched until the top surface of the control gate structure 104 is exposed, forming a first sidewall 112 located on the first sidewall of the control gate structure 104 and a second sidewall structure 113 located on the second sidewall of the control gate structure, wherein the second sidewall structure 113 includes the first sidewall 112 located on the surface of the second sidewall of the control gate structure and the second sidewall 114 located on the surface of the first sidewall 112.
[0075] In other embodiments, the method for forming a control gate sidewall may further include: forming an initial first sidewall on the floating gate material layer, the sidewall surface of the control gate structure, and the top surface of the control gate structure; forming a third mask layer on the surface of the initial first sidewall, the third mask layer exposing a portion of the surface of the initial first sidewall; using the third mask layer as a mask, etching the initial first sidewall until the top surface of the control gate structure is exposed, thereby forming a control gate sidewall located on the sidewall surface of the control gate structure.
[0076] In other embodiments, the material of the initial first spacer includes silicon nitride.
[0077] The process of etching the floating gate material layer 106 includes dry etching.
[0078] The material of the floating gate 103 includes polysilicon.
[0079] Most of the charges of the flash memory are stored in the floating gate and erased by the tunneling effect. The efficiency of the tunneling mainly depends on the interface electric field strength between the floating gate and the erase gate. Usually, a sharp angle is formed between the floating gate and the erase gate to enhance the local electric field strength and increase the erasure efficiency. In this embodiment, the side wall of the floating gate 103 protrudes from the side wall of the control gate structure 104, so the floating gate 103 has a sharp angle, which improves the local electric field strength of the floating gate 103 and ensures the erasure efficiency of the memory.
[0080] Please refer to Figure 7 After forming two separate storage gate structures 105 , a spacer oxide layer 115 is formed on the interface oxide layer 102 , the top surface of the storage gate structure 105 , and the sidewall surface of the storage gate structure 105 .
[0081] The material of the spacer oxide layer 115 includes silicon oxide.
[0082] The thickness range of the sidewall oxide layer 115 is:
[0083] The process of forming the sidewall oxide layer 115 includes a high temperature oxidation process. The function of the sidewall oxide layer 115 is to protect the sidewall of the floating gate 103 in the subsequent process of forming the modified region 116 and prevent the sharp corners of the floating gate 103 from being rounded.
[0084] Please refer to Figure 8 , a modified region 116 is formed in the storage region I between the two storage gate structures 105.
[0085] The method for forming the modified area 116 includes: forming a first mask layer (not marked) on the surface of the substrate 100 and the surface of the sidewall oxide layer 115, the top of the first mask layer (not marked) is higher than the top of the storage gate structure 105 and the first mask layer (not marked) exposes the substrate surface between the two storage gate structures 105 in each storage area I; modifying the substrate of the storage area I exposed by the first mask layer (not marked) to form a modified area 116 in the storage area I located between the two storage gate structures 105.
[0086] The material of the modified area 116 is amorphous.
[0087] Specifically, in this embodiment, the depth range of the modified zone 116 is:
[0088] The modification process is ion implantation. By implanting ions into the modified area 116 , the valence bonds between silicon atoms in the substrate 100 are broken, so that the oxidation rate of the modified area 116 is faster than that of other areas of the substrate 100 , providing a structural basis for the subsequent formation of a thicker erase gate oxide layer 122 .
[0089] Specifically, in this embodiment, the parameters of the ion implantation process include: the energy of the ion implantation is 20keV to 70keV; the ion implantation dose is 1E15 ions / cm 2 ~1E16 ions / cm 2 .
[0090] Specifically, in this embodiment, the implanted ion species include lead or arsenic.
[0091] Please refer to Fig. 9 After forming the modified region 116, the sidewall oxide layer 115 (eg, Figure 8 as shown) and the second side wall 114 (as shown Figure 8 shown).
[0092] Remove the sidewall oxide layer 115 (such as Figure 8 as shown) and the second side wall 114 (as shown Figure 8 The method as shown in the figure includes: wet etching; the etching solution of the wet etching is hydrofluoric acid.
[0093] Remove the sidewall oxide layer 115 (such as Figure 8 as shown) and the second side wall 114 (as shown Figure 8 The role of the first oxidized spacer 123 as shown in the figure is to provide a structural basis for the subsequent formation of a first oxidized spacer 123 with uniform and controllable thickness.
[0094] After removing the sidewall oxide layer 115 (such as Figure 8 as shown) and the second side wall 114 (as shown Figure 8 After that, a protection structure 117 is formed on the sidewall surface of the storage gate structure 105. For details, please refer to Figure 10 to Figure 11 .
[0095] In the present embodiment, the protection structure 117 includes a multi-layer structure, which includes: a first protection layer 118 located on the surface of the substrate 100, the sidewall surface of the storage gate structure 105, and the top surface of the storage gate structure 105, and a second protection layer 120 located on the sidewall surface of the first protection layer 118. The method for forming the protection structure 117 includes: forming the first protection layer 118 and the initial second protection layer 119 located on the surface of the first protection layer 118 on the top surface of the storage gate structure 105, the sidewall surface of the storage gate structure 105, and the surface of the substrate 100; etching back the initial second protection layer 119 with the first protection layer 118 as a stop layer, removing the initial second protection layer 119 parallel to the surface of the substrate 100, and forming the second protection layer 120.
[0096] Please refer to Fig.10 A first protection layer 118 and an initial second protection layer 119 located on the surface of the first protection layer 118 are formed on the top surface of the storage gate structure 105 , the sidewall surface of the storage gate structure 105 , and the surface of the substrate 100 .
[0097] The material of the first protection layer 118 includes silicon oxide; the material of the initial second protection layer 119 includes silicon nitride.
[0098] The first protective layer 118 is a component of the first oxidized spacer 123 formed subsequently, and its thickness is adjusted according to the needs of the first oxidized spacer 123. Specifically, in this embodiment, the thickness range of the first protective layer 118 is:
[0099] The initial second protective layer 119 provides a structural basis for the subsequent formation of the second protective layer 120. Specifically, in this embodiment, the thickness of the initial second protective layer 119 is in the range of
[0100] Please refer to Fig.11 , using the first protection layer 118 as a stop layer, the initial second protection layer 119 is etched back to remove the initial second protection layer 119 parallel to the surface direction of the substrate 100 , thereby forming a second protection layer 120 .
[0101] The material of the second protection layer 120 includes silicon nitride.
[0102] The thickness of the second protective layer 120 is in the range of The thickness of the second protective layer 120 is In the subsequent oxidation process to form the gate oxide layer 121 , the protection structure 117 can be completely oxidized to form the first oxidized spacer 123 .
[0103] In this embodiment, the protection structure 117 includes a first protection layer 118 and a second protection layer 120 located on the sidewall surface of the first protection layer 118. The protection structure 117 covers the sidewall surface of the storage gate structure 105, and can protect the surface of the floating gate 103 to prevent the sidewall of the floating gate 103 from being oxidized. When the surface of the logic region II, the modified region 116 and the protection structure 117 are subsequently oxidized, the floating gate 103 will not be oxidized to cause the sharp corners of the floating gate 103 to be rounded, thereby ensuring the local electric field strength of the floating gate 103 and ensuring the erasing efficiency of the memory.
[0104] In other embodiments, the protection structure includes a single-layer structure located on the sidewall surface of the storage gate structure, and the material of the protection structure includes silicon nitride.
[0105] In other embodiments, the method for forming the protection structure includes: forming an initial protection structure on the top surface of the storage gate structure, the sidewall surface of the storage gate structure, and the substrate surface; etching back the initial protection structure until the top surface of the storage gate structure and the substrate surface are exposed to form a protection structure.
[0106] Please refer to Fig.12 , in forming the protection structure 117 (such as Fig.11 After that, the surface of the logic area II and the modified area 116 (as shown in Fig.11 As shown) and protective structure 117 (as Fig.11 As shown in FIG. 1 , an oxidation treatment is performed to form a gate oxide layer 121 on the surface of the logic region II, so that the modified region 116 forms an erased gate oxide layer 122, and the protection structure 117 (as shown in FIG. 1 ) is formed. Fig.11 As shown) is oxidized into the first oxidized spacer 123, and the oxidation treatment has an effect on the modified area 116 (as shown) Fig.11 The oxidation rate of the surface of (as shown) is higher than the oxidation rate of the surface of logic region II.
[0107] In forming the protection structure 117 (such as Fig.11 As shown), before the oxidation treatment, the method further includes: on the protective structure 117 (as shown Fig.11 A fourth mask layer (not labeled) is formed on the surface of the logic region II; the fourth mask layer (not labeled) is used as a mask to etch the protective structure 117 (as shown in FIG. Fig.11 ), remove the protection structure 117 located on the surface of the logic region II. The etching method includes wet etching. Etching the protection structure 117 (as shown in FIG. Fig.11 The function of the gate oxide layer 121 is to remove the silicon oxide on the surface of the logic region II, thereby providing a structural basis for the subsequent formation of a gate oxide layer 121 with controllable thickness.
[0108] Specifically, in this embodiment, the oxidation treatment process includes a furnace tube high temperature treatment process, and the temperature of the oxidation treatment is greater than 950° C. Specifically, in this embodiment, the high temperature treatment process is an in-situ water vapor generation annealing process.
[0109] During the oxidation process, a gate oxide layer 121 is formed on the surface of the logic region II, and the protection structure 117 (such as Fig.11 ) and modified zone 116 (as shown Fig.11 As shown), an erase gate oxide layer 122 and a first oxide sidewall 123 are formed, which simplifies the process flow and reduces the process cost.
[0110] The erase gate oxide layer 122 provides a structural basis for the subsequent formation of the erase gate. There is a sharp angle between the erase gate oxide layer 122 and the floating gate 103, so that there is a sharp angle between the erase gate subsequently formed on the erase gate oxide layer 122 and the floating gate 103, which enhances the local electric field strength of the floating gate 103, improves the tunneling efficiency, and increases the erase efficiency.
[0111] The gate oxide layer 121 on the surface of the logic region II provides a structural basis for the subsequent formation of logic devices. The thickness range of the gate oxide layer 121 on the surface of the logic region II is: greater than
[0112] The first oxidized spacer 123 is directly formed by oxidizing the gate oxide layer 121 and the protective structure 117 at the same time, thereby eliminating the step of removing the protective structure 117 and simplifying the process flow.
[0113] After forming the gate oxide layer 121, the erase gate oxide layer 122 and the first oxidized spacer 123, the method further includes: forming an erase gate structure on the erase gate oxide layer 122; the erase gate structure includes: an erase gate dielectric layer and an erase gate located on the erase gate dielectric layer.
[0114] The erase gate dielectric layer includes a single-layer structure or a multi-layer structure; the material of the erase gate dielectric layer includes: one or more of silicon oxide or silicon nitride.
[0115] The material of the erase gate includes polysilicon.
[0116] After the erase gate structure is formed, the method further includes: forming a word line gate on both sides of the erase gate structure and the control gate structure 104 .
[0117] In this embodiment, the device structure formed on the storage area I is suitable for a Nor Flash device.
[0118] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.
Claims
1. A method for forming a memory structure, characterized in that: include: Providing a substrate, the substrate comprising a plurality of storage areas and a logic area; forming two separate storage gate structures on each of the storage areas, wherein the storage gate structures include a floating gate and a control gate structure located on the surface of each of the floating gates; forming a modified region in the storage region between the two storage gate structures; forming a protection structure on a sidewall surface of the storage gate structure; After forming the protection structure, the surface of the logic area, the modified area and the protection structure are oxidized to form a gate oxide layer on the surface of the logic area, an erase gate oxide layer is formed in the modified area, and the protection structure is oxidized into a first oxidized side wall. The oxidation rate of the surface of the modified area is higher than the oxidation rate of the surface of the logic area.
2. The method for forming a memory structure according to claim 1, wherein: The protection structure comprises a multi-layer structure, which comprises: a first protection layer located on a substrate surface, a sidewall surface of a storage gate structure, and a top surface of the storage gate structure, and a second protection layer located on a sidewall surface of the first protection layer.
3. The method for forming a memory structure according to claim 2, wherein: The material of the first protective layer includes silicon oxide; the material of the second protective layer includes silicon nitride; the thickness range of the first protective layer is: The thickness range of the second protective layer is:
4. The method for forming a memory structure according to claim 2, wherein: The method for forming the protection structure includes: forming a first protection layer and an initial second protection layer located on the surface of the first protection layer on the top surface of the storage gate structure, the side wall surface of the storage gate structure and the substrate surface; etching back the initial second protection layer using the first protection layer as a stop layer, removing the initial second protection layer parallel to the substrate surface direction, and forming a second protection layer.
5. The method for forming a memory structure according to claim 2, wherein: The method for forming the protection structure includes: forming an initial protection structure on the top surface of the storage gate structure, the sidewall surface of the storage gate structure, and the substrate surface; etching back the initial protection structure until the top surface of the storage gate structure and the substrate surface are exposed to form a protection structure.
6. The method for forming a memory structure according to claim 1, wherein: The protection structure comprises a single-layer structure located on the side wall surface of the storage gate structure, and the material of the protection structure comprises silicon nitride.
7. The method for forming a memory structure according to claim 1, wherein: Also includes: Before forming the storage gate structure, an interface oxide layer is formed on the surface of the substrate.
8. The method for forming a memory structure according to claim 7, wherein: Before forming the modified area and after forming two separate storage gate structures, the method further includes: forming a sidewall oxide layer on the interface oxide layer, the top surface of the storage gate structure and the sidewall surface of the storage gate structure.
9. The method for forming a memory structure according to claim 8, wherein: The method for forming the modified area includes: forming a first mask layer on the surface of the substrate and the surface of the sidewall oxide layer, wherein the top of the first mask layer is higher than the top of the storage gate structure and the first mask layer exposes the substrate surface between the two storage gate structures in each storage area; modifying the substrate of the storage area exposed by the first mask layer to form a modified area in the storage area between the two storage gate structures.
10. The method for forming a memory structure according to claim 9, wherein: The modification process is ion implantation.
11. The method for forming a memory structure according to claim 10, wherein: The parameters of the ion implantation process include: the energy of the ion implantation is 20keV to 70keV; the ion implantation dose is 1E15ions / cm 2 ~1E16 ions / cm 2 .
12. The method for forming a memory structure according to claim 8, wherein: After forming the modified area and before forming the protection structure, the method further includes: removing the sidewall oxide layer and the second sidewall of the storage gate structure sidewall on both sides of the modified area.
13. The method for forming a memory structure according to claim 12, wherein: The method for removing the sidewall oxide layer and the second sidewall of the storage gate structure sidewalls on both sides of the modified area comprises: wet etching; The wet etching solution is hydrofluoric acid.
14. The method for forming a memory structure according to claim 1, wherein: Also includes: Control grid side wall; The control gate spacer comprises: a first spacer located on a first side wall of the control gate structure and a second spacer structure located on a second side wall of the control gate structure; The second sidewall structure includes a first sidewall located on the second sidewall surface of the control gate structure and a second sidewall located on the first sidewall surface; the first sidewall is a sidewall facing the adjacent control gate structure, and the second sidewall is another sidewall opposite to the first sidewall.
15. The method for forming a memory structure according to claim 14, wherein: The floating gate includes a third sidewall and a fourth sidewall, the third sidewall is a sidewall facing the adjacent floating gate, and the fourth sidewall is another sidewall opposite to the third sidewall; the sidewall of the floating gate protrudes from the sidewall of the control gate structure.
16. The method for forming a memory structure according to claim 15, wherein: The method for forming the storage gate structure comprises: forming a floating gate dielectric layer on the surface of the storage area; forming a floating gate material layer on the surface of the floating gate dielectric layer; forming two separate control gate structures on the floating gate material layer, the control gate structure comprising a control gate dielectric layer and a control gate located on the surface of the control gate dielectric layer, and an opening is provided between adjacent control gate structures, the opening exposing the control gate sidewalls, the control gate dielectric layer sidewalls and the floating gate material layer surface; forming a control gate sidewall on the control gate sidewalls and the control gate dielectric layer sidewall surfaces; using the control gate sidewall as a mask, etching the floating gate material layer until the floating gate dielectric layer surface is exposed to form a floating gate, wherein the sidewalls of the floating gate protrude from the sidewalls of the control gate structure.
17. The method for forming a memory structure according to claim 16, wherein: The method for forming the control gate dielectric layer and the control gate includes: forming a control gate dielectric material layer and a control gate material layer located on the surface of the control gate dielectric material layer on the floating gate material layer; forming a second mask layer on the control gate material layer, wherein the second mask layer exposes a portion of the surface of the control gate material layer; using the second mask layer as a mask, etching the control gate material layer and the control gate dielectric material layer until the surface of the floating gate material layer is exposed to form a control gate and a control gate dielectric layer.
18. The method for forming a memory structure according to claim 1, wherein: The control gate structure includes: a control gate dielectric layer and a control gate located on the control gate dielectric layer.
19. The method for forming a memory structure according to claim 18, wherein: The control gate dielectric layer includes: a first silicon oxide layer, a silicon nitride layer located on the surface of the first silicon oxide layer, and a second silicon oxide layer located on the surface of the silicon nitride layer.
20. The method for forming a memory structure according to claim 1, wherein: The oxidation process includes a furnace tube high temperature treatment process; the oxidation temperature is greater than 950°C; the thickness of the gate oxide layer is greater than