Display panel and display device

Abstract

The invention provides a display panel and a display device. The display panel comprises a shielding layer; the pixel driving circuit layer is located on the shielding layer and comprises a plurality of pixel driving circuits which are at least partially overlapped with the shielding layer; and the power line is electrically connected with the shielding layer through a plurality of through holes formed in the pixel driving circuit layer. Wherein the converging wires between the adjacent through holes are arranged according to the shortest distance between the adjacent through holes.

Description

[0001] This application is a divisional application with a filing date of March 11, 2022, application number 202210237733.1, and invention name “Display panel and display device”. Technical Field

[0002] The present invention relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0003] OLED (Organic Light-Emitting Diode) screens are currently widely used, with the advantages of being lightweight and having a high color gamut. However, due to the use of an organic flexible substrate, OLED screens are prone to screen afterimages, initial voltage drop, and poor lifespan due to the influence of the interface between the substrate and the inorganic layer.

[0004] In order to reduce this effect, more and more OLED screens use bottom shielding metal to shield the pixel driving circuit at the interface between the substrate and the inorganic layer. However, in order to overlap with the power line, the edge of the bottom shielding metal is jagged, which is prone to ESD (Electro-Static Discharge) damage at the tip of the jagged edge, thus affecting the display effect. Summary of the invention

[0005] The embodiments of the present invention provide a display panel and a display device, which can improve the problem of ESD damage to the bottom shielding metal.

[0006] An embodiment of the present invention provides a display panel, comprising a display area and a non-display area arranged on at least one side of the display area, the display panel comprising: a substrate; a shielding layer, located on the substrate, comprising a plurality of shielding blocks and a convergence line electrically connected to the plurality of shielding blocks, the convergence line being located on at least one side of the plurality of shielding blocks; a pixel driving circuit layer, located on the shielding layer, comprising a plurality of pixel driving circuits located in the display area, each of the pixel driving circuits at least partially overlapping with the corresponding shielding block; and a first conductive layer, arranged on a side of the shielding layer away from the substrate, the first conductive layer comprising: a plurality of power lines, the plurality of power lines being electrically connected to the convergence line through a plurality of through holes; wherein the convergence line between adjacent through holes is arranged according to the shortest distance between adjacent through holes.

[0007] In some embodiments, the convergent traces between adjacent through holes are arranged in a straight line.

[0008] In some embodiments, the converging lines are arranged in a straight line, and the plurality of through holes overlapping with the converging lines are arranged in a straight line.

[0009] In some embodiments, the converging routing includes a first converging routing, the first converging routing includes a plurality of first connecting segments and a plurality of second connecting segments, wherein each of the second connecting segments is connected between the middle portions of two adjacent first connecting segments, the width of the first connecting segment is greater than the width of the second connecting segment, and the plurality of power lines are electrically connected to the plurality of first connecting segments through the plurality of through holes.

[0010] In some embodiments, the pixel driving circuit layer includes a plurality of pixel driving circuits arranged in an array along a first direction and a second direction, and each of the first connecting segments is electrically connected to a shielding block corresponding to a column of the pixel driving circuits arranged along the first direction.

[0011] In some embodiments, the outer periphery of the first connecting segment is in an arc shape, the second connecting segment is in a straight line shape, and the maximum width of the first connecting segment is greater than the width of the second connecting segment.

[0012] In some embodiments, the non-display area includes: a first non-display area and a second non-display area arranged on both sides of the display area, the first non-display area includes a bending sub-area, and the display panel is bent in the bending sub-area;

[0013] The convergent wiring includes a first convergent wiring arranged in the first non-display area, and the plurality of power lines are electrically connected to the first convergent wiring through at least a plurality of the through holes.

[0014] In some embodiments, the convergent wiring includes a second convergent wiring disposed in the second non-display area, and the plurality of power lines are further electrically connected to the second convergent wiring through a plurality of the through holes.

[0015] In some embodiments, the pixel driving circuit layer includes: a semiconductor layer, which is arranged on a side of the blocking layer away from the substrate; a first insulating layer, which is arranged on a side of the semiconductor layer away from the substrate; a first gate metal layer, which is arranged on a side of the first insulating layer away from the substrate; a second insulating layer, which is arranged on a side of the first gate metal layer away from the substrate; a second gate metal layer, which is arranged on a side of the second insulating layer away from the substrate; a third insulating layer, which is arranged on a side of the second gate metal layer away from the substrate; and the first conductive layer, which is arranged on a side of the third insulating layer away from the substrate, wherein the plurality of power lines of the first conductive layer are electrically connected to the convergence routing through the plurality of through holes, and the through holes pass through the first insulating layer, the second insulating layer, and the third insulating layer.

[0016] In some embodiments, the pixel driving circuit layer also includes: a fourth insulating layer, arranged between the second gate metal layer and the third insulating layer; a second conductive layer, arranged between the fourth insulating layer and the third insulating layer; the through hole includes a first through hole and a second through hole, the first through hole passes through the first insulating layer, the second insulating layer, and the fourth insulating layer, the second through hole passes through the third insulating layer, the first through hole is connected to the second through hole and the diameter of the second through hole is larger than the diameter of the first through hole.

[0017] An embodiment of the present invention further provides a display device, comprising the display panel as described above.

[0018] In the display panel and display device provided by the embodiments of the present invention, the multiple blocking blocks of the blocking layer block the multiple thin film transistors of the pixel driving circuit layer, and the power line and the converging wiring of the blocking layer are electrically connected to each other through a through hole, wherein the converging wiring between adjacent through holes is arranged according to the shortest distance between adjacent through holes, so that the path of the expected current flowing through the converging wiring is located within the boundary of the converging wiring and is conducted along the shortest distance between adjacent through holes, thereby reducing the accumulation of charge at the boundary of the blocking layer and reducing the phenomenon of ESD damage to the blocking layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0020] Figure 1 is a schematic cross-sectional view of a display panel provided by an embodiment of the present invention;

[0021] Figure 2 is a schematic top view of a display panel provided by an embodiment of the present invention;

[0022] Figure 3 yes Figure 2 An enlarged schematic diagram of part A in FIG.

[0023] Figure 4 is a schematic top view of a display panel provided by an embodiment of the present invention;

[0024] Figure 5 yes Figure 4 Schematic diagram of the enlarged portion B. DETAILED DESCRIPTION

[0025] The technical solutions in the embodiments of the present invention will be described clearly and completely below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments in the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention. In addition, it should be understood that the specific implementation methods described herein are only used to illustrate and explain the present invention, and are not used to limit the present invention. In the present invention, unless otherwise specified, the directional words used, such as "upper" and "lower", generally refer to the upper and lower parts of the device in actual use or working state, specifically the drawing direction in the drawings; while "inside" and "outside" refer to the outline of the device.

[0026] like Figure 1 and Figure 2 As shown, an embodiment of the present invention provides a display panel 1000, and the display panel 1000 may be an OLED display panel, a liquid crystal display panel, a micro-LED display panel, or a mini-LED display panel. Exemplarily, the display panel 1000 is an OLED display panel.

[0027] The display panel 1000 includes a display area DA and a non-display area NDA. The display area DA may be an area for setting a sub-pixel 9 for displaying an image. The non-display area NDA may be an area for providing a driving unit such as a gate driving circuit for providing a driving signal to a pixel driving circuit 40 set to the sub-pixel 9, and some areas connected to the driving unit. No sub-pixel 9 is set in the non-display area NDA. The non-display area NDA may be set on at least one side of the display area DA. The non-display area NDA may at least partially surround the display area DA. The non-display area NDA includes a first non-display area and a second non-display area set on both sides of the display area DA, and the display panel is bent in a bending sub-area BA of the first non-display area.

[0028] The display panel 1000 includes a substrate 1, a shielding layer 2 located on the substrate 1, a bottom insulating layer 30 located on the shielding layer 2, a buffer layer 31 located on the bottom insulating layer 30, a pixel driving circuit layer 4 located on the buffer layer 31, a pixel definition layer 5 and a light emitting device layer 6 located on the pixel driving circuit layer 4, and a power supply line 7. For ease of description, a plurality of the sub-pixels 9 may include the light emitting device layer 6.

[0029] See also Figure 1 The substrate 1 may include a single layer of insulating material such as glass, quartz and polymer resin, or a multi-layer insulating material such as a double layer of polymer resin. The substrate 1 may be a rigid substrate 1 or a flexible substrate 1. The substrate 1 is used to carry a film layer disposed thereon.

[0030] The bottom insulating layer 30 and the buffer layer 31 may include a single layer of insulating films such as silicon nitride (SiNx) and silicon oxide (SiOx) or a multilayer film of silicon nitride (SiNx) and silicon oxide (SiOx) stacked together. The buffer layer 31 prevents the penetration of unnecessary components such as impurities or moisture.

[0031] Please also read Figure 1 and Figure 2 The shielding layer 2 may include a single layer or multiple layers of metal materials such as Mo, Ti, Ti / Al / Ti, or semiconductor material Si, or a transparent conductive material such as ITO (Indium Tin Oxide). The shielding layer 2 is located between the bottom insulating layer 30 and the substrate 1, and is disposed under the pixel driving circuit layer 4 to shield the multiple pixel driving circuits 40 of the pixel driving circuit layer 4. The shielding layer 2 includes a convergence line 20, a shielding portion 21 and a common connection portion 22 that are interconnected, wherein the convergence line 20 is located in the non-display area NDA and close to the display area DA, and the shielding portion 21 is located in the display area DA.

[0032] The converging wiring 20 includes a first converging wiring 201 and a second converging wiring 202 relative to each other; wherein the first converging wiring 201 is located in the first non-display area, and the second converging wiring 202 is located in the second non-display area, and the first converging wiring 201 and the second converging wiring 202 extend along a first direction, and the first direction is the extension direction of the scanning line of the pixel driving circuit layer 4 (the direction from left to right in the figure). The first converging wiring 201 and the second converging wiring 202 each include a plurality of first connecting segments 203 and a plurality of second connecting segments 204, wherein the outer periphery of the first connecting segment 203 is in an arc shape, and illustratively, the outer periphery of the first connecting segment 203 can be roughly elliptical or circular, and the second connecting segment 204 is roughly linear. Each of the second connecting segments 204 is connected between the middle parts of two adjacent first connecting segments 203, and the maximum width of the first connecting segment 203 is greater than the width of the second connecting segment 204.

[0033] The shielding portion 21 is used to shield the plurality of thin film transistors 401 of the plurality of pixel driving circuits 40 arranged in an array along the first direction and the second direction. The plurality of thin film transistors 401 include a plurality of driving thin film transistors, and the shielding portion 21 includes a plurality of shielding blocks 211 for shielding the semiconductor patterns of the plurality of driving thin film transistors. The plurality of shielding blocks 211 are arranged in an array, and each column of the shielding blocks 211 shields the semiconductor patterns of the driving thin film transistors of the plurality of pixel driving circuits 40 driving a corresponding column of the sub-pixels 9, and is connected to the corresponding first connecting section 203.

[0034] The common connection portion 22 includes a plurality of common connection segments 221, wherein a first converging routing portion of the plurality of common connection segments 221 is directly connected between the plurality of outermost blocking blocks 211 in the row direction and the first connection segment 203, and a second portion of the plurality of common connection segments 221 is electrically connected between the plurality of blocking blocks 211.

[0035] Please continue reading Figure 1 The pixel driving circuit layer 4 includes a semiconductor layer 41, a first insulating layer 42 located on the semiconductor layer 41, a first gate metal layer 43 located on the first insulating layer 42, a second insulating layer 44 located on the first gate metal layer 43, a second gate metal layer 45 located on the second insulating layer 44, an interlayer insulating layer 46 (i.e., a fourth insulating layer) located on the second gate metal layer 45, a third metal layer 47 (i.e., a second conductive metal layer) located on the interlayer insulating layer 46, a first flat layer 481 (i.e., a third insulating layer) located on the third metal layer 47, a fourth metal layer 49 (i.e., a first conductive layer) located on the first flat layer 481, and a second flat layer 482 located on the fourth metal layer 49. The semiconductor layer 41, the first insulating layer 42, the first gate metal layer 43, the interlayer insulating layer 46, and the third metal layer 47 may form a plurality of thin film transistors 401 together, and the first gate metal layer 43, the second insulating layer 44, and the second gate metal layer 45 may form a plurality of capacitors 402 together. The plurality of pixel driving circuits 40 may include a plurality of capacitors 402 and a plurality of thin film transistors 401 to drive the sub-pixels 9 to emit light.

[0036] The semiconductor layer 41 may include polycrystalline silicon or an oxide semiconductor. At this time, the oxide semiconductor may include any one of an oxide based on titanium (Ti), hafnium (Hf), zirconium (Zr), aluminum (Al), tantalum (Ta), germanium (Ge), zinc (Zn), gallium (Ga), tin (Sn) or indium (In) or a composite oxide thereof. The semiconductor layer 41 may include the semiconductor pattern of the thin film transistor 401. The semiconductor pattern may include: a channel region, overlapping with the gate in the thickness direction; a first source / drain region and a second source / drain region, respectively located on one side and the other side of the channel region. The first source / drain region and the second source / drain region are conductive regions, which may have higher conductivity and lower resistance than the channel region.

[0037] The first insulating layer 42 and the second insulating layer 44 may be a single layer film including silicon oxide (SiOx) and silicon nitride (SiNx) or a multilayer film in which these are stacked.

[0038] The first gate metal layer 43 may include a gate of the thin film transistor 401 and a plurality of the scanning lines, and the gate may be formed of a low resistance material. The second gate metal layer 45 may include an upper plate of the capacitor 402, and the gate may serve as a lower plate of the capacitor 402. The materials of the first gate metal layer 43 and the second gate metal layer 45 may be the same or different. Exemplarily, the first gate metal layer 43 and the second gate metal layer 45 may include one or more metals selected from molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), tungsten (W), and copper (Cu), but are not limited thereto.

[0039] The interlayer insulating layer 46 may include silicon compounds, metal oxides, etc. For example, the interlayer insulating layer 46 may include silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, tantalum oxide, hafnium oxide, zirconium oxide, titanium oxide, etc. These substances may be used alone or in combination with each other.

[0040] The third metal layer 47 may include a source and a drain of the thin film transistor 401, and a plurality of the data lines. The materials of the third metal layer 47 and the fourth metal layer 49 may be the same. Exemplarily, the third metal layer 47 and the fourth metal layer 49 may include one or more metals selected from molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), tungsten (W), and copper (Cu). The third metal layer 47 may be a single-layer film or a multi-layer film. For example, the third metal layer 47 may be formed into a stacked structure of Ti / Al / Ti, Mo / Al / Mo, Mo / AlGe / Mo, Ti / Cu, etc.

[0041] The materials of the first planar layer 481 and the second planar layer 482 may be the same or different. For example, the first planar layer 481 and the second planar layer 482 may include inorganic insulating materials or organic insulating materials such as polyacrylate resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene ether resin, polyphenylene sulfide resin or benzocyclobutene. The first planar layer 481 may also include a photosensitive material, but is not limited thereto.

[0042] Please also read Figures 1 to 3 , the power line 7 is arranged in the fourth metal layer 49, the first power line 7 can be a power line with a fixed potential located in the non-display area NDA, the power line 7 includes a plurality of signal lines 71 arranged in the display area DA and electrically connected to the pixel driving circuit 40, and a peripheral line 72 arranged in the non-display area NDA and electrically connected to a preset voltage source (such as a power chip), the peripheral line 72 is electrically connected to the plurality of signal lines 71 to reduce the signal difference on the plurality of signal lines 71. The plurality of signal lines 71 extend along the second direction, which is the extension direction of the data line of the pixel driving circuit layer 4 (the direction from top to bottom in the figure). The peripheral line 72 extends along the first direction, including a first connecting portion 721 and a second connecting portion 722 relative to each other, the first connecting portion 721 is close to the bending sub-area BA, and the second connecting portion 722 is located in the second non-display area.

[0043] Exemplarily, the power line 7 is at least one of a high voltage power line and a reset signal line. The third metal layer 47 and the fourth metal layer 49 may form the high voltage power line, the low voltage power line and the reset signal line. The driving thin film transistor among the plurality of thin film transistors 401 may be connected in series with the light emitting layer of the sub-pixel 9 in the circuit loop formed by the high voltage power line and the low voltage power line to drive the light emitting layer 61 of the sub-pixel 9 to emit light. The reset signal line may be used to electrically connect to at least one of the capacitor 402, the first electrode of the sub-pixel 9 and the driving thin film transistor to reset it.

[0044] The power line 7 is electrically connected to the plurality of first connection segments 203 of the convergence line 20 through the through hole 90, so as to be electrically connected to the shielding layer 2. The convergence lines 20 between adjacent through holes 90 are arranged according to the shortest distance between adjacent through holes 90. Since the shortest distance between adjacent through holes 90, i.e., the virtual line segment 107, can represent the expected current path between adjacent through holes 90, the expected current path which is substantially linear can be located within the boundary of the convergence line 20. The through hole 90 passes through the first insulating layer 42, the second insulating layer 44, and the first flat layer 481. The through hole 90 includes a plurality of first through holes 91 and a plurality of second through holes 92. The first through hole 91 passes through the first insulating layer 42, the second insulating layer 44, and the interlayer insulating layer 46, and the second through hole 92 passes through the first flat layer 481. The first through hole 91 is connected to the second through hole 92, and the diameter of the first through hole 91 is smaller than the diameter of the second through hole 92.

[0045] Please continue to refer to FIG. 1 , the pixel definition layer 5 may include resins such as polyacrylates or polyimides and inorganic substances such as silicon dioxide. The pixel definition layer 5 is provided with a plurality of openings to expose the first electrode 60 of the light emitting device layer 6 .

[0046] The light emitting device layer 6 may include a first electrode 60 , a light emitting layer 61 and a second electrode 62 .

[0047] The first electrode 60 may be an anode. The anode may have a laminated film structure of a material layer with a higher work function such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3: InduimOxide) and a reflective material layer such as silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca) or a mixture thereof, but is not limited thereto. The layer with a higher work function may be arranged in an upper layer and close to the light emitting layer 61EL compared to the reflective material layer. The anode may have a multilayer structure of ITO / Mg, ITO / MgF2, ITO / Ag, ITO / Ag / ITO, but is not limited thereto.

[0048] The light emitting layer 61 may include an organic material layer. The organic material layer of the light emitting layer 61 may include an organic light emitting layer, and may further include a hole injection / transport layer and / or an electron injection / transport layer.

[0049] The second electrode 62 may be a cathode. The cathode may include a material layer with a small work function such as Li, Ca, LiF / Ca, LiF / Al, Al, Mg, Ag, Pt, Pd, Ni, Au, Nd, Ir, Cr, BaF2, Ba or a compound or mixture thereof (e.g., a mixture of Ag and Mg, etc.). The cathode may also include a transparent metal oxide layer disposed on the material layer with a small work function.

[0050] In the display panel 1000 of the present embodiment, the multiple blocking blocks 211 of the blocking layer 2 block the multiple thin film transistors 401 of the pixel driving circuit layer 4, and the power line 7 and the converging wiring 20 of the blocking layer 2 are electrically connected to each other via a through hole 90 provided in the pixel driving circuit layer 4, wherein the converging wiring 20 between adjacent through holes 90 is provided according to the shortest distance between adjacent through holes 90, so that the expected current path flowing through the converging wiring 20 is located within the boundary of the converging wiring and is conducted along the shortest distance between adjacent through holes 90, thereby reducing the accumulation of charge at the boundary of the blocking layer 2 and reducing the phenomenon of ESD damage to the blocking layer 2.

[0051] In other embodiments, see Figure 4 and Figure 5The first convergent wiring 201 and the second convergent wiring 202 are in a straight line shape, and the plurality of through holes 90 overlapping with the first convergent wiring 201 and the second convergent wiring 202 are arranged in a straight line. Based on the same or similar principle, the ESD damage occurring at adjacent connection positions can be reduced.

[0052] In other embodiments, the shielding layer 2 may be located between the buffer layer 31 and the semiconductor layer 41 , or may be located under the substrate 1 , so as to be located under the pixel driving circuit layer 4 for shielding.

[0053] In other embodiments, the power line 7 may also be located in other layers of the pixel driving circuit layer 4, or may be located below the pixel driving circuit layer 4, and is not limited to being a high voltage power line or a reset signal line.

[0054] An embodiment of the present invention further provides a display device, comprising any of the above-mentioned display panels 1000. The display device, as a device for displaying video or still images, can be not only a fixed terminal such as a television, a desktop computer, a monitor, and a billboard, but also a mobile terminal such as a mobile phone, a tablet computer, a mobile communication terminal, an electronic notepad, an electronic book, a multimedia player, a navigator, and a notebook computer, and can also be a wearable electronic device such as a smart watch, smart glasses, a virtual reality device, and an augmented reality device.

[0055] The embodiments of the present invention are described in detail above. Specific examples are used herein to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. At the same time, for those skilled in the art, according to the idea of ​​the present invention, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present invention.

Claims

1. A display panel, comprising a display area and a non-display area arranged on at least one side of the display area, characterized in that: The display panel comprises: substrate; A shielding layer, located on the substrate, the shielding layer includes at least two layers, the shielding layer includes a plurality of shielding blocks and a convergence line electrically connected to the plurality of shielding blocks, the convergence line is located on at least one side of the plurality of shielding blocks; a pixel driving circuit layer, located on the shielding layer, comprising a plurality of pixel driving circuits located in the display area, each of the pixel driving circuits at least partially overlapping with the corresponding shielding block; and A first conductive layer is arranged on a side of the shielding layer away from the substrate, the first conductive layer comprising: a plurality of power lines, the plurality of power lines being electrically connected to the convergence wiring through a plurality of through holes; Wherein, the converging wiring between adjacent through holes is arranged in a straight line shape.

2. The display panel according to claim 1, characterized in that: The material of the shielding layer includes at least two of molybdenum, titanium, aluminum, and indium tin oxide.

3. The display panel according to claim 1, characterized in that: The converging wiring is arranged in a straight line, and the plurality of through holes overlapping with the converging wiring are arranged in a straight line.

4. The display panel according to claim 1, characterized in that: The converging routing includes a first converging routing, the first converging routing includes a plurality of first connecting segments and a plurality of second connecting segments, wherein each of the second connecting segments is connected between the middle portions of two adjacent first connecting segments, the width of the first connecting segment is greater than the width of the second connecting segment, and the plurality of power lines are electrically connected to the plurality of first connecting segments through the plurality of through holes.

5. The display panel according to claim 4, characterized in that: The pixel driving circuit layer includes a plurality of pixel driving circuits arranged in an array along a first direction and a second direction, and each of the first connecting segments is electrically connected to a shielding block corresponding to a column of the pixel driving circuits arranged along the first direction.

6. The display panel according to claim 5, characterized in that: The outer periphery of the first connecting section is in an arc shape, the second connecting section is in a straight line shape, and the maximum width of the first connecting section is greater than the width of the second connecting section.

7. The display panel according to claim 1, characterized in that: The non-display area includes: a first non-display area and a second non-display area arranged at both sides of the display area, the first non-display area includes a bending sub-area, and the display panel is bent in the bending sub-area; The convergent wiring includes a first convergent wiring arranged in the first non-display area, and the plurality of power lines are electrically connected to the first convergent wiring through at least a plurality of the through holes.

8. The display panel according to claim 7, characterized in that: The convergent wiring includes a second convergent wiring arranged in the second non-display area, and the plurality of power lines are also electrically connected to the second convergent wiring through the plurality of through holes.

9. The display panel according to claim 1, characterized in that: The pixel driving circuit layer comprises: A semiconductor layer, disposed on a side of the shielding layer away from the substrate; A first insulating layer, disposed on a side of the semiconductor layer away from the substrate; A first gate metal layer is disposed on a side of the first insulating layer away from the substrate; A second insulating layer is disposed on a side of the first gate metal layer away from the substrate; A second gate metal layer is disposed on a side of the second insulating layer away from the substrate; A third insulating layer is disposed on a side of the second gate metal layer away from the substrate; The first conductive layer is arranged on a side of the third insulating layer away from the substrate, and the plurality of power lines of the first conductive layer are electrically connected to the convergent routing lines through a plurality of through holes, and the through holes pass through the first insulating layer, the second insulating layer, and the third insulating layer.

10. The display panel according to claim 9, characterized in that: The pixel driving circuit layer also includes: a fourth insulating layer, disposed between the second gate metal layer and the third insulating layer; A second conductive layer is disposed between the fourth insulating layer and the third insulating layer; The through hole includes a first through hole and a second through hole, the first through hole passes through the first insulating layer, the second insulating layer, and the fourth insulating layer, the second through hole passes through the third insulating layer, the first through hole is connected to the second through hole, and the diameter of the second through hole is greater than the diameter of the first through hole.

11. A display device, characterized in that: Comprising the display panel as described in any one of claims 1-10.

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