Multilayer ceramic capacitor

Abstract

The invention provides a multilayer ceramic capacitor capable of suppressing electric field concentration. The present invention is provided with: a laminate (10) having a plurality of dielectric layers (20) and a plurality of internal electrode layers (30); and a first external electrode (40A) and a second external electrode (40B), the plurality of internal electrode layers (30) have a plurality of first internal electrode layers (31) and second internal electrode layers (32) electrically connected to the first external electrode (40A) and the second external electrode (40B), respectively, and a plurality of holes (H) having different area-equivalent diameters are present in the first internal electrode layers (31) and the second internal electrode layers (32). The thickness t of the dielectric layer (20) is 0.5 [mu] m or more, where D99 is the area-equivalent diameter at which the cumulative value in the cumulative distribution of the area-equivalent diameters of the plurality of holes (H) is 99%, and t is the thickness of the dielectric layer (20) sandwiched between the first internal electrode layer (31) and the second internal electrode layer (32), and the following formula (1) is satisfied. (area equivalent diameter D99) lt; and 0.0879 * exp (2.86 * t)... (1).

Description

Technical Field

[0001] The present invention relates to a laminated ceramic capacitor. Background Art

[0002] In the past, laminated ceramic capacitors were known. Generally speaking, a laminated ceramic capacitor has a laminated body in which a plurality of dielectric layers and internal electrode layers are alternately laminated. In addition to being used in small electronic devices such as smartphones with low rated voltages, such laminated ceramic capacitors can also be used for automotive applications with relatively high rated voltages. When a laminated ceramic capacitor is used for applications with high rated voltages, it is required to ensure high reliability when voltage is applied.

[0003] Prior Art Literature

[0004] Patent Literature

[0005] Patent Document 1: Japanese Patent Application Publication No. 2000-133545 Summary of the invention

[0006] Problem that the invention aims to solve

[0007] For example, Patent Document 1 shows that if a laminated ceramic capacitor with a thin dielectric layer is used for high voltage, insulation breakdown may occur due to the concentration of the electric field. On the other hand, if the distance between the internal electrode layers is increased, and the distance between the internal electrode layers and the surface of the capacitor element is increased, a high withstand voltage can be achieved. In addition, Patent Document 1 also shows that by providing a plurality of auxiliary electrodes, the electric field concentration can be suppressed and a high withstand voltage can be achieved. However, Patent Document 1 does not consider the effect of the holes in the internal electrode layer on the electric field concentration of the laminated ceramic capacitor.

[0008] An object of the present invention is to provide a multilayer ceramic capacitor capable of suppressing electric field concentration.

[0009] Technical solutions to solve problems

[0010] The multilayer ceramic capacitor of the present invention comprises: a multilayer body having a plurality of stacked dielectric layers and a plurality of internal electrode layers stacked on the dielectric layers, and having a first main surface and a second main surface opposite to each other in a height direction, a first side surface and a second side surface opposite to each other in a width direction perpendicular to the height direction, and a first end surface and a second end surface opposite to each other in a length direction perpendicular to the height direction and the width direction; and a first external electrode and a second external electrode, wherein the plurality of internal electrode layers have: a plurality of first internal electrode layers opposite to the first The invention relates to a method for manufacturing a dielectric layer having a first internal electrode layer and a second internal electrode layer, wherein the dielectric layer has a first internal electrode layer and a second internal electrode layer, wherein the dielectric layer has a first internal electrode layer and a second internal electrode layer, and wherein the dielectric layer has a first internal electrode layer and a second internal electrode layer. The dielectric layer has a first internal electrode layer and a second internal electrode layer, wherein the dielectric layer has a first internal electrode layer and a second internal electrode layer. The dielectric layer has a first internal electrode layer and a second internal electrode layer. The dielectric layer has a first internal electrode layer and a second internal electrode layer. The dielectric layer has a first internal electrode layer and a second internal electrode layer. The dielectric layer has a first internal electrode layer and a second internal electrode layer.

[0011] (area equivalent diameter D99) < 0.0879 × exp (2.86 × t) ... (1)

[0012] Effects of the Invention

[0013] According to the present invention, it is possible to provide a multilayer ceramic capacitor capable of suppressing electric field concentration. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 It is a perspective view of the appearance of a multilayer ceramic capacitor according to an embodiment.

[0015] Figure 2 yes Figure 1 A cross-sectional view of the multilayer ceramic capacitor taken along line II-II is shown.

[0016] Figure 3 yes Figure 2 A cross-sectional view of the multilayer ceramic capacitor taken along line III-III is shown.

[0017] Figure 4A yes Figure 2 A cross-sectional view of the multilayer ceramic capacitor taken along line IVA-IVA is shown.

[0018] Figure 4B yes Figure 2 A cross-sectional view of the multilayer ceramic capacitor taken along line IVB-IVB is shown.

[0019] Figure 5 yes Figure 4A An enlarged view of the V portion of the multilayer ceramic capacitor 1 is shown.

[0020] Figure 6 This is a diagram showing area-equivalent diameter distribution data of a plurality of pores existing in the internal electrode layer.

[0021] Fig. 7A FIG. 1 is a diagram showing a model of an internal electrode layer used in the simulation.

[0022] Figure 7B 1 is a diagram showing the electric field intensity distribution near the hole of the internal electrode layer.

[0023] Figure 8 This is a graph in which the maximum electric field intensity in the model calculated in each simulation model is plotted. In each simulation model, the value of the area equivalent diameter D99 of the pores existing in the internal electrode layer is changed.

[0024] Fig. 9 This is a graph plotting the maximum electric field intensity in the model calculated in each simulation model, wherein the thickness of the dielectric layer and the value of the area equivalent diameter D99 of the pores present in the internal electrode layer are changed in each simulation model.

[0025] Fig.10 This is a graph for illustrating a region where electric field concentration can be suppressed when a voltage is applied.

[0026] Fig.11 This is a diagram for explaining a method for measuring the thickness of an internal electrode layer and a dielectric layer, and is a diagram showing an example of an enlarged image of a cross section of an exposed effective layer portion in a multilayer ceramic capacitor observed by SEM.

[0027] Fig.12 is with Figure 3 The SEM image corresponding to the enlarged view of the portion XII of the multilayer ceramic capacitor shown is a diagram showing a burnout state of the multilayer body at the time of dielectric breakdown when an accelerated life test is performed. DETAILED DESCRIPTION

[0028] Hereinafter, a multilayer ceramic capacitor 1 according to an embodiment of the present disclosure will be described. Figure 1 It is a perspective view of the appearance of the multilayer ceramic capacitor 1 according to the present embodiment. Figure 2 yes Figure 1 sectional view of the multilayer ceramic capacitor 1 taken along line II-II. Figure 3 yes Figure 2 sectional view of the multilayer ceramic capacitor 1 taken along line III-III. Figure 4A yes Figure 2 FIG. 1 is a cross-sectional view of the multilayer ceramic capacitor 1 taken along line IVA-IVA. Figure 4B yes Figure 21 is a cross-sectional view of the multilayer ceramic capacitor 1 taken along line IVB-IVB.

[0029] The multilayer ceramic capacitor 1 includes a multilayer body 10 and external electrodes 40 .

[0030] exist Figure 1 to Figure 4B The XYZ orthogonal coordinate system is shown. The length direction L of the laminated ceramic capacitor 1 and the laminated body 10 corresponds to the X direction. The width direction W of the laminated ceramic capacitor 1 and the laminated body 10 corresponds to the Y direction. The height direction T of the laminated ceramic capacitor 1 and the laminated body 10 corresponds to the Z direction. Here, Figure 2 The section shown is also referred to as the LT section. Figure 3 The section shown is also referred to as the WT section. Figure 4A as well as Figure 4B The section shown is also referred to as the LW section.

[0031] like Figure 1 to Figure 4B As shown, the stack 10 includes a first main surface TS1 and a second main surface TS2 opposite to each other in a height direction T, a first side surface WS1 and a second side surface WS2 opposite to each other in a width direction W perpendicular to the height direction T, and a first end surface LS1 and a second end surface LS2 opposite to each other in a length direction L perpendicular to the height direction T and the width direction W.

[0032] like Figure 1 As shown, the stack 10 has a substantially rectangular parallelepiped shape. In addition, the dimension in the length direction L of the stack 10 is not necessarily longer than the dimension in the width direction W. It is preferred that the corners and ridges of the stack 10 are rounded. The corner is the portion where three faces of the stack intersect, and the ridge is the portion where two faces of the stack intersect. In addition, a part or all of the surface constituting the stack 10 may be formed with concave and convex portions.

[0033] The size of the laminate 10 is not particularly limited. If the size in the length direction L of the laminate 10 is set to L size, the L size is preferably 0.2 mm or more and 6 mm or less. In addition, if the size in the height direction T of the laminate 10 is set to T size, the T size is preferably 0.05 mm or more and 5 mm or less. In addition, if the size in the width direction W of the laminate 10 is set to W size, the W size is preferably 0.1 mm or more and 5 mm or less.

[0034] like Figure 2 as well as Figure 3 As shown, the laminate 10 includes an inner layer portion 11 , and a first main surface side outer layer portion 12 and a second main surface side outer layer portion 13 arranged in the height direction T so as to sandwich the inner layer portion 11 .

[0035] The inner layer portion 11 includes a plurality of dielectric layers 20 and a plurality of internal electrode layers 30. The inner layer portion 11 includes the internal electrode layer 30 located closest to the first main surface TS1 side to the internal electrode layer 30 located closest to the second main surface TS2 side in the height direction T. In the inner layer portion 11, the plurality of internal electrode layers 30 are arranged opposite to each other with the dielectric layer 20 interposed therebetween. The inner layer portion 11 is a portion that generates electrostatic capacitance and substantially functions as a capacitor.

[0036] The plurality of dielectric layers 20 are composed of dielectric materials. The dielectric material may be, for example, a dielectric ceramic containing BaTiO3, CaTiO3, SrTiO3, or CaZrO3. In addition, the dielectric material may be a material in which a secondary component such as a Mn compound, a Fe compound, a Cr compound, a Co compound, or a Ni compound is added to these main components. The dielectric material is particularly preferably a material containing BaTiO3 as a main component.

[0037] The thickness of the dielectric layer 20 is preferably 0.5 μm or more. For example, the thickness t of the dielectric layer 20 may be 0.5 μm or more and 1.6 μm or less. The number of laminated dielectric layers 20 is preferably 15 or more and 1200 or less. In addition, the number of dielectric layers 20 is the total number of dielectric layers of the inner layer portion 11 and the number of dielectric layers of the first main surface side outer layer portion 12 and the second main surface side outer layer portion 13.

[0038] The plurality of internal electrode layers 30 include a plurality of first internal electrode layers 31 and a plurality of second internal electrode layers 32. The plurality of first internal electrode layers 31 are arranged on the plurality of dielectric layers 20. The plurality of second internal electrode layers 32 are arranged on the plurality of dielectric layers 20. The plurality of first internal electrode layers 31 and the plurality of second internal electrode layers 32 are alternately arranged in the height direction T of the laminate 10 with the dielectric layers 20 interposed therebetween. The first internal electrode layers 31 and the second internal electrode layers 32 are arranged so as to sandwich the dielectric layer 20.

[0039] The first internal electrode layer 31 includes a first opposing portion 31A opposing the second internal electrode layer 32 and a first lead portion 31B led out from the first opposing portion 31A to the first end surface LS1. The first lead portion 31B is exposed on the first end surface LS1.

[0040] The second internal electrode layer 32 includes a second opposing portion 32A opposing the first internal electrode layer 31 and a second lead portion 32B led out from the second opposing portion 32A to the second end surface LS2. The second lead portion 32B is exposed at the second end surface LS2.

[0041] In the present embodiment, the first opposing portion 31A and the second opposing portion 32A are opposed to each other via the dielectric layer 20 , thereby forming capacitance and exhibiting capacitor characteristics.

[0042] The shapes of the first opposing portion 31A and the second opposing portion 32A are not particularly limited, and are preferably rectangular. However, the corners of the rectangular shape may be rounded, or the corners of the rectangular shape may be formed obliquely. The shapes of the first lead-out portion 31B and the second lead-out portion 32B are not particularly limited, and are preferably rectangular. However, the corners of the rectangular shape may be rounded, or the corners of the rectangular shape may be formed obliquely.

[0043] The dimension of the first opposing portion 31A in the width direction W and the dimension of the first lead portion 31B in the width direction W may be formed to be the same dimension, or one of the dimensions may be formed to be smaller. The dimension of the second opposing portion 32A in the width direction W and the dimension of the second lead portion 32B in the width direction W may be formed to be the same dimension, or one of the dimensions may be formed to be smaller.

[0044] like Figure 4A As shown, the first internal electrode layer 31 has a first side WE1 on the first side surface WS1 side and a second side WE2 on the second side surface WS2 side. Figure 4B As shown, the second internal electrode layer 32 has a third side WE3 on the first side surface WS1 side and a fourth side WE4 on the second side surface WS2 side.

[0045] The first internal electrode layer 31 and the second internal electrode layer 32 are made of a suitable conductive material such as a metal such as Ni, Cu, Ag, Pd, Au, or an alloy containing at least one of these metals. When an alloy is used, the first internal electrode layer 31 and the second internal electrode layer 32 may be made of, for example, an Ag-Pd alloy.

[0046] The thickness of each of the first internal electrode layer 31 and the second internal electrode layer 32 is preferably about 0.2 μm or more and 2.0 μm or less. The total number of the first internal electrode layers 31 and the second internal electrode layers 32 is preferably 15 or more and 1000 or less.

[0047] The first main surface side outer layer portion 12 is located on the first main surface TS1 side of the stacked body 10. The first main surface side outer layer portion 12 is an aggregate of a plurality of dielectric layers 20 located between the first main surface TS1 and the internal electrode layer 30 closest to the first main surface TS1. The dielectric layer 20 used in the first main surface side outer layer portion 12 may be the same as the dielectric layer 20 used in the internal layer portion 11.

[0048] The second main surface side outer layer portion 13 is located on the second main surface TS2 side of the stacked body 10. The second main surface side outer layer portion 13 is an aggregate of a plurality of dielectric layers 20 located between the second main surface TS2 and the internal electrode layer 30 closest to the second main surface TS2. The dielectric layer 20 used in the second main surface side outer layer portion 13 may be the same as the dielectric layer 20 used in the internal layer portion 11.

[0049] As described above, the laminated body 10 includes a plurality of laminated dielectric layers 20 and a plurality of internal electrode layers 30 laminated on the dielectric layers 20. That is, the laminated ceramic capacitor 1 includes the laminated body 10 in which the dielectric layers 20 and the internal electrode layers 30 are alternately laminated.

[0050] The laminate 10 also includes an opposing electrode portion 11E. The opposing electrode portion 11E is a portion where the first opposing portion 31A of the first internal electrode layer 31 and the second opposing portion 32A of the second internal electrode layer 32 face each other. The opposing electrode portion 11E is configured as a part of the inner layer portion 11. Figure 4A as well as Figure 4B , the range of the opposing electrode portion 11E in the width direction W and the length direction L is shown. In addition, the opposing electrode portion 11E is also referred to as a capacitor effective portion.

[0051] In addition, the stacked body 10 has a side outer layer portion. The side outer layer portion has a first side outer layer portion WG1 and a second side outer layer portion WG2. The first side outer layer portion WG1 is a portion including the dielectric layer 20 located between the opposing electrode portion 11E and the first side WS1. The second side outer layer portion WG2 is a portion including the dielectric layer 20 located between the opposing electrode portion 11E and the second side WS2. Figure 3 , Figure 4A as well as Figure 4B , the range of the first side outer layer portion WG1 and the second side outer layer portion WG2 in the width direction W is shown. In addition, the side outer layer portion is also called a W interval or a side interval.

[0052] In addition, the stacked body 10 has an end face side outer layer portion. The end face side outer layer portion has a first end face side outer layer portion LG1 and a second end face side outer layer portion LG2. The first end face side outer layer portion LG1 is a portion including the dielectric layer 20 located between the opposing electrode portion 11E and the first end face LS1. The second end face side outer layer portion LG2 is a portion including the dielectric layer 20 located between the opposing electrode portion 11E and the second end face LS2. Figure 2 , Figure 4A as well as Figure 4B , the range of the first end surface side outer layer portion LG1 and the second end surface side outer layer portion LG2 in the length direction L is shown. In addition, the end surface side outer layer portion is also referred to as an L interval or an end interval.

[0053] The external electrode 40 includes a first external electrode 40A disposed on the first end surface LS1 side and a second external electrode 40B disposed on the second end surface LS2 side.

[0054] The first external electrode 40A is arranged on the first end surface LS1. The first external electrode 40A is connected to the first internal electrode layer 31. The first external electrode 40A may also be arranged on a portion of the first main surface TS1 and a portion of the second main surface TS2 and a portion of the first side surface WS1 and a portion of the second side surface WS2. In the present embodiment, the first external electrode 40A is formed to extend from the first end surface LS1 to a portion of the first main surface TS1 and a portion of the second main surface TS2 and a portion of the first side surface WS1 and a portion of the second side surface WS2.

[0055] The second external electrode 40B is arranged on the second end surface LS2. The second external electrode 40B is connected to the second internal electrode layer 32. The second external electrode 40B may also be arranged on a portion of the first main surface TS1 and a portion of the second main surface TS2 and a portion of the first side surface WS1 and a portion of the second side surface WS2. In the present embodiment, the second external electrode 40B is formed to extend from the second end surface LS2 to a portion of the first main surface TS1 and a portion of the second main surface TS2 and a portion of the first side surface WS1 and a portion of the second side surface WS2.

[0056] As described above, in the laminate 10, the first opposing portion 31A of the first internal electrode layer 31 and the second opposing portion 32A of the second internal electrode layer 32 are opposed to each other via the dielectric layer 20, thereby forming a capacitor. Therefore, the first external electrode 40A connected to the first internal electrode layer 31 and the second external electrode 40B connected to the second internal electrode layer 32 exhibit capacitor characteristics.

[0057] The first external electrode 40A includes a first foundation electrode layer 50A and a first plating layer 60A disposed on the first foundation electrode layer 50A.

[0058] The second external electrode 40B includes a second foundation electrode layer 50B and a second plating layer 60B disposed on the second foundation electrode layer 50B.

[0059] The first foundation electrode layer 50A is arranged on the first end surface LS1. The first foundation electrode layer 50A is connected to the first internal electrode layer 31. In the present embodiment, the first foundation electrode layer 50A is formed to extend from the first end surface LS1 to a portion of the first main surface TS1 and a portion of the second main surface TS2 and a portion of the first side surface WS1 and a portion of the second side surface WS2.

[0060] The second foundation electrode layer 50B is arranged on the second end surface LS2. The second foundation electrode layer 50B is connected to the second internal electrode layer 32. In the present embodiment, the second foundation electrode layer 50B is formed to extend from the second end surface LS2 to a portion of the first main surface TS1 and a portion of the second main surface TS2 and a portion of the first side surface WS1 and a portion of the second side surface WS2.

[0061] The first base electrode layer 50A and the second base electrode layer 50B of the present embodiment are sintered layers. The sintered layer preferably contains a metal component and either a glass component or a ceramic component, or both. As for the metal component, for example, it contains at least one selected from Cu, Ni, Ag, Pd, Ag-Pd alloy, Au, etc. As for the glass component, for example, it contains at least one selected from B, Si, Ba, Mg, Al, Li, etc. As for the ceramic component, the same type of ceramic material as the dielectric layer 20 can be used, or a different type of ceramic material from the dielectric layer 20 can be used. As for the ceramic component, for example, it contains at least one selected from BaTiO3, CaTiO3, (Ba, Ca)TiO3, SrTiO3, CaZrO3, etc.

[0062] The sintered layer is, for example, a sintered layer obtained by applying a conductive paste containing glass and metal to the laminate and sintering it. The sintered layer may be a sintered layer obtained by simultaneously sintering a laminated chip having an internal electrode and a dielectric layer and a conductive paste applied to the laminated chip, or a sintered layer obtained by sintering a laminated chip having an internal electrode and a dielectric layer and then applying a conductive paste to the laminate and sintering it. In addition, when the laminated chip having an internal electrode and a dielectric layer and the conductive paste applied to the laminated chip are sintered at the same time, the sintered layer is preferably formed by sintering a paste to which a ceramic material is added instead of a glass component. In this case, as the added ceramic material, it is particularly preferred to use a ceramic material of the same type as the dielectric layer 20. The sintered layer may also be a plurality of layers.

[0063] The thickness of the first foundation electrode layer 50A located at the first end surface LS1 in the longitudinal direction is preferably about 3 μm or more and 200 μm or less in the central portion in the height direction T and the width direction W of the first foundation electrode layer 50A, for example.

[0064] The thickness of the second foundation electrode layer 50B located at the second end surface LS2 in the longitudinal direction is preferably about 3 μm or more and 200 μm or less in the central portion in the height direction T and the width direction W of the second foundation electrode layer 50B, for example.

[0065] When the first base electrode layer 50A is also provided on a portion of at least one of the first main surface TS1 or the second main surface TS2, the thickness in the height direction of the first base electrode layer 50A provided on the portion is preferably, for example, greater than 3 μm and less than 25 μm in the central portion in the length direction L and the width direction W of the first base electrode layer 50A provided on the portion.

[0066] When the first base electrode layer 50A is also provided on a portion of at least one of the first side surface WS1 or the second side surface WS2, the thickness in the width direction of the first base electrode layer 50A provided on the portion is preferably, for example, greater than 3 μm and less than 25 μm in the central portion in the length direction L and the height direction T of the first base electrode layer 50A provided on the portion.

[0067] When a second base electrode layer 50B is also provided on a portion of at least one of the first main surface TS1 or the second main surface TS2, the thickness in the height direction of the second base electrode layer 50B provided on the portion is preferably, for example, greater than 3 μm and less than 25 μm in the central portion in the length direction L and the width direction W of the second base electrode layer 50B provided on the portion.

[0068] When the second base electrode layer 50B is also provided on a portion of at least one of the first side surface WS1 or the second side surface WS2, the thickness in the width direction of the second base electrode layer 50B provided on the portion is preferably, for example, greater than 3 μm and less than 25 μm in the central portion in the length direction L and the height direction T of the second base electrode layer 50B provided on the portion.

[0069] In addition, the first base electrode layer 50A and the second base electrode layer 50B are not limited to sintered layers. The first base electrode layer 50A and the second base electrode layer 50B include at least one selected from a sintered layer, a conductive resin layer, a thin film layer, etc. For example, the first base electrode layer 50A and the second base electrode layer 50B may also be a thin film layer. The thin film layer is formed by a thin film forming method such as a sputtering method or a vapor deposition method. The thin film layer is a layer of less than 10 μm on which metal particles are deposited.

[0070] The first plating layer 60A is arranged to cover the first foundation electrode layer 50A.

[0071] The second plating layer 60B is arranged to cover the second base electrode layer 50B.

[0072] The first plating layer 60A and the second plating layer 60B may include, for example, at least one selected from Cu, Ni, Sn, Ag, Pd, Ag-Pd alloy, Au, etc. The first plating layer 60A and the second plating layer 60B may also be formed of a plurality of layers. The first plating layer 60A and the second plating layer 60B are preferably a two-layer structure in which a Sn plating layer is formed on a Ni plating layer.

[0073] The first plating layer 60A is disposed so as to cover the first base electrode layer 50A. In the present embodiment, the first plating layer 60A includes a first Ni plating layer 61A and a first Sn plating layer 62A located on the first Ni plating layer 61A.

[0074] The second plating layer 60B is arranged to cover the second base electrode layer 50B. In the present embodiment, the second plating layer 60B includes a second Ni plating layer 61B and a second Sn plating layer 62B located on the second Ni plating layer 61B.

[0075] The Ni plating layer prevents the first base electrode layer 50A and the second base electrode layer 50B from being corroded by the solder when mounting the multilayer ceramic capacitor 1. In addition, the Sn plating layer improves the wettability of the solder when mounting the multilayer ceramic capacitor 1. Thus, the mounting of the multilayer ceramic capacitor 1 becomes easy. The thickness of each of the first Ni plating layer 61A, the first Sn plating layer 62A, the second Ni plating layer 61B, and the second Sn plating layer 62B is preferably 2 μm or more and 10 μm or less.

[0076] In addition, the first external electrode 40A and the second external electrode 40B of the present embodiment may also have a conductive resin layer containing conductive particles and a thermosetting resin, for example. When a conductive resin layer is provided as a base electrode layer (the first base electrode layer 50A, the second base electrode layer 50B), the conductive resin layer may be configured to cover the sintered layer, or may be directly provided on the laminate 10 without providing the sintered layer. When the conductive resin layer is configured to cover the sintered layer, the conductive resin layer is provided between the sintered layer and the plating layer (the first plating layer 60A, the second plating layer 60B). The conductive resin layer may completely cover the sintered layer, or may cover a portion of the sintered layer.

[0077] The conductive resin layer containing a thermosetting resin is more flexible than a conductive layer composed of, for example, a plated film or a fired product of a conductive paste. Therefore, even when a physical impact or an impact caused by a thermal cycle is applied to the multilayer ceramic capacitor 1, the conductive resin layer functions as a buffer layer. Therefore, the conductive resin layer suppresses the generation of cracks in the multilayer ceramic capacitor 1.

[0078] The metal constituting the conductive particles may also be Ag, Cu, Ni, Sn, Bi or an alloy containing them. The conductive particles preferably contain Ag. The conductive particles are, for example, Ag metal powder. Ag has the lowest specific resistance among metals and is therefore suitable for electrode materials. In addition, Ag is a noble metal and is therefore not easily oxidized and has high weather resistance. Therefore, Ag metal powder is suitable as the conductive particles.

[0079] In addition, the conductive particles may be metal powders coated with Ag on the surface of the metal powders. When using metal powders coated with Ag on the surface of the metal powders, the metal powders are preferably Cu, Ni, Sn, Bi or alloy powders thereof. In order to make the metal of the base material a cheap metal while maintaining the characteristics of Ag, it is preferred to use metal powders coated with Ag.

[0080] Furthermore, the conductive particles may be conductive particles in which Cu and Ni have been subjected to an oxidation prevention treatment. In addition, the conductive particles may be metal powders in which Sn, Ni, and Cu are coated on the surface of the metal powder. When a metal powder in which Sn, Ni, and Cu are coated on the surface of the metal powder is used, the metal powder is preferably Ag, Cu, Ni, Sn, Bi, or an alloy powder thereof.

[0081] The shape of the conductive particles is not particularly limited. The conductive particles may be spherical or flat, but preferably, a mixture of spherical metal powder and flat metal powder is used.

[0082] The conductive particles contained in the conductive resin layer mainly play a role in ensuring the conductivity of the conductive resin layer. Specifically, a plurality of conductive particles are in contact with each other, thereby forming a conductive path inside the conductive resin layer.

[0083] The resin constituting the conductive resin layer may also include at least one selected from various known thermosetting resins such as epoxy resin, phenolic resin, urethane resin, silicone resin, polyimide resin, etc. Among them, epoxy resin with excellent heat resistance, moisture resistance, adhesion, etc. is one of the most suitable resins. In addition, the resin of the conductive resin layer preferably contains a curing agent together with the thermosetting resin. When epoxy resin is used as the base resin, the curing agent of the epoxy resin may also be various known compounds such as phenols, amines, acid anhydrides, imidazoles, active esters, and amide-imides.

[0084] In addition, the conductive resin layer may be formed of a plurality of layers. The thickness of the thickest portion of the conductive resin layer is preferably 10 μm or more and 150 μm or less.

[0085] Alternatively, the following structure may be adopted, that is, without providing the first base electrode layer 50A and the second base electrode layer 50B, and the first plating layer 60A and the second plating layer 60B described later may be directly disposed on the laminate 10. That is, the laminated ceramic capacitor 1 may also have a structure including a plating layer that is directly electrically connected to the first internal electrode layer 31 and the second internal electrode layer 32. In such a case, the plating layer may be formed after a catalyst is disposed on the surface of the laminate 10 as a pretreatment.

[0086] In this case, the plating layer is also preferably a plurality of layers. The lower plating layer and the upper plating layer are preferably respectively composed of at least one metal selected from, for example, Cu, Ni, Sn, Pb, Au, Ag, Pd, Bi or Zn, or an alloy containing these metals. The lower plating layer is more preferably formed using Ni having a solder resist. The upper plating layer is more preferably formed using Sn or Au having good solder wettability. In addition, for example, when Ni is used to form the first internal electrode layer 31 and the second internal electrode layer 32, the lower plating layer is preferably formed using Cu having good bonding properties with Ni. In addition, the upper plating layer can be formed as required, and the external electrode 40 can also be composed only of the lower plating layer. In addition, the plating layer can use the upper plating layer as the outermost layer, or other plating layers can be further formed on the surface of the upper plating layer.

[0087] The thickness of each plating layer arranged without providing a base electrode layer is preferably 2 μm or more and 10 μm or less. In addition, the plating layer preferably does not contain glass. The metal ratio per unit volume of the plating layer is preferably 99 volume % or more.

[0088] In addition, when the plating layer is directly formed on the laminated body 10, the thickness of the base electrode layer can be reduced. Therefore, the dimension of the stacked ceramic capacitor 1 in the height direction T can be reduced in accordance with the reduction in the thickness of the base electrode layer, thereby achieving a lower height of the stacked ceramic capacitor 1. Alternatively, the thickness of the dielectric layer 20 sandwiched between the first internal electrode layer 31 and the second internal electrode layer 32 can be increased in accordance with the reduction in the thickness of the base electrode layer, thereby achieving an increase in the thickness of the body. In this way, by directly forming the plating layer on the laminated body 10, the degree of freedom in designing the stacked ceramic capacitor can be improved.

[0089] In addition, if the dimension in the length direction of the multilayer ceramic capacitor 1 including the stacked body 10 and the external electrode 40 is set to L dimension, the L dimension is preferably 0.2 mm or more and 6 mm or less. In addition, if the dimension in the height direction of the multilayer ceramic capacitor 1 is set to T dimension, the T dimension is preferably 0.05 mm or more and 5 mm or less. In addition, if the dimension in the width direction of the multilayer ceramic capacitor 1 is set to W dimension, the W dimension is preferably 0.1 mm or more and 5 mm or less.

[0090] The inventors of the present application have repeatedly conducted studies, experiments, and simulations and have come to the conclusion that, in order to improve the reliability of a multilayer ceramic capacitor, it is preferable to set the holes in the internal electrode layer to an appropriate state. This will be described below.

[0091] In the past, various methods have been adopted to improve the reliability of multilayer ceramic capacitors. For example, Patent Document 1 discloses a multilayer ceramic capacitor having a multilayer body in which a plurality of dielectric layers and internal electrode layers are alternately stacked and a plurality of auxiliary electrodes. In the multilayer ceramic capacitor of Patent Document 1, by having a plurality of auxiliary electrodes, electric field concentration is suppressed and the reliability of the product is improved. However, in Patent Document 1, the influence of the holes in the internal electrode layer on the reliability of the multilayer ceramic capacitor is not considered. Therefore, additional components such as auxiliary electrodes are required.

[0092] The inventors of the present application have considered the above contents and have conducted intensive research on the structure of the internal electrode layer, that is, by ensuring the thickness of the dielectric layer, basic voltage resistance can be ensured, and further, electric field concentration can be suppressed to improve reliability when voltage is applied. As a result, the inventors of the present application have obtained the following insight, that is, as long as the structure of the present embodiment is provided, electric field concentration can be suppressed and reliability when voltage is applied can be improved.

[0093] Specifically, the inventors of the present application have found that when insulation breakdown occurs in a laminated ceramic capacitor, burning starts from the location where the holes exist in the internal electrode layer. Furthermore, the inventors of the present application have found that by adjusting the size of the area equivalent diameter D99 described later of the plurality of holes in the internal electrode layer, electric field concentration can be suppressed even when a relatively high voltage is applied.

[0094] More specifically, the inventors of the present application have found that by setting the following structure, it is possible to ensure basic voltage resistance by ensuring the thickness of the dielectric layer 20, and further, it is possible to suppress electric field concentration when voltage is applied. The structure is that when the area equivalent diameter at which the cumulative value of the cumulative distribution of the area equivalent diameters of the plurality of holes H existing in the first internal electrode layer 31 and the second internal electrode layer 32 becomes 99% is set as the area equivalent diameter D99, and the thickness of the dielectric layer 20 sandwiched between the first internal electrode layer 31 and the second internal electrode layer 32 is set to thickness t, the thickness t of the dielectric layer 20 is greater than 0.5 μm, and also satisfies the following formula (1).

[0095] (area equivalent diameter D99) < 0.0879 × exp (2.86 × t) ... (1)

[0096] Hereinafter, the dielectric layer 20 and the internal electrode layer 30 of the present embodiment will be described in detail.

[0097] Figure 5 yes Figure 4A The enlarged view of the V portion of the multilayer ceramic capacitor 1 shown in FIG. 1 is a view exemplarily showing the state of the first internal electrode layer 31 as the internal electrode layer 30. More specifically, Figure 5 This is a diagram when the internal electrode layer 30 in the WT section of the multilayer ceramic capacitor 1 of the present embodiment is observed in the height direction T connecting the first main surface TS1 and the second main surface TS2, that is, it is a diagram when the internal electrode layer 30 in the WT section of the multilayer ceramic capacitor 1 of the present embodiment is viewed from above. In addition, the covering state of the first internal electrode layer 31 on the dielectric layer 20 and the covering state of the second internal electrode layer 32 on the dielectric layer 20 when observed in the height direction T connecting the first main surface TS1 and the second main surface TS2 become basically the same state. Therefore, in the following description, the first internal electrode layer 31 and the second internal electrode layer 32 are collectively described as the internal electrode layer 30 as needed.

[0098] Figure 5 1 is a diagram showing the internal electrode layer 30 in the vicinity of the first side WE1 which is a side of the internal electrode layer 30. Figure 5 As shown, a plurality of holes H having different area equivalent diameters exist in the internal electrode layer 30. Figure 5 The thickness of the internal electrode layer 30 shown is 0.6 μm, and the coverage of the dielectric layer 20 by the internal electrode layer is 81%. In addition, the inside of the hole H of the internal electrode layer 30 may be a void, or a glass component such as a dielectric or silicon dioxide may exist. When the inside of the hole H of the internal electrode layer 30 is a void, the dielectric layer 20 can be seen through the hole H. In addition, the thickness of the dielectric layer 20 sandwiched between the two internal electrode layers 30 (the first internal electrode layer 31 and the second internal electrode layer 32) is 1.4 μm.

[0099] Figure 6 : is a graph showing area-equivalent diameter distribution data of a plurality of holes H present in the internal electrode layer 30. Figure 6 In the figure, the cumulative % versus area equivalent diameter is shown. Figure 6 The horizontal axis is the area equivalent diameter of hole H, Figure 6 The vertical axis is cumulative %, which represents the value obtained by dividing the number of holes H with an area equivalent diameter or less (the cumulative value of the number of holes H) by the total number (the number of holes H forming the parent set). That is, Figure 6 The area equivalent diameter distribution data shown is the area equivalent diameter distribution data based on the number of pieces. Figure 6The data is the area equivalent diameter distribution data in the measurement target area near the edge of the internal electrode layer 30, which is the area equivalent diameter distribution data in the measurement target area near the edge of the internal electrode layer 30. Figure 5 The data when the hole H in the larger area shown in the figure is used as the parent set.

[0100] In the multilayer ceramic capacitor 1 of the present embodiment, when the area equivalent diameter at which the cumulative value of the cumulative distribution of the area equivalent diameters of the plurality of holes H existing in the first internal electrode layer 31 and the second internal electrode layer 32 becomes 99% is set as the area equivalent diameter D99, and the thickness of the dielectric layer 20 sandwiched between the first internal electrode layer 31 and the second internal electrode layer 32 is set as the thickness t, the thickness t of the dielectric layer 20 is 0.5 μm or more, and the following formula (1) is satisfied. In addition, the unit of the area equivalent diameter D99 and the unit of the thickness t of the dielectric layer 20 are set to be consistent and marked, for example, as "μm".

[0101] (area equivalent diameter D99) < 0.0879 × exp (2.86 × t) ... (1)

[0102] exist Figure 6 In the example of the area equivalent diameter distribution data shown, the area equivalent diameter D99 is 4.7 μm. This is smaller than the value obtained by substituting 1.4 μm into the thickness t on the right side of the formula (1), that is, 4.8 μm. That is, when the thickness t of the dielectric layer 20 is 1.4 μm and the area equivalent diameter distribution data of the internal electrode layer 30 is Figure 6 In the example of the data shown, the thickness t of the dielectric layer 20 is 0.5 μm or more and satisfies the formula (1). With such a structure, it is possible to suppress electric field concentration and improve reliability when voltage is applied.

[0103] The area equivalent diameter is the value of the diameter of a perfect circle having an area equal to the area of ​​the hole H defined by the contour of the hole H. For example, when the area of ​​the hole H defined by the contour of the hole H is 50 μm 2 When , the area equivalent diameter becomes 8.0 μm.

[0104] As described above, the area equivalent diameter D99 is the area equivalent diameter at which the cumulative value in the cumulative distribution of the area equivalent diameters of the plurality of holes H becomes 99%. That is, the value at which the ratio of holes H having an area equivalent diameter equal to or less than this area equivalent diameter becomes 99% is referred to as the area equivalent diameter D99.

[0105] Next, a case where the above-mentioned effect can be obtained will be described using simulation.

[0106] Fig. 7A is a model of the internal electrode layer 30 used in the simulation. In this model, the internal electrode layer 30 is provided on the dielectric layer 20. In addition, in this model, Fig. 7A As shown, a plurality of holes H are randomly arranged. In addition, the area-equivalent diameters of the plurality of holes H vary. In this model, an internal electrode layer 30 having a plurality of holes H randomly arranged is also provided on the back side of the dielectric layer 20, similarly to the front side.

[0107] In addition to being used in small electronic devices such as smartphones with low rated voltages, multilayer ceramic capacitors can also be used for applications such as automotive applications with relatively high rated voltages. When multilayer ceramic capacitors are used for applications with high rated voltages, it is required to ensure high reliability when relatively high voltages are applied. In order to ensure insulation withstand voltage through the basic structure of multilayer ceramic capacitors, it is preferable to ensure the thickness of the dielectric layer 20 sandwiched between the two internal electrode layers 30 (the first internal electrode layer 31 and the second internal electrode layer 32). In this simulation, first, the thickness t of the dielectric layer 20 is set to 1.0 μm.

[0108] In addition, for example, regarding laminated ceramic capacitors for vehicle use, laminated ceramic capacitors with a relatively high rated voltage compared to laminated ceramic capacitors used for smartphones and the like are often used, for example, laminated ceramic capacitors with a rated voltage of about 25 V are used. Therefore, in this simulation, the applied voltage is set to 25 V. In addition, in the simulation, a voltage is applied between the internal electrode layer 30 on the surface side and the internal electrode layer 30 on the back side sandwiching the dielectric layer 20.

[0109] Furthermore, in this simulation, the thickness of the internal electrode layer 30 is set to 0.6 μm, and the coverage of the internal electrode layer 30 to the dielectric layer 20 is set to 88%. In addition, in this simulation, first, a plurality of holes H are set in the internal electrode layer 30 so that the area equivalent diameter D99 becomes 2.0 μm.

[0110] As a result of the simulation under the present setting conditions, a tendency that the electric field is easily concentrated around the contour of the hole H was confirmed. Figure 7B is a diagram showing the electric field intensity distribution near the hole H. Figure 7B In the figure, the electric field strength is shown in grayscale, and the higher the electric field strength, the lighter the color. Figure 7B , it can be confirmed that the electric field is concentrated around the outline of the hole H. In addition, the following tendency can be confirmed, that is, Figure 7B Compared with the contour of the relatively small hole H shown on the right, the electric field is more likely to be concentrated around Figure 7B The left side shows the contour of the relatively large hole H.

[0111] Next, the electric field strength generated in each model was calculated using the model in which the value of the area equivalent diameter D99 was changed. Specifically, a model in which the area equivalent diameter D99 was set to 1.0 μm, a model in which the area equivalent diameter D99 was set to 1.5 μm, and a model in which the area equivalent diameter D99 was set to 4.0 μm were additionally created, and the electric field strength generated in the model was calculated. In addition, the thickness of the internal electrode layer 30, the coverage of the internal electrode layer 30 to the dielectric layer 20, the thickness of the dielectric layer 20, and the applied voltage were set to fixed values ​​and simulation was performed. Figure 8 is a graph showing the results. Figure 8 The horizontal axis (x-axis) is the value of the area equivalent diameter D99 in the model. Figure 8 The vertical axis (y-axis) is the maximum electric field intensity in the model. Figure 8 In FIG. 1 , an approximate curve obtained by fitting the plotted points is shown.

[0112] according to Figure 8 , the following tendency was confirmed, that is, the smaller the value of the area equivalent diameter D99 is, the more the electric field concentration can be suppressed. Figure 8 The approximate curve of the dielectric layer 20 confirms that, when the thickness t of the dielectric layer 20 is 1.0 μm, when the area equivalent diameter D99 of the plurality of holes H present in the internal electrode layer 30 is less than 1.6 μm, the value of the maximum electric field intensity generated in the model is less than 72 MV / m, and the electric field concentration can be suppressed. The value of the maximum electric field intensity is a value that can be allowed in order to ensure the reliability of the multilayer ceramic capacitor.

[0113] Next, the following simulation was performed, that is, the value of the thickness t of the dielectric layer 20 was changed, and the electric field strength was calculated. Specifically, when the thickness t of the dielectric layer 20 was 0.75 μm, the electric field strength in the model was calculated when the area equivalent diameter D99 was set to 1.0 μm, 1.5 μm, and 2.0 μm. In addition, when the thickness t of the dielectric layer 20 was 1.25 μm and 1.4 μm, respectively, the electric field strength in the model was calculated when the area equivalent diameter D99 was set to 1.0 μm, 2.0 μm, and 4.0 μm. In addition, the thickness of the internal electrode layer 30, the coverage of the internal electrode layer 30 to the dielectric layer 20, the thickness of the dielectric layer 20, and the applied voltage were set to fixed values ​​and the simulation was performed.

[0114] Fig. 9 is a graph showing the results. Fig. 9 The horizontal axis (x-axis) is the value of the area equivalent diameter D99 in the model. Fig. 9 The vertical axis (y-axis) is the maximum electric field intensity in the model. Fig. 9In FIG. 1 , an approximate curve obtained by fitting the plotted points is shown.

[0115] like Fig. 9 As shown in FIG. 1 , even when the thickness t of the dielectric layer 20 is 0.75 μm, 1.25 μm, or 1.4 μm, it is confirmed that, similarly to the case of 1.0 μm, the smaller the value of the area equivalent diameter D99 is, the more the electric field concentration can be suppressed. Fig. 9 The approximate curve of , confirms that, when the thickness t of the dielectric layer 20 is 0.75 μm, if the area equivalent diameter D99 of the plurality of holes H present in the internal electrode layer 30 is less than 0.7 μm, the value of the maximum electric field intensity generated in the model is less than 72 MV / m, and the electric field concentration can be suppressed. In addition, it is confirmed that, when the thickness t of the dielectric layer 20 is 1.25 μm, if the area equivalent diameter D99 of the plurality of holes H present in the internal electrode layer 30 is less than 3 μm, the value of the maximum electric field intensity generated in the model is less than 72 MV / m, and the electric field concentration can be suppressed. In addition, it is confirmed that, when the thickness t of the dielectric layer 20 is 1.4 μm, if the area equivalent diameter D99 of the plurality of holes H present in the internal electrode layer 30 is less than 5 μm, the value of the maximum electric field intensity generated in the model is less than 72 MV / m, and the electric field concentration can be suppressed.

[0116] Next, use Fig. 9 The approximate curves shown in FIG. 1 and FIG. 2 show that the maximum electric field intensity generated in the model when the thickness t of the dielectric layer 20 is 0.75 μm, 1 μm, 1.25 μm, and 1.4 μm is calculated to be 72 MV / m in area equivalent diameter D99. Fig.10 Drawn in . Fig.10 The horizontal axis (x axis) is the thickness t of the dielectric layer 20, Fig.10 The vertical axis (y-axis) is the value of the area equivalent diameter D99. Fig.10 In FIG. 1 , an approximate curve obtained by fitting the plotted points is shown.

[0117] In the laminated ceramic capacitor 1 in which the thickness of the dielectric layer 20 sandwiched between the plurality of internal electrode layers is a given thickness, by setting the area-equivalent diameter D99 of the plurality of holes H present in the internal electrode layer 30 to be greater than Fig.10The area below the approximate curve of , thereby improving the reliability when voltage is applied. For example, by setting the following structure, the basic insulation withstand voltage can be ensured by ensuring the thickness of the dielectric layer 20, and further, the electric field concentration when voltage is applied can be suppressed. The structure is that when the area equivalent diameter at which the cumulative value of the cumulative distribution of the area equivalent diameters of the plurality of holes H existing in the first internal electrode layer 31 and the second internal electrode layer 32 becomes 99% is set as the area equivalent diameter D99, and the thickness of the dielectric layer 20 sandwiched between the first internal electrode layer 31 and the second internal electrode layer 32 is set as the thickness t, the thickness t of the dielectric layer 20 is set to 0.5μm or more, and the following formula (1) is satisfied. In this case, the area equivalent diameter D99 of the plurality of holes existing in the internal electrode layer may also be 0.37μm or more.

[0118] (area equivalent diameter D99) < 0.0879 × exp (2.86 × t) ... (1)

[0119] In addition, the following structure may be adopted, that is, the thickness t of the dielectric layer is set to be greater than 0.75 μm and the above formula (1) is satisfied. Thus, the basic insulation withstand voltage can be ensured by ensuring the thickness of the dielectric layer, and further, the electric field concentration when the voltage is applied can be suppressed. The area equivalent diameter D99 of the plurality of holes H present in the internal electrode layer 30 may also be greater than 0.75 μm.

[0120] In addition, the following structure may be adopted, that is, the thickness t of the dielectric layer 20 is set to 1.4 μm or less, and the above formula (1) is satisfied. By setting the thickness of the dielectric layer in this way, the decrease in electrostatic capacitance can be suppressed, and the electric field concentration when a voltage is applied can be further suppressed. In addition, by setting the thickness of the dielectric layer 20 in this way, the miniaturization of the multilayer ceramic capacitor 1 can be sought, and the electric field concentration when a voltage is applied can be further suppressed. The area equivalent diameter D99 of the plurality of holes H present in the internal electrode layer 30 may also be 4.8 μm or less.

[0121] In addition, the following structure may be adopted, that is, the thickness t of the dielectric layer 20 is set to 1.0 μm or less, and the above formula (1) is satisfied. By setting the thickness of the dielectric layer 20 in this way, the decrease in electrostatic capacitance can be suppressed, and the electric field concentration when a voltage is applied can be further suppressed. In addition, by setting the thickness of the dielectric layer 20 in this way, the multilayer ceramic capacitor 1 can be miniaturized, and the electric field concentration when a voltage is applied can be further suppressed. The area equivalent diameter D99 of the plurality of holes H present in the internal electrode layer 30 may also be 1.5 μm or less.

[0122] The thickness t of the dielectric layer 20 may be greater than or equal to 0.5 μm and less than or equal to 1.4 μm. Alternatively, the thickness t of the dielectric layer 20 may be greater than or equal to 0.5 μm and less than or equal to 1.0 μm. In addition, the thickness t of the dielectric layer 20 may be greater than or equal to 0.75 μm and less than or equal to 1.4 μm. In addition, the thickness t of the dielectric layer 20 may be greater than or equal to 0.75 μm and less than or equal to 1.0 μm.

[0123] In addition, in the model of this simulation, even when the coverage of the internal electrode layer 30 to the dielectric layer 20 is changed, the value of the maximum electric field strength remains almost unchanged. In order to ensure the electrostatic capacitance, it is preferred that the coverage is high. For example, even when the coverage is 70% or more and 99% or less, the decrease in electrostatic capacitance can be suppressed by adopting the structure of the present embodiment, and the electric field concentration when the voltage is applied can be suppressed. In addition, even when the coverage is as high as 86% or more and 93% or less and the productivity is also good, the decrease in electrostatic capacitance can be suppressed by adopting the structure of the present embodiment, and the electric field concentration when the voltage is applied can be suppressed. The coverage can also be 81% or more and 93% or less.

[0124] In addition, in the model of this simulation, even when the thickness of the internal electrode layer 30 is changed, the value of the maximum electric field strength remains almost unchanged. By reducing the thickness of the internal electrode layer 30, the number of stacked sheets can be increased even for the stacked body 10 of the same size, so that the electrostatic capacitance can be ensured. For example, when the thickness of the internal electrode layer 30 is greater than 0.2 μm and less than 2.0 μm, the structure of this embodiment can be adopted to suppress the decrease in electrostatic capacitance and suppress the electric field concentration when the voltage is applied. In addition, when the thickness of the internal electrode layer 30 is greater than 0.2 μm and less than 0.6 μm, the structure of this embodiment can be adopted to suppress the decrease in electrostatic capacitance and suppress the electric field concentration when the voltage is applied. In addition, when the thickness of the internal electrode layer 30 is greater than 0.2 μm and less than 0.4 μm, the structure of this embodiment can be adopted to suppress the decrease in electrostatic capacitance and suppress the electric field concentration when the voltage is applied.

[0125] In addition, the thickness of the first internal electrode layer 31 and the second internal electrode layer 32 may be thicker than the thickness t of the dielectric layer 20 sandwiched between the first internal electrode layer 31 and the second internal electrode layer 32. Thus, the coverage of the internal electrode layer 30 can be increased, and the area equivalent diameter D99 of the plurality of holes H present in the internal electrode layer 30 can be easily reduced, thereby improving the reliability of the product.

[0126] In addition, in the model of this simulation, even when the area equivalent diameter D99 of the plurality of holes H present in the internal electrode layer 30 is fixed and the average diameter is changed, the value of the maximum electric field intensity remains almost unchanged. Therefore, it can be said that the average pore diameter has a low dependence on the maximum electric field intensity, and the change in the state of the hole H with a large area equivalent diameter contributes most to suppressing the maximum electric field intensity.

[0127] The structure of the present embodiment can be particularly suitably applied to laminated ceramic capacitors for vehicles with a relatively high rated voltage compared to laminated ceramic capacitors for portable electronic devices (for example, laminated ceramic capacitors with a rated voltage of 10V or more, such as laminated ceramic capacitors used at a rated voltage of about 25V). For example, in the laminated ceramic capacitor 1 of the present embodiment, it is preferred that the maximum electric field strength when the rated voltage is applied between the first internal electrode layer 31 and the second internal electrode layer 32 sandwiching the dielectric layer 20 is 72MV / m or less. The rated voltage is, for example, 25V. In the laminated ceramic capacitor 1 of the present embodiment, it is preferred that the maximum electric field strength when 25V is applied between the first internal electrode layer 31 and the second internal electrode layer 32 sandwiching the dielectric layer 20 is 72MV / m or less. For laminated ceramic capacitors with a rated voltage of 6.3V or more and 50V or less (for example, laminated ceramic capacitors with a rated voltage of 10V or more and 25V or less), the laminated ceramic capacitor 1 of the present embodiment can also be used in actual use. However, the use of laminated ceramic capacitors is not limited to this.

[0128] The following describes the measurement methods of various parameters. Various parameters can be confirmed by the following methods.

[0129] <Method for measuring thickness of internal electrode layer and dielectric layer>

[0130] A method for measuring the thicknesses of the dielectric layer 20 and the internal electrode layer 30 of the multilayer ceramic capacitor 1 will be described.

[0131] First, the outer layer of the side surface is removed by grinding from the first side surface WS1 or the second side surface WS2 to expose the internal electrode layer 30. Then, grinding is performed to a degree of 10 μm toward the center side in the width direction W to expose the LT cross section that exposes a plurality of internal electrode layers 30. If necessary, the cross section that exposes the observation position is etched to remove the internal electrode layer 30 that has been stretched by grinding.

[0132] The exposed cross section was observed using a SEM (scanning electron microscope) at the center in the longitudinal direction L and at the upper, central, and lower locations in the stacking direction (height direction T). The observation magnification was set to a magnification that enables observation of the five-layer dielectric layer 20 and the six-layer internal electrode layer 30, and to a magnification that enables clear distinction between the dielectric layer 20 and the internal electrode layer 30. Fig.11 This is a diagram showing an example of an enlarged image of a cross section of the multilayer ceramic capacitor 1 observed using a SEM.

[0133] When measuring the thickness of the internal electrode layer 30 of the multilayer ceramic capacitor 1, first, Fig.11 As shown, in the enlarged image of the cross section of the multilayer ceramic capacitor 1, five straight lines La to Le extending in the stacking direction of the stack 10 are drawn at equal intervals (pitch S). ​​The pitch S can be determined to be 5 to 10 times the thickness of the internal electrode layer 30 to be measured. For example, when measuring the internal electrode layer 30 with a thickness of about 0.5 μm, the pitch S is set to 2.5 μm. Next, the thickness of the internal electrode layer 30 is measured on each of the straight lines La to Le. However, when the internal electrode layer 30 is missing on each of the straight lines La to Le and the dielectric layers 20 sandwiching the internal electrode layer 30 are connected to each other, or when the enlarged image of the measurement position is unclear, a new straight line is drawn to measure the thickness of the internal electrode layer 30.

[0134] For example, when measuring the thickness of the internal electrode layer 30, Fig.11 As shown, the thickness d1 on the straight line La, the thickness d2 on the straight line Lb, the thickness d3 on the straight line Lc, the thickness d4 on the straight line Ld, and the thickness d5 on the straight line Le are measured. Then, for the upper part, the middle part, and the lower part of the cross section of the stacked body 10, the thickness of each of the five layers of the internal electrode layer 30 is measured by the above-mentioned method, and the average value is taken as the thickness of the internal electrode layer 30 of the present embodiment.

[0135] The thickness of the dielectric layer 20 is also measured by the same method as the internal electrode layer 30. When measuring the thickness of the dielectric layer 20, Fig.11 As shown in FIG. 1 , the thickness D1 on the straight line La, the thickness D2 on the straight line Lb, the thickness D3 on the straight line Lc, the thickness D4 on the straight line Ld, and the thickness D5 on the straight line Le are measured. Then, the thickness of each of the five dielectric layers 20 is measured at the upper part, the middle part, and the lower part of the cross section of the laminate 10 by the above-mentioned method, and the average value thereof is taken as the thickness of the dielectric layer 20 of the present embodiment.

[0136] <Measurement area of ​​area equivalent diameter D99, etc.>

[0137] Next, the measurement target area when measuring parameters such as the area-equivalent diameter D99 will be described.

[0138] The inventors of the present application have obtained the following insights through repeated research, experiments, and simulations, namely, in order to improve the reliability of a laminated ceramic capacitor, it is particularly preferred to set the holes in a given area of ​​the internal electrode layer to an appropriate state. Specifically, the inventors of the present application have obtained the following insights through repeated analysis after accelerated life tests of laminated ceramic capacitors, namely, the burnout position of the laminated body of the laminated ceramic capacitor during insulation breakdown is often near the outer layer portion on the side and is a region slightly separated from the edge (end) of the internal electrode layer, and it is preferred to set the holes in this region to an appropriate state.

[0139] Fig.12 is with Figure 3 The SEM image corresponding to the enlarged view of the XII part of the WT cross section of the multilayer ceramic capacitor 1 shown is a diagram showing the burnout state of the multilayer body 10 during the insulation breakdown during the accelerated life test. As described above, in the multilayer ceramic capacitor 1, the burnout site D of the multilayer body 10 is likely to occur in the vicinity of the side outer layer portion WG and in the region slightly separated from the edge of the internal electrode layer 30.

[0140] Therefore, it is preferable to set the plurality of holes H of the internal electrode layer 30 in this region to an appropriate state. The above-mentioned measurement target region is preferably set near the side outer layer portion WG and in a region slightly away from the side of the internal electrode layer 30 .

[0141] Specifically, the region from the position of 10 μm to the position of 50 μm from the first side WE1 in the first internal electrode layer 31 is set as the first region A1, the region from the position of 10 μm to the position of 50 μm from the second side WE2 is set as the second region A2, the region from the position of 10 μm to the position of 50 μm from the third side in the second internal electrode layer 32 is set as the third region A3, and the region from the position of 10 μm to the position of 50 μm from the fourth side is set as the fourth region A4. In this case, it is preferable to use the first region A1, the second region A2, the third region A3, and the fourth region A4 as the measurement target regions. In addition, when the linearity of the first side WE1 to the fourth side WE4 is low, the first region A1 to the fourth region A4 are defined after each side is defined as a straight line by linear fitting based on linear regression or the like.

[0142] exist Figure 4A Schematically shows the first area A1 and the second area A2 as the measurement target areas. Figure 4BSchematically showing the third area A3 and the fourth area A4 as the measurement target areas.

[0143] In the first area A1 , the second area A2 , the third area A3 , and the fourth area A4 as the measurement target areas, a measurement target range for actually measuring parameters based on SEM observation is set.

[0144] In SEM observation, the observation range in one observation field is set to about 40 μm × 40 μm to 80 μm × 80 μm. Then, the analysis target range is set to the 40 μm × 40 μm range therein. Then, based on the set of the analysis target ranges of the 12 locations, parameters such as area equivalent diameter are measured.

[0145] Specifically, in each of the first area A1, the second area A2, the third area A3 and the fourth area A4, three analysis target ranges a are set respectively. The three analysis target ranges a are set within the range of the opposing electrode portion 11E. Among the three analysis target ranges a, the analysis target range a set on the side closest to the first end face LS1 is set at a position 10 μm away from the outer layer portion LG1 on the first end face side. Among the three analysis target ranges a, the analysis target range a set on the side closest to the second end face LS2 is set at a position 10 μm away from the outer layer portion LG2 on the second end face side. Among the three analysis target ranges a, the analysis target range a set at the center is set at a position in the central portion in the length direction L of the stacked body 10. The three analysis target ranges a are set at positions that are equally spaced in the length direction L of the stacked ceramic capacitor. Figure 4A , as an example, the analysis target range a set at three locations in the second area A2 is shown. Then, the measurement target range for measuring parameters such as the area equivalent diameter D99 is set by a collection of the analysis target ranges a of 12 locations in total, 4 regions×3 locations.

[0146] In addition, when the chip size of the multilayer ceramic capacitor 1 is small, the first area A1 to the fourth area A4 may be set at overlapping positions. In addition, each analysis target range a may be set at an overlapping position. In this case, each area is overlapped and set at a different position, and each analysis target range is set to cover the internal electrode layer 30 as large as possible.

[0147] <Measurement method of area equivalent diameter D99>

[0148] A method for measuring the area-equivalent diameter D99 of the pores present in the internal electrode layer 30 will be described.

[0149] First, the internal electrode layer 30 and the dielectric layer 20 located in the center of the stack 10 in the height direction are peeled off by electric field peeling, thereby exposing the internal electrode layer 30. Next, a portion of the first region A1 to the fourth region A4 of the internal electrode layer 30 as the measurement target region is set as the above-mentioned analysis target range a, and SEM observation is performed. In addition, when the first internal electrode layer 31 is exposed, first, a portion of the first region A1 and the second region A2 of the first internal electrode layer 31 are set as the above-mentioned analysis target range a, and SEM observation is performed. Then, the second internal electrode layer 32 is exposed by FIB (focused ion beam) processing. Then, a portion of the third region A3 and the fourth region A4 of the second internal electrode layer 32 are set as the above-mentioned analysis target range a, and SEM observation is performed. In addition, the SEM observation of the first internal electrode layer 31 may be performed after the SEM observation of the second internal electrode layer 32 is performed.

[0150] In the SEM observation, the SEM image is analyzed to identify the contours of each hole H formed in the internal electrode layer 30. Then, for each hole H formed in the internal electrode layer 30, the area equivalent diameter of the hole H is calculated based on the area of ​​the hole H specified by the contour of the hole H. The area equivalent diameter (equivalent diameter of a circle of equal area) is a value of the diameter of a perfect circle having an area equal to the area of ​​the hole H specified by the contour of the hole H.

[0151] For the analysis target range a of 12 locations constituting the measurement target range, the area equivalent diameter of each of the holes H described above is calculated.

[0152] The set of all the wells H identified in the measurement target range (that is, the analysis target range of 12 sites) is set as the parent set of the wells H.

[0153] The area equivalent diameter D99 is calculated based on the data of the area equivalent diameter of the parent set of holes H in the measurement target range. The area equivalent diameter at which the cumulative value of the cumulative distribution of the area equivalent diameters of the plurality of holes H existing in the measurement target region based on the number of holes is 99% is calculated as the area equivalent diameter D99.

[0154] <Method for measuring coverage>

[0155] A method for measuring the coverage ratio, which is the coverage ratio of the internal electrode layer 30 to the dielectric layer 20 , will be described.

[0156] First, the internal electrode layer 30 and the dielectric layer 20 located in the center of the stack 10 in the height direction are peeled off by electric field peeling, thereby exposing the internal electrode layer 30. Next, a portion of the first region A1 to the fourth region A4 of the internal electrode layer 30 as the measurement target region is set as the above-mentioned analysis target range a, and SEM observation is performed. In addition, when the first internal electrode layer 31 is exposed, first, a portion of the first region A1 and the second region A2 of the first internal electrode layer 31 are set as the above-mentioned analysis target range a, and SEM observation is performed. Then, the second internal electrode layer 32 is exposed by FIB (focused ion beam) processing. Then, a portion of the third region A3 and the fourth region A4 of the second internal electrode layer 32 are set as the above-mentioned analysis target range a, and SEM observation is performed. In addition, the SEM observation of the first internal electrode layer 31 may be performed after the SEM observation of the second internal electrode layer 32 is performed.

[0157] Then, the region of the internal electrode layer 30 in the analysis target range a is identified by analyzing the SEM image. Then, based on the area of ​​the analysis target range a and the area of ​​the region of the internal electrode layer 30 , the coverage of the dielectric layer 20 by the internal electrode layer 30 is calculated by the following formula (2).

[0158] Coverage rate (%) = (area of ​​internal electrode layer / area of ​​analysis target range) × 100… (2)

[0159] The coverage of the dielectric layer 20 by the internal electrode layer 30 was calculated for the 12 analysis target areas constituting the measurement target area, and the average value thereof was taken as the coverage of the dielectric layer 20 by the internal electrode layer 30 in the present embodiment.

[0160] Next, a method for manufacturing the multilayer ceramic capacitor 1 of the present embodiment will be described. Note that the method for manufacturing the multilayer ceramic capacitor 1 of the present embodiment is not limited as long as the above-mentioned requirements are satisfied.

[0161] A dielectric sheet for the dielectric layer 20 and a conductive paste for the internal electrode layer 30 are prepared. The dielectric sheet and the conductive paste for the internal electrode contain a binder and a solvent. The binder and the solvent may be known binders and solvents.

[0162] On the dielectric sheet, a conductive paste for the internal electrode layer 30 is printed in a predetermined pattern by, for example, screen printing or gravure printing. Thus, a dielectric sheet having a pattern of the first internal electrode layer 31 and a dielectric sheet having a pattern of the second internal electrode layer 32 are prepared.

[0163] A predetermined number of dielectric sheets without the pattern of the internal electrode layer printed thereon are stacked to form a portion of the first main surface side outer layer portion 12 on the first main surface TS1 side. A dielectric sheet with the pattern of the first internal electrode layer 31 printed thereon and a dielectric sheet with the pattern of the second internal electrode layer 32 printed thereon are stacked in sequence to form a portion of the inner layer portion 11. A predetermined number of dielectric sheets without the pattern of the internal electrode layer printed thereon are stacked to form a portion of the second main surface side outer layer portion 13 on the second main surface TS2 side. In this way, a laminated sheet is produced.

[0164] The laminated sheets are pressed in the height direction by isostatic pressing or the like, thereby producing a laminated block.

[0165] The stacked block is cut into a given size to thereby cut out stacked small pieces. At this time, the corners and ridges of the stacked small pieces may be rounded by barrel grinding or the like.

[0166] The stacked small pieces are fired to produce the stacked body 10. The firing temperature depends on the materials of the dielectric layer 20 and the internal electrode layer 30, but is preferably 900°C or higher and 1400°C or lower.

[0167] Here, the above-mentioned manufacturing conditions may be adjusted so that the area-equivalent diameter D99 of the hole H present in the internal electrode layer 30 is less than or equal to a given value, or so that it falls within a given range.

[0168] Specifically, the pressure, temperature, and pressing time when stacking dielectric sheets printed with the pattern of the internal electrode layer 30 are adjusted so that the area-equivalent diameter D99 of the hole H present in the internal electrode layer 30 becomes less than a given value. For example, when the internal electrode layer 30 is relatively thin, the pressure when pressing the stacked sheets is set high.

[0169] In addition, in order to make the area equivalent diameter D99 of the hole H present in the internal electrode layer 30 below a given value, the material of the conductive paste for the internal electrode layer 30 may be adjusted. For example, when the main component of the internal electrode layer 30 is Ni, Ni particles with a large average particle size are used as the raw material of the conductive paste, so that the bonding start temperature of the Ni particles and the sintering shrinkage start temperature of the ceramic can be close. As a result, the spheroidization of the internal electrode layer 30 can be suppressed, and the area equivalent diameter D99 can be adjusted to be below a given value. In addition, when the same ceramic powder as the ceramic powder contained in the dielectric layer 20 is added as a common material to the conductive paste for the internal electrode layer 30, by using a common material with a large average particle size, the bonding start temperature of the Ni particles and the sintering shrinkage start temperature of the ceramic can be close. As a result, the spheroidization of the internal electrode layer 30 can be suppressed, and the area equivalent diameter D99 can be adjusted to be below a given value. Furthermore, the dispersibility of the common material can be improved by controlling the affinity between the Ni particles, the common material, and the solvent of the conductive paste for the internal electrode layer 30. Thus, the spheroidization of the internal electrode layer 30 can be suppressed, and the area equivalent diameter D99 of the hole H can be adjusted to be less than a given value.

[0170] In addition, when the stacked small pieces are fired, the stacked small pieces may be densely arranged, thereby improving the uniformity of the temperature inside the small pieces during firing. As a result, the spheroidization of the internal electrode layer 30 can be suppressed, and the area equivalent diameter D99 can be adjusted to be below a given value. In addition, the stacked small pieces may be fired while being buried in the ceramic powder, thereby improving the uniformity of the temperature inside and outside the small pieces during firing. As a result, the spheroidization of the internal electrode layer 30 can be suppressed, and the area equivalent diameter D99 can be adjusted to be below a given value. In addition, during firing, the temperature of the portion of the stacked small pieces close to the first side surface and the second side surface (for example, the edge on the first side surface WS1 side of the internal electrode layer 30 and the edge on the second side surface WS2 side of the internal electrode layer 30) tends to rise. Therefore, the spheroidization of the internal electrode layer 30 tends to occur in this portion. However, by the above method, spheroidization of the first to fourth regions A1 to A4 of the internal electrode layer 30 can be suppressed, and the area-equivalent diameter D99 of the holes H present in the internal electrode layer 30 can be made smaller than a given value.

[0171] In addition, the internal electrode layer 30 may be formed by two-step printing, thereby forming the internal electrode layer 30 so that the area equivalent diameter D99 of the hole H existing at least in the portion close to the first side surface and the second side surface of the stacked small piece (for example, the first region A1 to the fourth region A4) becomes less than a given value. In this case, a conductive paste containing Ni particles with a large average particle size and a common material with a large average particle size is printed at least in the first region A1 to the fourth region A4. Moreover, a conductive paste containing Ni particles with a relatively small average particle size and a common material with a relatively small average particle size is printed in other regions including the central region of the internal electrode layer 30. As a result, at least for the hole H existing in the first region A1 to the fourth region A4, its area equivalent diameter D99 can be less than a given value.

[0172] In addition, the above-mentioned method of making the area equivalent diameter D99 of the hole H present in the internal electrode layer 30 less than a given value can be appropriately combined. Thus, the area equivalent diameter D99 of the hole H present in the internal electrode layer 30 can be adjusted to less than a given value, or can be adjusted to within a given range. Similarly, by the above-mentioned method, the area equivalent diameter D90 of the hole H present in the internal electrode layer 30 can be adjusted to less than a given value, or can be adjusted to within a given range.

[0173] A conductive paste that becomes a base electrode layer (a first base electrode layer 50A and a second base electrode layer 50B) is applied to both end surfaces of the laminate 10. In the present embodiment, the base electrode layer is a sintered layer. The conductive paste containing a glass component and a metal is applied to the laminate 10 by, for example, a dipping method. Then, a sintering treatment is performed to form the base electrode layer. The temperature of the sintering treatment at this time is preferably 700° C. or higher and 900° C. or lower.

[0174] In addition, when the stacked small pieces before firing and the conductive paste applied to the stacked small pieces are fired at the same time, the sintered layer is preferably formed by firing a paste to which a ceramic material is added instead of a glass component. At this time, as the added ceramic material, it is particularly preferred to use a ceramic material of the same type as the dielectric layer 20. In this case, the conductive paste is applied to the stacked small pieces before firing, and the stacked small pieces and the conductive paste applied to the stacked small pieces are fired at the same time, thereby forming a stacked body 10, which forms a sintered layer.

[0175] Then, a plating layer is formed on the surface of the base electrode layer. In the present embodiment, a first plating layer 60A is formed on the surface of the first base electrode layer 50A. In addition, a second plating layer 60B is formed on the surface of the second base electrode layer 50B. In the present embodiment, a Ni plating layer and a Sn plating layer are formed as plating layers. When performing the plating process, either electrolytic plating or electroless plating can be used. However, with respect to electroless plating, in order to increase the deposition rate of the plating layer, it is necessary to perform pretreatment using a catalyst, etc., so there is a disadvantage that the process is complicated. Therefore, it is generally preferred to use electrolytic plating. The Ni plating layer and the Sn plating layer are formed in sequence, for example, by roller plating.

[0176] In addition, when the base electrode layer is formed by a thin film layer, a thin film layer as the base electrode layer is formed at a portion where an external electrode is to be formed by performing mask setting, etc. The thin film layer is formed by a thin film forming method such as sputtering or evaporation. The thin film layer is a layer of 1.0 μm or less in which metal particles are deposited.

[0177] In addition, when a conductive resin layer is provided as a base electrode layer, the conductive resin layer may be configured to cover the sintered layer, or may be directly provided on the laminate 10 without providing the sintered layer. When a conductive resin layer is provided, a conductive resin paste containing a thermosetting resin and a metal component is applied on the sintered layer or the laminate 10, and then heat-treated at a temperature of 250 to 550° C. or higher. Thus, the thermosetting resin is heat-cured to form a conductive resin layer. The atmosphere during the heat treatment is preferably an N2 atmosphere. In addition, in order to prevent the scattering of the resin and the oxidation of various metal components, the oxygen concentration is preferably 100 ppm or less.

[0178] In addition, the plating layer may be directly arranged on the exposed portion of the internal electrode layer 30 of the stack 10 without providing the base electrode layer. In this case, the plating process is implemented on the first end face LS1 and the second end face LS2 of the stack 10 to form the plating layer on the exposed portion of the internal electrode layer 30. When the plating process is performed, any one of electrolytic plating and electroless plating can be adopted. However, regarding electroless plating, in order to increase the deposition speed of the plating layer, it is necessary to perform pretreatment using a catalyst, etc., so there is a disadvantage that the process is complicated. Therefore, electrolytic plating is usually preferably adopted. As a plating method, drum plating is preferably adopted. In addition, an upper plating layer can also be formed by the same method as the lower plating layer as needed, and the upper plating layer is formed on the surface of the lower plating layer.

[0179] Through such manufacturing steps, the multilayer ceramic capacitor 1 can be manufactured.

[0180] Furthermore, the multilayer ceramic capacitor 1 may be a two-terminal multilayer ceramic capacitor having two external electrodes, or may be a multi-terminal multilayer ceramic capacitor having a plurality of external electrodes.

[0181] According to the multilayer ceramic capacitor 1 of the present embodiment, the following effects are achieved.

[0182] (1) A multilayer ceramic capacitor 1 according to the present embodiment comprises: a multilayer body 10 having a plurality of laminated dielectric layers 20 and a plurality of internal electrode layers 30 laminated on the dielectric layers 20, and having a first main surface TS1 and a second main surface TS2 opposing each other in a height direction, a first side surface WS1 and a second side surface WS2 opposing each other in a width direction perpendicular to the height direction, and a first end surface LS1 and a second end surface LS2 opposing each other in a length direction perpendicular to the height direction and the width direction; and a first external electrode 40A and a second external electrode 40B, wherein the plurality of internal electrode layers 30 have: a plurality of first main surfaces TS1 and a second main surface TS2 opposing each other in a height direction, a first side surface WS1 and a second side surface WS2 opposing each other in a width direction perpendicular to the height direction, and a first end surface LS1 and a second end surface LS2 opposing each other in a length direction perpendicular to the height direction and the width direction. The internal electrode layer 31 is electrically connected to the first external electrode 40A; and the plurality of second internal electrode layers 32 are electrically connected to the second external electrode 40B. There are a plurality of holes H having different area equivalent diameters in the first internal electrode layer 31 and the second internal electrode layer 32. When the area equivalent diameter at which the cumulative value of the cumulative distribution of the area equivalent diameters of the plurality of holes H becomes 99% is set as the area equivalent diameter D99, and the thickness of the dielectric layer 20 sandwiched between the first internal electrode layer 31 and the second internal electrode layer 32 is set as the thickness t, the thickness t of the dielectric layer 20 is greater than 0.5 μm, and the following formula (1) is also satisfied.

[0183] (area equivalent diameter D99) < 0.0879 × exp (2.86 × t) ... (1)

[0184] Thus, a multilayer ceramic capacitor capable of suppressing electric field concentration can be provided.

[0185] (2) In the multilayer ceramic capacitor 1 of the present embodiment, the thickness t of the dielectric layer 20 is 1.4 μm or less. Therefore, even when the thickness t of the dielectric layer 20 is 1.4 μm or less, electric field concentration can be suppressed.

[0186] (3) In the multilayer ceramic capacitor 1 of the present embodiment, the thickness t of the dielectric layer 20 is 1.0 μm or less. Therefore, even when the thickness t of the dielectric layer 20 is 1.0 μm or less, electric field concentration can be suppressed.

[0187] (4) In the multilayer ceramic capacitor 1 of the present embodiment, the thickness t of the dielectric layer 20 is 0.75 μm or more. Thus, even when the thickness of the dielectric layer 20 is 0.75 μm or more, electric field concentration can be suppressed.

[0188] (5) In the multilayer ceramic capacitor 1 of the present embodiment, the area-equivalent diameter D99 of the plurality of holes H present in the first internal electrode layer 31 and the second internal electrode layer 32 is 0.37 μm or more. The 0.37 μm in this case is a value obtained by substituting 0.5 μm as the thickness t of the dielectric layer 20 into the above formula (1).

[0189] (6) In the multilayer ceramic capacitor 1 of the present embodiment, the area-equivalent diameter D99 of the plurality of holes H present in the first internal electrode layer 31 and the second internal electrode layer 32 is 0.75 μm or more. The 0.75 μm in this case is a value obtained by substituting 0.75 μm as the thickness t of the dielectric layer 20 into the above formula (1).

[0190] (7) In the multilayer ceramic capacitor 1 of the present embodiment, the area-equivalent diameter D99 of the plurality of holes H present in the first internal electrode layer 31 and the second internal electrode layer 32 is 4.8 μm or less. The 4.8 μm in this case is a value obtained by substituting 1.4 μm as the thickness t of the dielectric layer 20 into the above formula (1).

[0191] (8) In the multilayer ceramic capacitor 1 of the present embodiment, the coverage of the dielectric layer 20 by the internal electrode layer 30 is 70% to 99%. This can suppress a decrease in capacitance and electric field concentration when voltage is applied.

[0192] (9) In the multilayer ceramic capacitor 1 of the present embodiment, the coverage of the dielectric layer 20 by the internal electrode layer 30 may be 81% to 93%, or 86% to 93%. This can suppress a decrease in capacitance and suppress electric field concentration when a voltage is applied.

[0193] (10) The external electrode 40 of the multilayer ceramic capacitor 1 of the present embodiment includes: a first external electrode 40A, which is arranged on the first end surface LS1 side; and a second external electrode 40B, which is arranged on the second end surface LS2 side. The plurality of internal electrode layers 30 include: a plurality of first internal electrode layers 31, which are electrically connected to the first external electrode 40A; and a plurality of second internal electrode layers 32, which are electrically connected to the second external electrode 40B. The first internal electrode layer 31 includes a first edge WE1 on the first side surface WS1 side and a second edge WE2 on the second side surface WS2 side. The second internal electrode layer 32 includes a third edge WE3 on the first side surface WS1 side and a fourth edge WE4 on the second side surface WS2 side. The first internal electrode layer 31 is extended from a position 10 μm away from the first edge WE1 to a position 50 μm away from the first edge WE1. The area at the position of m is set as the first area A1, the area from the position of 10 μm to the position of 50 μm from the second side WE2 is set as the second area A2, the area from the position of 10 μm to the position of 50 μm from the third side WE3 in the second internal electrode layer 32 is set as the third area A3, the area from the position of 10 μm to the position of 50 μm from the fourth side WE4 is set as the fourth area A4, and the set of holes H existing in the first area A1, the second area A2, the third area A3 and the fourth area A4 is set as the parent set of holes H. At this time, the area equivalent diameter D99 is the area equivalent diameter at which the cumulative value of the cumulative distribution of the area equivalent diameters of the holes H in the parent set of holes H becomes 99%. Thus, it is possible to provide a laminated ceramic capacitor with high reliability while suppressing electric field concentration.

[0194] (11) The multilayer ceramic capacitor 1 of the present embodiment comprises: a multilayer body 10 having a plurality of stacked dielectric layers 20 and a plurality of internal electrode layers 30 stacked on the dielectric layers 20, and having a first main surface TS1 and a second main surface TS2 opposite to each other in the height direction, a first side surface WS1 and a second side surface WS2 opposite to each other in the width direction perpendicular to the height direction, and a first end surface LS1 and a second end surface LS2 opposite to each other in the length direction perpendicular to the height direction and the width direction; and an external electrode 40 connected to the internal electrode layer 30 and having an area of ​​about 100 mm on the internal electrode layer 30. The outer electrode 40 comprises: a first outer electrode 40A, which is arranged on the first end face LS1 side; and a second outer electrode 40B, which is arranged on the second end face LS2 side; the inner electrode layers 30 comprise: a plurality of first inner electrode layers 31, which are electrically connected to the first outer electrode 40A; and a plurality of second inner electrode layers 32, which are electrically connected to the second outer electrode 40B; the first inner electrode layer 31 comprises a first side WE1 on the first side face WS1 side and a second side WE2 on the second side face WS2 side; the second inner electrode layer 32 comprises a third side WE 3 and the fourth side WE4 on the second side WS2 side, the area from the position of 10 μm away from the first side WE1 to the position of 50 μm away from the first side WE1 in the first internal electrode layer 31 is set as the first area A1, the area from the position of 10 μm away from the second side WE2 to the position of 50 μm away from the second side WE2 is set as the second area A2, the area from the position of 10 μm away from the third side WE3 to the position of 50 μm away from the third side WE3 in the second internal electrode layer 32 is set as the third area A3, and the area from the position of 10 μm away from the fourth side WE4 is set as the third area A4. The area extending to a position 50 μm away from the fourth edge WE4 is set as the fourth area A4, the set of holes H existing in the first area A1, the second area A2, the third area A3 and the fourth area A4 is set as the parent set of holes H, the area equivalent diameter at which the cumulative value of the cumulative distribution of the area equivalent diameters of the holes H in the parent set of holes H becomes 99% is set as the area equivalent diameter D99, and the thickness of the dielectric layer 20 sandwiched between the first internal electrode layer 31 and the second internal electrode layer 32 is set to thickness t. At this time, the thickness t of the dielectric layer 20 is greater than 0.5 μm and also satisfies the following formula (1).

[0195] (area equivalent diameter D99) < 0.0879 × exp (2.86 × t) ... (1)

[0196] Thus, it is possible to provide a highly reliable multilayer ceramic capacitor that suppresses electric field concentration.

[0197] The present invention is not limited to the configuration of the above-described embodiment, and can be applied with appropriate changes within the scope of the present invention. In addition, a configuration combining two or more of the preferred configurations described in the above-described embodiment is also the present invention.

[0198] Description of Reference Numerals

[0199] 1: Multilayer ceramic capacitor;

[0200] 10: laminate;

[0201] 20: dielectric layer;

[0202] 30: internal electrode layer;

[0203] 31: first internal electrode layer;

[0204] 32: second internal electrode layer;

[0205] 40: external electrode;

[0206] 40A: 1st external electrode;

[0207] 40B: second external electrode;

[0208] H: hole;

[0209] L: length direction;

[0210] W: width direction;

[0211] T: height direction;

[0212] LS1: 1st end face;

[0213] LS2: 2nd end face;

[0214] WS1: side 1;

[0215] WS2: side 2;

[0216] TS1: 1st main surface;

[0217] TS2: The second main side.

Claims

1. A multilayer ceramic capacitor comprising: A laminate having a plurality of laminated dielectric layers and a plurality of internal electrode layers laminated on the dielectric layers, and having a first main surface and a second main surface opposite to each other in a height direction, a first side surface and a second side surface opposite to each other in a width direction perpendicular to the height direction, and a first end surface and a second end surface opposite to each other in a length direction perpendicular to the height direction and the width direction; and a first external electrode and a second external electrode, The plurality of internal electrode layers have: a plurality of first internal electrode layers electrically connected to the first external electrode; and a plurality of second internal electrode layers electrically connected to the second external electrode; The first internal electrode layer and the second internal electrode layer have a plurality of holes having different area equivalent diameters. When the area equivalent diameter at which the cumulative value of the cumulative distribution of the area equivalent diameters of the plurality of holes becomes 99% is set as the area equivalent diameter D99, and the thickness of the dielectric layer sandwiched between the first internal electrode layer and the second internal electrode layer is set as the thickness t, the thickness t of the dielectric layer is 0.5 μm or more, and the following formula (1) is satisfied, (area equivalent diameter D99) < 0.0879 × exp (2.86 × t)… (1).

2. The multilayer ceramic capacitor according to claim 1, wherein The thickness t of the dielectric layer is less than 1.4 μm.

3. The multilayer ceramic capacitor according to claim 2, wherein: The thickness t of the dielectric layer is 1.0 μm or less.

4. The multilayer ceramic capacitor according to any one of claims 1 to 3, wherein The thickness t of the dielectric layer is greater than 0.75 μm.

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