Integrated circuit including circuitry for matching voltage provided to gate of power transistor

Abstract

The invention relates to an integrated circuit comprising: an enhancement mode power transistor (P2), and an adaptation circuit for providing a voltage to a gate of the enhancement mode power transistor, the adaptation circuit comprising at least one branch (101) connected between an input (INPUT) and a second end (SOURCE) of the integrated circuit, the branch comprises a depletion-mode head transistor (M1), a depletion-mode tail transistor (M2) connected to the first dipole (R1), a connected quadrupole (10), and an enhancement-mode base transistor, the source of which is connected to the second terminal (SOURCE), the gate of which is connected to the drain thereof, the drain of which is connected to the second dipole (15), and the drain of which is connected to the second terminal (SOURCE). The driver circuit is connected to the gate of the power transistor (P2) through the source of the head transistor (M1).

Description

Technical Field

[0001] The present invention relates to the field of power electronics.

[0002] More particularly, the present invention relates to a circuit for regulating the voltage supplied to the gate of a power transistor.

[0003] The invention advantageously makes it possible to control the gate of a power transistor at a higher voltage level than in the prior art without damaging the power transistor. The invention further proposes an adaptation circuit that is more robust and more compact than circuits of the prior art. Background Art

[0004] Power electronics is the branch of electronics dedicated to high-power energy transmission, for which it is important to minimize energy losses. It is mainly based on the use of controlled power switches. For this purpose, a variety of silicon technology switches (IGBT, MOSFET) and wide-bandgap semiconductor elements (SiC, GaN) can be used. The transistor can be controlled by a control circuit called a "driver". This control circuit is intended to control the charging and / or discharging of the gate of the power element in order to be able to change the state of the power transistor.

[0005] Typically, the gate of a transistor is limited to the voltage it can apply without being damaged. Specifically, depending on the GaN transistor model, this voltage can be a maximum of 3V, 6V or 9V.

[0006] The driver itself can provide a voltage between 6 V and 20 V. To adapt the voltage provided by the driver, an adaptation circuit can be inserted between the driver and the gate of the power transistor.

[0007] To do this, you can use Figure 1 The circuit shown is formed by discrete components.

[0008] Typically, the adaptation circuit 200 in the prior art receives a pulse width modulation signal (also called a PWM signal) alternating between a high state and a low state as an input INPUT. The input INPUT is connected to a first interconnection point A1 of the three branches of the adaptation circuit 200.

[0009] The first branch includes a resistor R4 connected in series with the cathode of the Schottky diode D4, and the anode of the Schottky diode D4 is connected to the second interconnection point A2.

[0010] The second branch, which is installed in parallel with the first branch, comprises a resistor R3.

[0011] The third branch comprises, among other things, two Schottky diodes D2, D3. The first Schottky diode D2 is connected to the first interconnection point A1 via its cathode, and the second Schottky diode D3 is connected to the first interconnection point A1 via its anode. The cathode of the second Schottky diode D3 is connected to the capacitor C1 on the one hand and to the cathode of the Zener diode D1 on the other hand, and the capacitor C1 is connected in parallel with the Zener diode D1. The anode of the first diode D2 is connected to the resistor R2, and the other end of the resistor R2 is connected to the ground on the one hand and to the anode of the Zener diode D1 and the second end of the capacitor C1 on the other hand.

[0012] The adaptation circuit 200 supplies power to the gate of the power transistor P2.

[0013] A disadvantage of this circuit is that it comprises a large number of components and therefore occupies a large surface area, which makes it impossible to integrate the circuit in a small space.

[0014] Another solution of the prior art consists in using integrated circuits, such as Figure 2 The integrated circuit in patent US2020 / 0357906 is shown.

[0015] Integrated circuit 300 also receives a pulse width modulated signal as an input. The input is connected to the drain of transistor T1. The gate of transistor T1 is connected to the cathode of Zener diode D7, and the anode of Zener diode D7 is grounded. Resistor R7 is connected between the drain and gate of transistor T1. The source of transistor T1 is connected to the gate of the power transistor whose voltage is to be regulated.

[0016] This circuit is generally referred to as a “clamping circuit.” Due to the presence of the Zener diode D7, the voltage delivered to the gate of a power transistor (not shown in the figure) connected to the access point of the “clamping signal” can be limited.

[0017] Although the circuit is Figure 1 The circuit in the FPGA is more compact, but it is very sensitive to temperature changes and variations in transistor manufacturing parameters (also known as "process corners").

[0018] The technical problem to be solved by the present invention is to provide an adaptation circuit which is more compact than the circuits in the prior art and whose sensitivity to temperature changes and changes in transistor manufacturing parameters is limited. Summary of the invention

[0019] To solve this problem, the applicant has developed an integrated circuit comprising:

[0020] an enhancement mode power transistor having a drain connected to the first terminal of the integrated circuit and a source connected to the second terminal of the integrated circuit, and

[0021] - a circuit for adapting a voltage supplied to a gate of an enhancement mode power transistor, the circuit comprising at least one branch connected between an input adapted to receive a signal capable of adopting a low state and a high state and a second terminal. The branch comprises:

[0022] - a depletion-mode header transistor, the drain of which is connected to the input;

[0023] a depletion tail transistor having a source connected to one end of the first dipole and a gate connected to the second end of the first dipole;

[0024] - a connecting (or linking) quadrupole, a first end of which is connected to the gate of the head transistor, a second end of which is connected to the source of the head transistor, a third end of which is connected to the source of the tail transistor, and a fourth end of which is connected to the drain of the tail transistor, and

[0025] - an enhancement mode base (or leg) transistor having its source connected to the second terminal and its gate connected to its drain, said drain being connected to the second terminal of the second dipole, the first terminal of the second dipole being connected to the second terminal of the first dipole.

[0026] The adaptation circuit is connected to the gate of the power transistor via the source of the head transistor.

[0027] According to the present invention, the signal capable of adopting the low state and the high state is, for example, a pulse width modulated signal.

[0028] and Figure 1 Compared to the prior art, this adaptation circuit has very few components. It is therefore easier to implement in an integrated circuit. Moreover, due to the limited number of components, fewer disturbances appear on the control signal of the power transistor related to the interaction between the components. Moreover, the circuit can be qualified as quasi-passive in the sense that it comprises only one input connected to the driver and an output connected to the gate of the power transistor and it does not require any energy source other than the power supplied by the driver to regulate the voltage.

[0029] Furthermore, it is well known that a depletion mode transistor has a negative threshold voltage, whereas an enhancement mode transistor has a positive threshold voltage.

[0030] By observing the threshold voltages of enhancement-mode and depletion-mode transistors during variations in manufacturing parameters, it is sometimes possible to compensate for the effects of these variations on the performance of circuits using the transistors.

[0031] Thus, in the circuit of the present invention, when the lower and upper portions of the circuit are combined, the enhancement mode transistors can compensate for a pair of depletion mode transistors.

[0032] The direct result is that fluctuations associated with temperature changes and variations in the methods of manufacturing a given transistor are compensated for by the presence of other transistors in the circuit.

[0033] Therefore, the circuit is more robust than prior art circuits.

[0034] According to the first embodiment, the above-mentioned connecting quadrupole is composed of two short circuits respectively connecting the first end and the third end and the second end and the fourth end.

[0035] Advantageously, the second dipole is thus a short circuit.

[0036] This embodiment is the simplest. The circuit comprises only two depletion mode transistors, an enhancement mode transistor and a dipole, a total of four components. Therefore, this circuit is particularly easy to implement and integrate into an integrated circuit.

[0037] The number of enhancement mode transistors and the number of depletion mode transistors are selected based on the maximum voltage that it attempts to apply to the gate of the enhancement mode power transistor.

[0038] Therefore, the adaptation circuit of this first embodiment delivers a maximum voltage of 3V.

[0039] According to the second embodiment, the connecting quadrupole includes two depletion-type transistors: a high-order transistor and a low-order transistor, the source of the high-order transistor is connected to the drain of the low-order transistor and to the first end of the connecting quadrupole, the drain of the high-order transistor is connected to the second end of the connecting quadrupole, the gate of the low-order transistor is connected to the third end of the connecting quadrupole, and the gate of the high-order transistor and the source of the low-order transistor are connected to the fourth end of the connecting quadrupole.

[0040] Advantageously, the second dipole thus comprises an enhancement mode transistor, the source of which is connected to the second end of the second dipole and the gate of which is connected to its drain, which is connected to the first end of the second dipole.

[0041] In this embodiment, the circuit includes two enhancement mode transistors whose threshold voltages are compensated by two pairs of depletion mode transistors.

[0042] The adaptation circuit of this second embodiment therefore delivers a maximum voltage of 6V.

[0043] According to the third embodiment, the connecting quadrupole is composed of n basic quadrupoles, where n>1, and each basic quadrupole includes two depletion-type transistors: a high-order transistor and a low-order transistor, the source of the high-order transistor is connected to the drain of the low-order transistor and to the first end of the basic quadrupole, the drain of the high-order transistor is connected to the second end of the basic quadrupole, the gate of the low-order transistor is connected to the third end of the basic quadrupole, and the gate of the high-order transistor and the source of the low-order transistor are connected to the fourth end of the basic quadrupole; the basic quadrupoles are connected in series, wherein two consecutive basic quadrupoles are connected so that the first end of the basic quadrupole is connected to the third end of the basic quadrupole, and the second end of the basic quadrupole is connected to the fourth end of the basic quadrupole; the first end and the second end of the basic quadrupole form the first end and the second end of the connecting quadrupole, and the third end and the fourth end of the basic quadrupole form the third end and the fourth end of the connecting quadrupole.

[0044] Advantageously, the second dipole thus comprises n enhancement type transistors, each having its gate connected to its drain, said transistors being connected in series, two consecutive transistors being connected via the source of one of them and the drain of the other, and wherein the drain of the first transistor forms the first end of the second dipole and the source of the last transistor forms the second end of the second dipole.

[0045] According to an embodiment, the first dipole can be, for example, an enhancement mode transistor, whose gate is connected to its drain. Thus, the transistor behaves similarly to a diode. Preferably, the first dipole is a resistor, which can better compensate for variations within the circuit. In principle, the size of the transistor or the resistance value of the resistor has no significant influence on the voltage reference value. However, the size of these elements can be adapted to limit the energy consumption of the adaptation circuit.

[0046] Therefore, the adaptation circuit of this third embodiment delivers a maximum voltage of 3V times n.

[0047] In order to increase the value of the current delivered to the power transistor, several branches such as those described above can be connected in parallel.

[0048] The adaptation circuit thus comprises m branches connected in parallel, each branch being connected to the gate of the power transistor via the source of its head transistor. The available current at the output is thus increased by a ratio of m while maintaining the performance of the original branches. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] The manner of implementing the present invention and the advantageous effects produced thereby will be apparent from the following description of embodiments supported by the accompanying drawings, in which:

[0050] Figure 1 An electrical diagram of a prior art adaptation circuit including separate components;

[0051] Figure 2 An electrical diagram of another prior art adaptation circuit that can be implemented in an integrated circuit;

[0052] Figure 3 is an electrical diagram of an adaptation circuit according to a first embodiment of the present invention;

[0053] Figure 4 for Figure 3 An electrical diagram of a variant embodiment;

[0054] Figure 5 is an electrical diagram of an adaptation circuit according to a second embodiment of the present invention;

[0055] Figure 6 is an electrical diagram of an adaptation circuit according to a third embodiment of the present invention;

[0056] Figure 7 is an electrical diagram of an adaptation circuit according to a fourth embodiment of the present invention;

[0057] Figure 8 is an electrical diagram of an adaptation circuit according to a fifth embodiment of the present invention;

[0058] Fig. 9 is an electrical diagram of an adaptation circuit according to a sixth embodiment of the present invention;

[0059] Fig.10 A comparison diagram between input signals and output signals of the circuit of the present invention for different transistors with manufacturing process variations;

[0060] Fig.11 FIG. 1 is a graph showing how the amplitude of a signal supplied to a gate of a power transistor behaves according to an input voltage under three process corner conditions. DETAILED DESCRIPTION

[0061] Such as Figures 3 to 9 As shown, the integrated circuit of the present invention includes an adaptation circuit connected to the gates of the enhanced power transistors P2-P8. The integrated circuit has three terminals: an input terminal INPUT, a first terminal DRAIN connected to the drains of the enhanced power transistors P2-P8, and a second terminal SOURCE connected to the sources of the enhanced power transistors P2-P8.

[0062] The adaptation circuit comprises at least one branch 101-108. Each branch comprises a head transistor M1, M11, M21, M31, M41, M51, M61, M71, the drain of which is connected to an input terminal INPUT intended to receive a pulse width modulated signal alternating between a high state and a low state. For example, this signal can be provided by a control circuit or "driver". For example, the input signal INPUT can adopt a high state between 8V and 12V, and a low state equal to 0V.

[0063] Sources of the header transistors M1 , M11 , M21 , M31 , M41 , M51 , M61 , and M71 are connected to gates of the enhancement mode power transistors P2 - P8 .

[0064] Each branch 101-108 in the adaptation circuit of the present invention may further include tail transistors M2, M14, M26, M36, M44, M54, M64, M74.

[0065] The two head transistors M1, M11, M21, M31, M41, M51, M61, M71 and the tail transistors M2, M14, M26, M36, M44, M54, M64, M74 are connected to each other via the connecting quadrupoles 10, 20, 30, 40.

[0066] exist Figure 3 and Figure 4 In the first embodiment, the connection quadrupole 10 corresponds to two short circuits. The first short circuit is connected to the Q1 terminal and the Q3 terminal of the connection quadrupole 10 ; the second short circuit is connected to the Q2 terminal and the Q4 terminal of the connection quadrupole 10 .

[0067] Therefore, the head transistor M1 is connected to the drain of the tail transistor M2 through its source through the short circuit connecting the Q2 terminal and the Q4 terminal. In addition, the source of the tail transistor M2 is connected to the gate of the head transistor M1 through the short circuit connecting the Q1 terminal and the Q3 terminal.

[0068] exist Figure 5 In the second embodiment, the connection quadrupole 20 includes two depletion-type transistors M12 and M13 connected in series: a high-order transistor M12 and a low-order transistor M13. The source of the high-order transistor M12 is connected to the drain of the low-order transistor M13, and is connected to the first end Q1 of the connection quadrupole 20. The first end Q1 is also connected to the gate of the head transistor M11. The drain of the high-order transistor M12 is connected to the second end Q2 of the connection quadrupole 20. The second end Q2 is also connected to the source of the head transistor M11. The gate of the low-order transistor M13 is connected to the third end Q3 of the connection quadrupole 20. The third end Q3 is also connected to the source of the tail transistor M14. Finally, the gate of the high-order transistor M12 and the source of the low-order transistor M13 are connected to the fourth end Q4 of the connection quadrupole 20, and the source of the low-order transistor M13 is also connected to the drain of the tail transistor M14.

[0069] exist Figure 7In the fourth embodiment, the connecting quadrupole 30 is composed of two basic quadrupoles QEi, QEi+1 connected in series, that is, the third terminal QEi-3 of the first basic quadrupole QEi is connected to the first terminal QEi+1-1 of the second basic quadrupole QEi+1, and the fourth terminal QEi-4 of the first basic quadrupole QEi is connected to the second terminal QEi+1-2 of the second basic quadrupole QEi+1. Each basic quadrupole QEi, QEi+1 includes two depletion transistors M32-M35: high-order transistors M32, M34 and low-order transistors M33, M35. The source of each high-order transistor M32, M34 is connected to the drain of each low-order transistor M33, M35, and is connected to the first terminal QEi-1, QEi+1-1 of each basic quadrupole QEi, QEi+1. The drain of each high-order transistor M32, M34 is connected to the second terminal QEi-2, QEi+1-2 of each basic quadrupole QEi, QEi+1; the gate of each low-order transistor M33, M35 is connected to the third terminal QEi-3, QEi+1-3 of each basic quadrupole QEi, QEi+1; the gate of each high-order transistor M32, M34 and the source of each low-order transistor M33, M35 are connected to the fourth terminal QEi-4, QEi+1-4 of each basic quadrupole QEi, QEi+1. The terminals QEi-1 and QEi-2 respectively form the terminals Q1 and Q2 connected to the quadrupole 30; the terminals QEi+1-3 and QEi+1-4 respectively form the terminals Q3 and Q4 connected to the quadrupole 30.

[0070] exist Figure 6 In the third embodiment, the connection quadrupole 40 is composed of n basic quadrupoles QE1-QEn, where n>1. Each basic quadrupole includes two depletion-type transistors: a high-order transistor M22, M24 and a low-order transistor M23, M25; Figure 5 The basic quadrupoles QEi and QEi+1 described in the specification are connected in the same manner. The basic quadrupoles QE1-QEn are connected in series, and two consecutive basic quadrupoles QEi and QEi+1 are connected so that the first end QEi+1-1 of the basic quadrupole QEi+1 is connected to the third end QEi-3 of the basic quadrupole QEi, and the second end QEi+1-2 of the basic quadrupole QEi+1 is connected to the fourth end QEi-4 of the basic quadrupole QEi. The first end QE1-1 and the second end QE1-2 of the basic quadrupole QE1 form the first end Q1 and the second end Q2 of the connection quadrupole 40; the third end QEn-3 and the fourth end QEn-4 of the basic quadrupole QEn form the third end Q3 and the fourth end Q4 of the connection quadrupole 40.

[0071] The head transistor and the tail transistor are depletion mode transistors. They can belong to the category of GaN transistors or MOS transistors.

[0072] The tail transistors M2, M14, M26, M36, M44, M54, M64, M74 are connected to one end of the first dipole via their sources. The gates of the tail transistors M2, M14, M26, M36, M44, M54, M64, M74 are connected to the second end of the first dipole. The first dipole may be, for example, Figure 3 and Figure 5-Figure 9 The resistors R1, R11, R21, R31, R41, R51, R61, R71 shown in FIG. 1 may also be diodes. For example, the first dipole is an enhancement transistor M4 installed as a diode, i.e., such as Figure 4 As shown in , its gate is connected to its drain.

[0073] The second end of the first dipole is connected in series with the second dipole 15 , 25 , 35 , 45 .

[0074] exist Figure 3 and Figure 4 In the first embodiment, the second dipole 15 corresponds to a short circuit.

[0075] exist Figure 5 In the second embodiment, the second dipole 25 comprises an enhancement mode transistor M15 , whose source is connected to the second end of the second dipole 25 , whose gate is connected to the drain, and whose drain is also connected to the first end of the second dipole 25 .

[0076] exist Figure 7 In the fourth embodiment, the second dipole 35 includes two enhancement mode transistors M37 and M38. The gate of each transistor M37 and M38 is connected to its drain. The transistors M37 and M38 are connected in series, that is, the source of the first transistor M37 is connected to the drain of the second transistor M38. Therefore, the drain of the first transistor M37 forms the first end A3 of the second dipole 45, and the source of the second transistor M38 forms the second end A4 of the second dipole 45.

[0077] exist Figure 6 In the third embodiment shown, the second dipole 35 includes n enhancement mode transistors M27, M28. The gate of each transistor M27, M28 is connected to its drain. The transistors M27, M28 are connected in series, i.e. two consecutive transistors M27, M28 are connected via the source of one and the drain of the other. Therefore, the drain of the first transistor M27 forms the first end A3 of the second dipole 35, and the source of the last transistor M28 forms the second end A4 of the second dipole 35.

[0078] The second end of the second dipole 15, 25, 35, 45 is connected to a non-linear element. In practice, the non-linear element is a base transistor M3, M16, M29, M39. The base transistor M3, M29, M39 is advantageously an enhancement transistor, the gate of which is connected to its drain. The base transistor M3, M29, M39, M46, M56, M66, M76 is connected via its source to a second end SOURCE, which is usually grounded.

[0079] The maximum voltage value provided to the gates of the power transistors P2-P8 is determined by the number of enhancement mode transistors M3, M15, M16, M27-M29, M37-M39, M45, M46, M55, and M56 of the circuit.

[0080] Thus, the first embodiment comprises a single enhancement transistor M3 and makes it possible to limit the voltage supplied to the gate of the power transistor P2 to a value substantially equal to 3 V. The second embodiment comprises two enhancement transistors M15, M16 and makes it possible to limit the voltage supplied to the gate of the power transistor P4 to a value substantially equal to 6 V. The fourth embodiment comprises three enhancement transistors M37-M39 and makes it possible to limit the voltage supplied to the gate of the power transistor P6 to a value substantially equal to 9 V. The third embodiment comprises n enhancement transistors M37-M39 and makes it possible to limit the voltage supplied to the gate of the power transistor P5 to a value substantially equal to n times 3 V.

[0081] according to Figure 8 and Fig. 9 In the fifth and sixth embodiments shown, two identical branches 101-108 can be installed in parallel to increase the current of the signal provided to the gates of the power transistors P2-P8 while maintaining the same voltage. Therefore, the fifth and sixth embodiments include two branches 105-108, each branch including two enhancement transistors M45, M46, M65, M66, and make it possible to limit the voltage provided to the gates of the power transistors P7, P8 to a value substantially equal to 6V.

[0082] Therefore, in the case where the circuit includes only a single branch, the current circulating in the circuit from the input INPUT to the gates of the enhancement mode power transistors P2-P8 is approximately 1A.

[0083] When several branches are connected in parallel, the current can reach several amperes. Therefore, the present invention can be well adapted to a wide range of power transistors.

[0084] For this reason, Figure 8As shown, branches 105 and 106 are connected in parallel between the input INPUT and the second terminal SOURCE. Branch 105 is connected to branch 106 via the source of its head transistor M41, which is connected to the source of the head transistor M51 of branch 106. Therefore, the sources of the two head transistors M41 and M51 are connected to the gate of the power transistor P7.

[0085] In such Fig. 9 In the variant shown, the lower part of the adaptation circuit comprising the enhancement transistors M75, M76 can be brought together. Thus, the branches 105 and 106 are connected in parallel between the input INPUT and the second end of the first dipole R71.

[0086] Thus, an adaptation circuit is obtained which is not very sensitive to fluctuations in supply voltage, temperature and variations in transistor manufacturing methods.

[0087] In fact, the applicant has conducted digital simulations and the results are as follows Fig.10 and Fig.11 As shown. Thus, for an input signal 120 having a high state equal to 12V and a low state equal to 0V, the signal provided to the gates of the power transistors P2-P8 varies very little according to the transistor manufacturing process. In the worst case, i.e. for slow-slow (SS) transistors, the signal 140 has a slight delay that is added, but it remains absolutely satisfactory. For all other combinations of transistors, the signal 130 is faithfully reproduced and has a low state of 0V, and a high state of 6V.

[0088] Fig.11 The behavior of the signal (reference V(V)) supplied to the gate of the power transistor as a function of the input voltage INPUT (reference VDC) is shown, obtained by means of the process corners traditionally used in digital simulations to check the behavior of the circuit by taking into account the variations associated with the manufacturing method. Thus, the curves FF and SS correspond to the simulations at the two extreme "corners" of the "process corner", namely fast-fast and slow-slow, and the curve TT corresponds to the simulation of nominal or typical conditions. It is therefore noteworthy that the voltage V(V) remains substantially constant under the conditions in question.

Claims

1. An integrated circuit, comprising: - an enhanced power transistor (P2-P8), wherein the drain of the enhanced power transistor is connected to the first terminal (DRAIN) of the integrated circuit, and the source of the enhanced power transistor is connected to the second terminal (SOURCE) of the integrated circuit; - an adaptation circuit for the voltage supplied to the gate of the enhancement mode power transistor (P2-P8), the adaptation circuit comprising at least one branch (100-108) connected between an input (INPUT) suitable for receiving a signal capable of adopting a low state and a high state and a second terminal (SOURCE); the at least one branch (100-108) comprising: - a depletion-type header transistor (M1, M11, M21, M31, M41, M51, M61, M71), the drain of which is connected to the input (INPUT); a depletion tail transistor (M2, M14, M24, M34, M46, M56), wherein a source of the depletion tail transistor is connected to one end of the first dipole (R1, R11, R21, M4), and a gate of the depletion tail transistor is connected to a second end of the first dipole (R1, R11, R21, R31, R41, R51, R61, R71, M4); - a connecting quadrupole (10, 20, 30, 40), wherein a first end (Q1) of the connecting quadrupole is connected to a gate of a head transistor (M1, M11, M21, M31, M41, M51, M61, M71), a second end (Q2) of the connecting quadrupole is connected to a source of a head transistor (M1, M11, M21, M31, M41, M51, M61, M71), a third end (Q3) of the connecting quadrupole is connected to a source of a tail transistor (M2, M14, M26, M36, M44, M54, M64, M74), a fourth end (Q4) of the connecting quadrupole is connected to a drain of a tail transistor (M2, M14, M26, M36, M44, M54, M64, M74), and - an enhanced base transistor (M3, M16, M29, M39, M46, M56, M76), the source of the enhanced base transistor being connected to the second end (SOURCE), the gate of the enhanced base transistor being connected to its drain, the drain being connected to the second end (A4) of the second dipole (15, 25, 35), the first end (A3) of the second dipole being connected to the second end of the first dipole (R1, R11, R21, R31, R41, R51, R61, R71, M4); The adaptation circuit is connected to the gate of the power transistor (P2-P8) via the source of the head transistor (M1, M11, M21, M31, M41, M51, M61, M71).

2. The integrated circuit according to claim 1, characterized in that The connecting quadrupole (10) is composed of two short circuits, which are respectively connected to the first end (Q1) and the third end (Q3), and the second end (Q2) and the fourth end (Q4).

3. The integrated circuit according to claim 1, characterized in that The connecting quadrupole (20) comprises two depletion-type transistors (M12, M13, M42, M52, M43, M53, M62, M63, M72, M73): a high-order transistor (M12, M42, M52, M62, M72) and a low-order transistor (M13, M43, M53, M63, M73), wherein the source of the high-order transistor (M12, M42, M52, M62, M72) is connected to the drain of the low-order transistor (M13, M43, M53, M63, M73), and is connected to the drain of the connecting quadrupole (20). The first end (Q1) is connected, the drain of the high-order transistor (M12, M42, M52, M62, M72) is connected to the second end (Q2) connected to the quadrupole (20), the gate of the low-order transistor (M13, M43, M53, M63, M73) is connected to the third end (Q3) connected to the quadrupole (20), and the gate of the high-order transistor (M12, M42, M52, M62, M72) and the source of the low-order transistor (M13, M43, M53, M63, M73) are connected to the fourth end (Q4) connected to the quadrupole (20).

4. The integrated circuit according to claim 1, characterized in that The connecting quadrupole (40) is composed of n basic quadrupoles (QE1, QEi, QEi+1, QEn), wherein n>1, each basic quadrupole (QEi) includes two depletion-type transistors: a high-order transistor (M42, M52, M44, M54) and a low-order transistor (M23, M33, M25, M35), the source of the high-order transistor (M22, M24) is connected to the source of the low-order transistor (M23, The drain of the high-order transistors (M22 and M24) is connected to the second end (QEi-2) of the basic quadrupole (QEi), the gate of the low-order transistors (M23 and M25) is connected to the third end (QEi-3) of the basic quadrupole (QEi), and the gate of the high-order transistors (M22 and M24) is connected to the gate of the low-order transistors (M23 and M25). 23, M25) is connected to the fourth end (QEi-4) of the basic quadrupole (QEi); the basic quadrupoles are connected in series, and two consecutive basic quadrupoles (QEi, QEi+1) are connected so that the first end (QEi+1-1) of the basic quadrupole (QEi+1) is connected to the third end (QEi-3) of the basic quadrupole (QEi), and the second end (QEi+1-2 ) is connected to the fourth end (QEi-4) of the basic quadrupole (QEi); the first end (QE1-1) and the second end (QE1-2) of the basic quadrupole (QE1) form a first end (Q1) and a second end (Q2) connected to the quadrupole (40); the third end (QEn-3) and the fourth end (QEn-4) of the basic quadrupole (QEn) form a third end (Q3) and a fourth end (Q4) connected to the quadrupole (40).

5. The integrated circuit according to claim 1, characterized in that The depletion mode transistors (M1, M2, M11-M14, M21-M26, M31-M36, M41-M46, M51-M54, M61-M64, M71-M74) and the enhancement mode transistors (M3, M15, M27-M29, M37-M39, M45, M46, M55, M56, M75, M76) are GaN transistors or MOS transistors.

6. The integrated circuit according to claim 1, characterized in that The first dipole is a resistor (R1, R11, R21, R31, R41, R51, R61, R71).

7. The integrated circuit according to claim 1, characterized in that The first dipole is an enhancement mode transistor (M4), the gate of the enhancement mode transistor (M4) being connected to its drain.

8. The integrated circuit according to claim 2, characterized in that The second dipole (15) is a short circuit.

9. The integrated circuit according to claim 3, characterized in that: The second dipole (25) comprises an enhancement mode transistor (M15), the source of the enhancement mode transistor (M15) is connected to the second end of the second dipole (25), the gate of the enhancement mode transistor (M15) is connected to its drain, and the drain is connected to the first end (A3) of the second dipole (25).

10. The integrated circuit according to claim 4, characterized in that The second dipole (35) comprises n enhancement transistors (M27, M28), the gate of each enhancement transistor (M27, M28) being connected to its drain, the enhancement transistors (M27, M28) being connected in series, two consecutive enhancement transistors (M27, M28) being connected to the drain of the other through the source of one of them, and the drain of the first enhancement transistor (M27) forming the first end (A3) of the second dipole (35), and the source of the last enhancement transistor (M28) forming the second end (A4) of the second dipole (35).

11. The integrated circuit according to claim 1, characterized in that The integrated circuit comprises n branches (101-108) connected in parallel, and each branch is connected to the gate of a power transistor (P2-P8) through the source of its head transistor (M1, M11, M21, M31, M41, M51, M61, M71).

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