High-safety chip scan chain test mode circuit and access method

Abstract

The invention discloses a high-security chip scan chain test mode circuit and an entry method, and relates to the field of integrated circuit design, the high-security chip scan chain test mode circuit comprises a boundary scan test interface, a boundary scan test interface controller, a data register, a first data selector, a second data selector, an instruction decoder and an instruction register; the data register comprises an equipment marker register, a boundary scan register, a bypass register and a test register; the test register comprises N stages of test registers and M coding and decoding modules, and the coding and decoding modules are used for generating read-write enable signals of each stage of test register; opening the read-write permission of the test register through the instruction register and the coding and decoding module; according to the invention, the JTAG port is multiplexed, the number of pins required for testing is reduced, the difficulty of entering a scan chain test mode is increased, and the safety performance of the chip is improved.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit design, and in particular to a high-security chip scan chain test mode circuit and an entry method. Background Art

[0002] When the chip is in scan chain test mode, almost all the internal registers are connected in series, and their values ​​can be shifted in and out of the PAD. In this way, we can configure and observe the value of any register inside the chip through the scan chain, which will bring security risks to the chip.

[0003] There are two main ways to enter the existing scan chain test mode. One is to apply a fixed level to a specific pin. This method is too simple and can easily be used by others to attack the chip from the outside and steal internal information of the chip using the scan chain. The other is to reuse the JTAG port and enter the scan chain test mode by configuring the instruction register (Instruction Reg) and the data register (Data Reg). Compared with the first method, this method has greatly improved security, but there is still room for improvement.

[0004] The background description provided herein is for the purpose of generally presenting the context of the present disclosure. Unless otherwise indicated herein, the materials described in this section are not prior art to the claims of this application and are not admitted to be prior art by inclusion in this section. Summary of the invention

[0005] In view of the above technical problems in the related art, the present invention proposes a highly secure chip scan chain test mode circuit and entry method.

[0006] In order to achieve the above-mentioned invention object, the present invention adopts the following technical scheme: In a first aspect, the present invention provides a high-security chip scan chain test mode circuit, the chip scan chain test mode circuit includes a boundary scan test interface, a boundary scan test interface controller, a data register, a first data selector, a second data selector, an instruction decoder and an instruction register; the boundary scan test interface is used to receive test data and output test data; the boundary scan interface controller is used to generate control signals for the instruction register and the data register, and control the instruction register and the data register to capture, shift and update data; the instruction register is used to store instructions to be executed, and the instruction decoder encodes and decodes the instructions to be executed; the data register includes a boundary scan register and a test register; the boundary scan register is used for boundary scan testing; the test register includes N levels of test registers and M encoding and decoding modules, each level of test registers is composed of one or more groups of registers, and the encoding and decoding module is used to generate read and write enable signals for each level of test registers; the read and write permissions of the test registers are opened through the instruction register and the encoding and decoding module; wherein M is equal to N, and N is a positive integer greater than or equal to 2; The boundary scan test interface is connected to the boundary scan test interface controller, the data register and the instruction register; the instruction register is connected to the data register through the instruction decoder; the data register and the data decoder are connected to the first data selector; the boundary scan test interface controller, the instruction register and the first data selector are connected to the second data selector; the second data selector is connected to the boundary scan test interface; The instruction entered into the instruction register is decoded by the instruction decoder to generate a control signal to control the data register and the first data selector; The boundary scan test interface includes a test data input terminal, a test data output terminal, a test mode selection terminal, a test clock terminal and a test reset terminal.

[0007] Specifically, the boundary scan test interface controller is a finite state machine, which generates control signals for the instruction register and the data register, and controls the instruction register and the data register to capture, shift and update data.

[0008] Specifically, the test mode selection terminal being pulled high for 5 clock cycles can be regarded as a reset signal to make the boundary scan test interface controller enter a reset state.

[0009] Specifically, the test reset terminal is used to send a reset signal to make the boundary scan test interface controller enter a reset state.

[0010] Specifically, the data register further includes a bypass register, and the bypass register is 1-bit.

[0011] Specifically, the data register also includes a device flag register, and the device flag register is 32-bit.

[0012] Specifically, each level of test register in the test register is a 1-bit or multi-bit register.

[0013] Specifically, the read and write permissions of the test registers are opened through the instruction register and the codec module as follows: the read and write permissions of the test registers of the next level can be obtained only when the values ​​of the test registers of the previous level are all configured correctly, and the codec module can decide whether the chip enters the scan link mode only when the values ​​of the test registers of the last level are all configured correctly.

[0014] Specifically, the read and write permissions of the test registers at the next level can be obtained only when the values ​​of the test registers at the previous level are all configured correctly, and the codec module can decide whether the chip enters the scan chain mode only when the values ​​of the test registers at the last level are all configured correctly. Specifically, the test registers include first-level test registers, second-level test registers, a first codec module and a second codec module; the first-level test registers include n register groups, and the second-level test registers include m register groups; the read and write permissions of the first-level test registers are opened through the instruction register, and when the first-level test registers are configured to the correct values, the first codec module generates a read and write enable signal for the second-level test registers to work together with the instruction register to open the read and write permissions of the second-level test registers, and when the second-level test registers are configured to the correct values, the second codec module generates a scan chain test enable signal, and the chip enters the scan chain test mode; wherein m and n are both positive integers greater than or equal to 3.

[0015] In a second aspect, the present invention provides a high-security chip scan chain test mode entry method, based on the high-security chip scan chain test mode circuit described in any one of the first aspects, the method comprises the following steps: State 1, the test reset terminal signal is low level, the boundary scan test interface controller, instruction register and data register are in reset state. In this state, data or instructions cannot be loaded serially from the test data input terminal, and the output of the instruction register and data register maintains the reset value; State2, the test reset terminal signal is pulled high, and the boundary scan test interface controller is controlled to perform state conversion through the test mode selection terminal signal and the test clock terminal; State3, when the boundary scan test interface controller is in the Shift-IR state, the value of the test mode selection terminal is kept unchanged, and specific instructions are serially loaded from the test data input terminal. When the state machine switches to the Update-IR state, the read and write permissions of the specific first-level test registers can be opened; State4, in the Shift-DR state, the test data is serially loaded from the test data input terminal to configure the first-level test registers, and the state3 to state4 are cycled until all the values ​​in the register group of the first-level test registers are configured, and the chip obtains the read and write permissions of the second-level test registers; State 5, when the boundary scan test interface controller TAP Controller is in the Shift-IR state, the value of the test mode selection terminal is kept unchanged, and specific instructions are serially loaded from the test data input terminal. When the state machine switches to the Update-IR state, the read and write permissions of the specific second-level test registers can be opened; State 6, in the Shift-DR state, the test data is serially loaded from the test data input terminal TDI to configure the second-level test registers, and the state 5 to state 6 are looped until all the values ​​in the register group of the second-level test registers are configured; State7, the chip enters the scan chain test mode.

[0016] The present invention divides the test registers into two or more levels, and each level is composed of one or more groups of 1-bit or multi-bit registers. Only when the values ​​of the registers of the previous level are all configured correctly can the read and write permissions of the registers of the next level be obtained. The values ​​of the registers of the last level are determined by the encoding and decoding module to determine whether the chip enters the scan chain test mode or other test modes, thereby increasing the difficulty of entering the scan chain test mode and improving the chip safety performance.

[0017] The present invention reuses the JTAG port, reduces the number of pins required for testing, increases the difficulty of entering the scan chain test mode, and improves the chip safety performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0019] Figure 1 It is a schematic diagram of a circuit structure of a high-security chip scan chain test mode provided according to an embodiment of the present invention; Figure 2 is a schematic diagram of a state transition diagram of a boundary scan test interface controller provided in an embodiment of the present invention; Figure 3 is a schematic diagram of a scan chain test mode circuit provided according to an embodiment of the present invention; Figure 4 Schematic diagram of a method for entering a chip scan chain test mode with high security provided in accordance with an embodiment of the present invention; Among them, 1- boundary scan test interface; 2- boundary scan test interface controller; 3- data register; 4- first data selector; 5- second data selector; 6- instruction decoder; 7- instruction register; 8- device flag register; 9- boundary scan register; 10- bypass register; 11- test register. DETAILED DESCRIPTION

[0020] The following will be combined with the accompanying drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field belong to the scope of protection of the present invention.

[0021] Embodiment 1.

[0022] refer to Figure 1 , this embodiment provides a high-security chip scan chain test mode circuit, including a boundary scan test interface 1 (TAP), a boundary scan test interface controller 2 (TAP Controller), the data register 3 (DataReg), a first data selector 4, a second data selector 5, an instruction decoder 6 (IRDecoder), and an instruction register 7 (Instruction Reg); The instruction register 7 is used to store instructions to be executed, and the instruction decoder 6 encodes and decodes the instructions to be executed.

[0023] The first data selector 4 and the second data selector 5 are multiplexers; A multiplexer (MUX) is an electronic device whose main function is to select one of multiple input signals and output it.

[0024] The boundary scan test interface 1 is connected to the boundary scan test interface controller 2, the data register 3 and the instruction register 7; the instruction register 7 is connected to the data register 3 through the instruction decoder 6; the data register 3 and the data decoder 6 are connected to the first data selector 4; the boundary scan test interface controller 2, the instruction register 7 and the first data selector 4 are connected to the second data selector 5; the second data selector 5 is connected to the boundary scan test interface 1; the instruction entered into the instruction register 7 is decoded by the instruction decoder 6 to generate a control signal to control the data register 3 and the first data selector 4.

[0025] Specifically, the first end of the boundary scan test interface 1 is a test data output end, the second end of the boundary scan test interface 1 is a test data input end, the third end of the boundary scan test interface 1 is a test reset end, the fourth end of the boundary scan test interface 1 is a test mode selection end, and the fifth end of the boundary scan test interface 1 is a test clock end; a boundary scan test interface controller 2, the first end of the boundary scan test interface controller 2 is electrically connected to the sixth end of the boundary scan test interface 1, the second end of the boundary scan test interface controller 2 is electrically connected to the seventh end of the boundary scan test interface 1, and the third end of the boundary scan test interface controller 2 is electrically connected to the eighth end of the boundary scan test interface 1; a data register 3, the first end of the data register 3 is electrically connected to the ninth end of the boundary scan test interface 1, the second end of the data register 3 is electrically connected to the first end of the data register 3, and the third end of the data register 3 is electrically connected to the ninth end of the boundary scan test interface 1. The first data selector 4 is electrically connected to the second end of the data register 3, the fourth end of the data register 3 is electrically connected to the third end of the data register 3, and the fifth end of the data register 3 is electrically connected to the fourth end of the boundary scan test interface controller 2; the first data selector 4, the first end of the first data selector 4 is electrically connected to the sixth end of the data register 3, the second end of the first data selector 4 is electrically connected to the seventh end of the data register 3, the third end of the first data selector 4 is electrically connected to the eighth end of the data register 3, and the fourth end of the first data selector 4 is electrically connected to the ninth end of the data register 3; the second data selector 5, the first end of the second data selector 5 is electrically connected to the fifth end of the first data selector 4, the second end of the second data selector 5 is electrically connected to the tenth end of the boundary scan test interface 1, and the third end of the second data selector 5 is electrically connected to the fifth end of the boundary scan test interface controller 2; Specifically, the first end of the instruction decoder 6 is electrically connected to the tenth end of the data register 3, and the second end of the instruction decoder 6 is electrically connected to the sixth end of the first data selector 4; instruction register 7, the first end of the instruction register 7 is electrically connected to the fourth end of the data register 3, the second end of the instruction register 7 is electrically connected to the sixth end of the boundary scan test interface controller 2, the third end of the instruction register 7 is electrically connected to the third end of the instruction decoder 6, the fourth end of the instruction register 7 is electrically connected to the fourth end of the instruction decoder 6, the fifth end of the instruction register 7 is electrically connected to the fifth end of the instruction decoder 6, and the sixth end of the instruction register 7 is electrically connected to the fourth end of the second data selector.

[0026] The boundary scan test interface 1 can be 4-pin or 5-pin. The boundary scan test interface 1 includes a test data input terminal (TDI), a test data output terminal (TDO), a test mode selection terminal (TMS), a test clock terminal (TCK) and a test reset terminal (TRST). The test reset terminal can reset the boundary scan test interface controller 2. The test mode selection terminal can be pulled high for 5 clock cycles to make the boundary scan test interface controller 2 enter a reset state. Therefore, the test reset terminal is an optional interface. Preferably, in this embodiment, the scan test interface 1 is 5-pin, and the test reset terminal is a mandatory port.

[0027] The boundary scan test interface controller 2 is a finite state machine with 16 states, which generates control signals of the instruction register 7 (Instruction Reg) and the data register 3 (Data Reg), and controls the instruction register 7 and the data register 3 to capture Capture, shift Shift and update Update data.

[0028] The 16 states of the boundary scan test interface controller include: Test-Logic-Reset (test logic reset), Run-Test / Idle (run-test / idle), Select-DR-Scan (select data register scan), Capture-DR (capture data register), Shift-DR (data register shift), Exit1-DR (exit data register state 1), Pause-DR (pause data register state), Exit2-DR (exit data register state 2), Update-DR (data register refresh), Select-IR-Scan (select instruction register scan), Capture-IR (capture instruction register), Shift-IR (instruction register shift), Exit1-IR (exit instruction register state 1), Pause-IR (pause instruction register state), Exit2-IR (exit instruction register state 2), Update-IR (instruction register refresh).

[0029] Specifically, the state transition diagram of the boundary scan test interface controller 2 is as follows: Figure 2 As shown, the test mode selection terminal controls the boundary scan test interface controller 2 to perform state conversion at the rising edge of the test clock terminal. In the Capture state, data or instructions are loaded into the selected data register 3 or the instruction register 7 in parallel; in the Shift state, data or instructions are loaded into the selected data register 3 or the instruction register 7 in series through the test data input terminal, and the previous data or instructions are output in series from the test data output terminal; in the Update state, the current data or instructions are updated.

[0030] The data register 3 includes a device identification register 8 (IDCODE Reg), a boundary scan register 9 (Boundary Scan Reg), a bypass register 10 (Bypass Reg) and a test register 11 (Test Reg); in the JTAG standard protocol, the bypass register is 1-bit, and this data path can be selected through the Bypass instruction. The device identification register is 32-bit and is an optional option.

[0031] The boundary scan register 9 is used for boundary scan testing; the bypass register 10 is used to bypass the boundary scan logic and connect the chip input to the output through its internal 1-bit register; the device flag register 8 is used to store the chip's identity information.

[0032] Specifically, the first end of the device flag register 8 is electrically connected to the ninth end of the boundary scan test interface 1, and the second end of the device flag register 8 is electrically connected to the first end of the first data selector 4; the boundary scan register 9, the first end of the boundary scan register 9 is electrically connected to the first end of the device flag register 8, and the second end of the boundary scan register 9 is electrically connected to the second end of the first data selector 4; the first end of the bypass register 10 is electrically connected to the first end of the boundary scan register 9, and the second end of the bypass register 10 is electrically connected to the third end of the first data selector 4; the first end of the test register 11 is electrically connected to the first end of the bypass register 10, and the second end of the test register 11 is electrically connected to the fourth end of the first data selector 4.

[0033] The test register 11 is a register that needs to be used when the chip is tested, and the output of the register can generate a key signal required for the test after being encoded and decoded.

[0034] The test register 11 includes N levels of test registers and M encoding and decoding modules, each level of test registers is composed of one or more groups of registers, and the encoding and decoding module is used to generate read and write enable signals for each level of test registers; the read and write permissions of the test registers are opened through the instruction register and the encoding and decoding module; wherein M is equal to N, and N is a positive integer greater than or equal to 2; preferably, in this embodiment, M and N are both 2.

[0035] Only when the values ​​of the test registers of the previous level are all configured correctly can the read and write permissions of the test registers of the next level be obtained. Only when the values ​​of the test registers of the last level are all configured correctly can the codec module decide whether the chip enters the scan link mode. Among them, each level of test register is a 1-bit or multi-bit register.

[0036] refer to Figure 3 , the test register 11 includes a first-level test register, a second-level test register, a first encoding and decoding module and a second encoding and decoding module; the first-level test register includes n register groups, and the second-level test register includes m register groups; the read and write permissions of the first-level test register are opened through the instruction register, and when the first-level test register is configured to a correct value, the first encoding and decoding module generates a second-level test register read and write enable signal and works with the instruction register 7 to open the read and write permissions of the second-level test register, and when the second-level test register is configured to a correct value, the second encoding and decoding module generates a scan chain test enable signal, and the chip enters the scan chain test mode; wherein m and n are both positive integers greater than or equal to 3. Preferably, in this embodiment, m and n are both 3.

[0037] Figure 3 The improved scan chain test mode circuit is shown in the figure. The circuit mainly divides the test registers into two levels: the first-level test registers (level1 Test Reg) and the second-level test registers (level2 Test Reg). The first-level test registers include multiple register groups, group 1, group 2…group n, and the second-level test registers include multiple register groups, group 1, group 2…group m. The read and write permissions of the first-level test registers can be opened through the instruction register 7. When the first-level test registers are configured to the correct value, the first encoding and decoding module (Decode1) generates a second-level test register read and write enable signal (level2 Test Reg W / R enable), which works together with the instruction register 7 to open the read and write permissions of the second-level test registers. When the second-level test registers are configured to the correct value, the second encoding and decoding module (Decode2) generates a scan chain test enable signal (Scan Testenable), and the chip enters the scan chain test mode.

[0038] This embodiment provides a specific implementation method of entering the scan chain test mode through a test register, as shown below: The instruction register is a group of 8-bit registers. The test registers are divided into two levels: the first level and the second level. The first level test registers include three groups of 8-bit registers: group 1, group 2, and group 3. When the value of the instruction register is configured to 0x01, group 1 can be connected in series between TDI and TDO. When the value of the instruction register is configured to 0x02, group 2 can be connected in series between TDI and TDO. When the value of the instruction register is configured to 0x03, group 3 can be connected in series between TDI and TDO. When the value of group 1 is configured to 0x55, the value of group 2 is configured to 0x22, and the value of group 3 is configured to 0x77, the read and write permissions of the second level test registers can be obtained.

[0039] The second-level test registers include three 8-bit register groups: group 1, group 2, and group 3. When the value of the instruction register is configured to 0x04, group 1 can be connected in series between TDI and TDO. When the value of the instruction register is configured to 0x05, group 2 can be connected in series between TDI and TDO. When the value of the instruction register is configured to 0x06, group 3 can be connected in series between TDI and TDO. When the value of group 1 is configured to 0x25, the value of group 2 is configured to 0x26, and the value of group 3 is configured to 0x27, the chip enters the scan chain test mode.

[0040] In this embodiment, the test registers are divided into two or more levels, and each level is composed of one or more groups of 1-bit or multi-bit registers. Only when the values ​​of the registers of the previous level are all configured correctly can the read and write permissions of the registers of the next level be obtained. The values ​​of the registers of the last level are determined by the codec module to determine whether the chip enters the scan chain test mode or other test modes.

[0041] Embodiment 2.

[0042] refer to Figure 4 This embodiment provides a high-security chip scan chain test mode entry method based on the high-security chip scan chain test mode circuit of embodiment 1, comprising the following steps: state1, the test reset terminal TRST signal is low level, the boundary scan test interface controller TAPController, the instruction register Instruction Reg and the data register Data Reg are in reset state, in this state, data or instructions cannot be loaded serially from the test data input terminal TDI, and the outputs of the instruction register Instruction Reg and the data register Data Reg maintain the reset value; State2, the test reset terminal TRST signal is pulled high, and the boundary scan test interface controller TAP Controller is controlled to perform state conversion through the test mode selection terminal TMS signal and the test clock terminal TCK; State 3, when the boundary scan test interface controller TAP Controller is in the Shift-IR state, the value of the test mode selection terminal TMS is kept unchanged, and a specific instruction is serially loaded from the test data input terminal TDI. When the state machine switches to the Update-IR state, the read and write permissions of the specific first-level test registers can be opened; State 4, in the Shift-DR state, the test data is serially loaded from the test data input terminal TDI to configure the first-level test registers, and the state 3 to state 4 are cycled until the values ​​of the register groups group 1 to group n in the first-level test registers are all configured, and the chip obtains the read and write permissions of the second-level test registers; State 5, when the boundary scan test interface controller TAP Controller is in the Shift-IR state, the value of the test mode selection terminal TMS is kept unchanged, and a specific instruction is serially loaded from the test data input terminal TDI. When the state machine switches to the Update-IR state, the read and write permissions of the specific second-level test registers can be opened; State 6, in the Shift-DR state, the test data is serially loaded from the test data input terminal TDI to configure the second-level test registers, and state 5 to state 6 are looped until the values ​​of the register groups group 1 to group m in the second-level test registers are all configured; State7, the chip enters the scan chain test mode.

[0043] This embodiment reuses the JTAG port, reduces the number of pins required for testing, increases the difficulty of entering the scan chain test mode, and improves the chip security performance.

[0044] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A high-security chip scan chain test mode circuit, the chip scan chain test mode circuit includes a boundary scan test interface, a boundary scan test interface controller, a data register, a first data selector, a second data selector, an instruction decoder and an instruction register; the boundary scan test interface is used to receive test data and output test data; the boundary scan interface controller is used to generate control signals for the instruction register and the data register, and control the instruction register and the data register to capture, shift and update data; the instruction register is used to store instructions to be executed, and the instruction decoder encodes and decodes the instructions to be executed; the data register includes a boundary scan register and a test register; the boundary scan register is used for boundary scan testing; it is characterized in that The test register includes N levels of test registers and M codec modules, each level of test registers is composed of one or more groups of registers, and the codec module is used to generate a read and write enable signal for each level of test registers; the read and write permissions of the test registers are opened through the instruction register and the codec module; wherein M is equal to N, and N is a positive integer greater than or equal to 2; The boundary scan test interface is connected to the boundary scan test interface controller, the data register and the instruction register; the instruction register is connected to the data register through the instruction decoder; the data register and the data decoder are connected to the first data selector; the boundary scan test interface controller, the instruction register and the first data selector are connected to the second data selector; the second data selector is connected to the boundary scan test interface; The instruction entered into the instruction register is decoded by the instruction decoder to generate a control signal to control the data register and the first data selector; The boundary scan test interface includes a test data input terminal, a test data output terminal, a test mode selection terminal, a test clock terminal and a test reset terminal; The specific method of opening the read and write permissions of the test registers through the instruction register and the codec module is as follows: the read and write permissions of the test registers of the next level can be obtained only when the values ​​of the test registers of the previous level are all configured correctly, and the codec module can decide whether the chip enters the scan link mode only when the values ​​of the test registers of the last level are all configured correctly.

2. The chip scan chain test mode circuit according to claim 1, characterized in that: The boundary scan test interface controller is a finite state conversion machine, which generates control signals for the instruction register and the data register, and controls the instruction register and the data register to capture, shift and update data.

3. The chip scan chain test mode circuit according to claim 1, characterized in that: The test mode selection terminal being pulled high for 5 clock cycles can be regarded as a reset signal to put the boundary scan test interface controller into a reset state.

4. The chip scan chain test mode circuit according to claim 1, characterized in that: The test reset terminal is used to send a reset signal to make the boundary scan test interface controller enter a reset state.

5. The chip scan chain test mode circuit according to claim 1, characterized in that: The data register also includes a bypass register, and the bypass register is 1-bit.

6. The chip scan chain test mode circuit according to claim 1, characterized in that: The data register also includes a device flag register, and the device flag register is 32-bit.

7. The chip scan chain test mode circuit according to claim 1, characterized in that: Each level of test register in the test register is a 1-bit or multi-bit register.

8. The chip scan chain test mode circuit according to claim 1, characterized in that: The read and write permissions of the test registers at the next level can only be obtained when the values ​​of the test registers at the previous level are all configured correctly, and the codec module can decide whether the chip enters the scan chain mode only when the values ​​of the test registers at the last level are all configured correctly. Specifically, the test registers include first-level test registers, second-level test registers, a first codec module and a second codec module; the first-level test registers include n register groups, and the second-level test registers include m register groups; the read and write permissions of the first-level test registers are opened through the instruction register, and when the first-level test registers are configured to the correct values, the first codec module generates a read and write enable signal for the second-level test registers to work together with the instruction register to open the read and write permissions of the second-level test registers, and when the second-level test registers are configured to the correct values, the second codec module generates a scan chain test enable signal, and the chip enters the scan chain test mode; wherein m and n are both positive integers greater than or equal to 3.

9. A high-security chip scan chain test mode entry method, based on the high-security chip scan chain test mode circuit according to any one of claims 1 to 8, characterized in that: The method comprises the following steps: State 1, the test reset terminal signal is low level, the boundary scan test interface controller, instruction register and data register are in reset state. In this state, data or instructions cannot be loaded serially from the test data input terminal, and the output of the instruction register and data register maintains the reset value; State2, the test reset terminal signal is pulled high, and the boundary scan test interface controller is controlled to perform state conversion through the test mode selection terminal signal and the test clock terminal; State3, when the boundary scan test interface controller is in the Shift-IR state, the value of the test mode selection terminal is kept unchanged, and specific instructions are serially loaded from the test data input terminal. When the state machine switches to the Update-IR state, the read and write permissions of the specific first-level test registers can be opened; State4, in the Shift-DR state, the test data is serially loaded from the test data input terminal to configure the first-level test registers, and the state3 to state4 are cycled until all the values ​​in the register group of the first-level test registers are configured, and the chip obtains the read and write permissions of the second-level test registers; State 5, when the boundary scan test interface controller is in the Shift-IR state, the value of the test mode selection terminal is kept unchanged, and specific instructions are serially loaded from the test data input terminal. When the state machine switches to the Update-IR state, the read and write permissions of the specific second-level test registers can be opened; State 6, in the Shift-DR state, the test data is serially loaded from the test data input terminal TDI to configure the second-level test registers, and the state 5 to state 6 are looped until all the values ​​in the register group of the second-level test registers are configured; State7, the chip enters the scan chain test mode.

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