Circuit and method for calibrating on-chip RC time constant

Abstract

The invention provides a circuit and method for calibrating an on-chip RC time constant, and belongs to the technical field of analog integrated circuit calibration. In the circuit, the output end of an operational amplifier AMP is connected with the grid electrodes of transistors I1 and I2, and the source electrode of the transistor I1 is connected with the positive electrode of a resistor R and the negative input end of the AMP; the source of the I2 is connected with one end of the switch S1; the other end of the S1 is connected with one end of the switch S2 and one end of the switch S4, an upper-level plate of the capacitor array Cbank and the negative input of the operational amplifier CMP; the other end of the S2 is connected with a Cbank lower pole plate and one end of a switch S3; the S3 is connected between the negative end of the Cbank and the ground; s4 is connected between two input ends of the CMP; the output end DATA of the CMP is connected with a shift register Shift REG, and two paths of differential output control words of the shift register Shift REG are used for adjusting the capacitance value of the Cbank. According to the invention, the structure is simple, rapid calibration can be realized, a more accurate RC time constant is provided, and the performance robustness of the system is ensured.

Description

Technical Field

[0001] The invention belongs to the technical field of analog integrated circuit calibration, and in particular relates to a circuit and method for calibrating an on-chip RC time constant. Background Art

[0002] During the chip manufacturing process, wafer foundry equipment faces many complex problems, such as doping disturbance, line width variation, and via resistance value variation, which bring unpredictable and low parameter yield to the target specifications. Specifically for unit devices, changes in the parameters of integrated components will affect the performance of the entire integrated circuit system. In order to cover the impact of process angle changes, a large margin will be introduced in chip design, but at the same time, the circuit complexity will increase and the cost will increase. As one of the most important basic units, the active RC filter is used to filter out high-frequency or low-frequency components in the signal and retain the signal within the required frequency range. Its filtering performance is highly related to the passive components R and C. However, the manufacturing accuracy of on-chip resistors R and capacitors C is generally around ±20%, so the error of the RC product is about ±50%. This degree of bandwidth variation seriously deteriorates the performance of active RC filters. Therefore, on-chip resistor and capacitor calibration technology has become a hot topic of current research.

[0003] The US patent application number is US8552797, which shows a high-precision resistor and capacitor calibration circuit, which includes a current mirror CURRENT MIRROR, a gate, a comparator CMP, a digital logic DIGITAL LOGIC, a resistor Rref and a capacitor array Cc. Among them, the current mirror output transistor M1 is connected to the resistor Rref and the capacitor array Cc through the switch SWrc gate, the resistor Rref and the capacitor Cc are respectively connected to the positive input and negative input of the comparator CMP, the comparator CMP output is connected to the digital logic, and the digital logic output control word connects the capacitor array Cc and the main filter SLAVE FILTER. The working principle of the circuit is that the resistor and capacitor array reuse a current source through the gate to avoid the influence of the current mirror mismatch on the calibration accuracy; at the same time, after the comparator CMP compares the voltage values ​​on the resistor and capacitor arrays, the control word of the capacitor array is adjusted through the digital logic feedback to make the voltage values ​​on the resistor and capacitor arrays similar. In addition, the technical solution also reduces the influence of circuit parasitic capacitance through pre-charging technology. The disadvantage of this solution is that the capacitor array of the multi-bit control word needs to be discharged and charged multiple times during the calibration process, which increases power consumption and increases the calibration time, limiting its application in situations where frequent calibration is required.

[0004] The Chinese patent application number is 201911237566.5, which shows a circuit and method for calibrating on-chip RC constants using switched capacitors. The circuit structure is as follows Figure 1As shown, it includes three current mirrors, a comparator, a logic control unit, a resistor and a switched capacitor circuit. Among them, the current mirror is connected to the resistor R0, the resistor Rint and the switched capacitor circuit respectively, the resistor Rint and the switched capacitor circuit are connected to the positive and negative input terminals of the comparator respectively, the comparator output is connected to the control logic unit, and the control logic unit output is connected to the switched capacitor circuit. The basic principle of this circuit is to adjust the capacitance of the capacitor array by feedback by comparing the resistance value of the switched capacitor equivalent resistor and the on-chip resistor, so that the RC constant is close to the clock cycle of the switched capacitor circuit. The disadvantage of this solution is that the parasitic capacitance at the input of the comparator will reduce the calibration accuracy, and the ripple generated by the switched capacitor circuit requires a larger capacitor to reduce, which increases the calibration time and increases the area cost.

[0005] The common disadvantage of the above two RC constant calibration technologies is that the calibration time is long. The former requires multiple charging and discharging, which means multiple repeated sampling, resulting in redundant sampling time; the latter requires a larger filter capacitor, resulting in a longer circuit recovery time. Secondly, the influence of the parasitic capacitance at the input of the comparator is difficult to eliminate, which affects the calibration accuracy. Summary of the invention

[0006] The purpose of the present invention is to overcome the shortcomings of the prior art and propose a circuit and method for calibrating an on-chip RC time constant. The circuit structure of the present invention is simple, and fast calibration can be achieved. In the scenario where the chip ambient temperature or power supply voltage fluctuates greatly, a more accurate RC time constant is provided to ensure the performance robustness of the system.

[0007] The embodiment of the present invention provides a circuit for calibrating an on-chip RC time constant, comprising: an operational amplifier AMP, two identical transistors I1 and I2, a resistor R, a comparator CMP, a shift register Shift REG, a capacitor array Cbank, and four switches S1, S2, S3 and S4; wherein the output end of the operational amplifier AMP is respectively connected to the gates of the transistors I1 and I2, the source of the transistor I1 is connected to the positive electrode of the resistor R and the negative input end of the operational amplifier AMP, and is used to control the transistors I1 and I2 to output a reference current; the source of the transistor I2 is connected to one end of the switch S1, and is used to charge the capacitor array Cbank; the other end of the switch S1 is respectively connected to one end of the switches S2 and S4, the upper board of the capacitor array Cbank and the negative input of the operational amplifier CMP; the switch S1 is used to control the transistor I1 2. The output current is turned on and off; when S1 is connected, the transistor I2 is used to charge the capacitor array Cbank; the other end of the switch S2 is connected to the lower plate of the capacitor array Cbank and one end of the switch S3, which is used to clear the charge of the capacitor array Cbank in the charge clearing stage; the switch S3 is connected between the negative end of Cbank and the ground, and is used to disconnect the connection between the negative end of Cbank and the ground; the switch S4 is connected between the two input ends of the comparator CMP, and is used to pre-charge the two input ends of the comparator CMP to eliminate the influence of parasitic capacitance; the output end DATA of the comparator CMP is connected to the shift register Shift REG for data transmission, and the comparator CMP also generates a follow-up asynchronous clock ASYN_CLK for controlling the reading of data by the shift register Shift REG; the two differential output control words CCFG_X<4:0> and CCFG_Y<4:0> of the shift register Shift REG are connected to the capacitor array Cbank to adjust the capacitance of Cbank.

[0008] In a specific implementation of the present invention, the circuit further includes: a clock unit CLK Cell, a D flip-flop DFF, logic gates OR1, NOR1, AND2 and AND3; the clock unit CLK Cell is used to generate two inverted clock signals CLK and CLKB for controlling the state of the calibration circuit.

[0009] In a specific implementation of the present invention, it also includes:

[0010] The output CLK of the clock unit CLK Cell is respectively connected to the trigger DFF, logic gates OR1, NOR1, and AND2; CLKB is connected to one end of the comparator CMP and the logic gate AND3; the other ends of the logic gates OR1 and NOR1 are connected to the Q end of the trigger DFF; the other ends of the logic gates AND2 and AND3 are connected to the QB end of the trigger DFF; the outputs of the OR1, NOR1, AND2, and AND3 are respectively connected to switches S1, S2, S3, and S4 for controlling the charging and discharging process of the capacitor array Cbank.

[0011] In a specific implementation of the present invention, the capacitor array Cbank includes: capacitors Cfix, 8Ca, 8Cb, 4Ca, 4Cb, 2Ca, 2Cb, 1Ca, 1Cb, 05Ca, 05Cb, and switches S5, S6, S7, S8, S9, S10, S11, S12, S13, S14; wherein Ca and Cb are capacitors with equal capacitances controlled by CCFG_X and CCFG_Y respectively; the upper plates of all capacitors in the capacitor array Cbank are connected together; the capacitor C The lower plate of fix is ​​connected to ground, and the lower plates of capacitors 8Ca, 8Cb, 4Ca, 4Cb, 2Ca, 2Cb, 1Ca, 1Cb, 05Ca, and 05Cb are respectively connected to one end of switches S14, S13, S12, S11, S10, S9, S8, S7, S6, and S5; the other ends of switches S14, S13, S12, S11, S10, S9, S8, S7, S6, and S5 are connected to ground; the control ends of switches S14, S12, S10, S8, and S6 are connected to the output CCFG_X<4:0> of shift register Shift REG, and the control ends of switches S13, S11, S9, S7, and S5 are connected to the output CCFG_Y<4:0> of shift register Shift REG.

[0012] This embodiment also provides a method for calibrating an on-chip RC time constant based on the above circuit, including:

[0013] Each calibration cycle is divided into: charge clearing stage, sampling and holding stage, and charge redistribution stage; in the charge clearing stage, CLK The clock signal CLK output by Cell is 0, CLKB is 1, S1, S2, S3, S4 are 0, 1, 0, 1 respectively, switches S1, S3 are disconnected, switches S2, S4 are closed, the charge of capacitor array Cbank is cleared, and the negative input terminal of comparator CMP is charged to VREF; in the sampling and holding stage, the rising edge of CLK arrives, CLK is 1, CLKB is 0, S1, S2, S3, S4 are 1, 0, 1, 0 respectively, switches S1, S3 are closed, switches S2, S4 are disconnected, and transistor I2 charges Cbank; in the charge redistribution stage, the falling edge of CLK arrives, the D flip-flop works, S1, S2, S3, S4 are 0, 0, 1, 0 respectively, switches S1, S2, S4 are disconnected, switch S3 is closed, the charge number stored in capacitor array Cbank is Tint*VREF / R, and comparator CMP outputs the comparison result and the accompanying clock to shift register Shift REG, Shift REG changes CCFG_X<4:0> or CCFG_Y<4:0> from high to low; where Tint is the duty cycle time of CLK, that is, the target value of RC calibration.

[0014] In a specific implementation of the present invention, it also includes:

[0015] In the charge clearing stage, the initial values ​​of the control words CCFG_X<4:0> and CCFG_Y<4:0> are 5'B11111 and 5'B00000 respectively; in each calibration cycle, the control word is adjusted accordingly according to the result of the comparator CMP; among them, if the charging voltage Vc is greater than VREF, the comparator CMP outputs 0, CCFG_X<4:0> remains unchanged, and the control word of CCFG_Y<4:0> corresponding to this cycle changes from 0 to 1, completing one comparison; if the charging voltage Vc is less than VREF, the comparator CMP outputs 1, CCFG_Y<4:0> remains unchanged, and the control word of CCFG_X<4:0> corresponding to this cycle changes from 1 to 0, completing one comparison; after completing 5 comparisons, the calibration of this cycle ends.

[0016] Features and beneficial effects of the present invention:

[0017] The switch control logic of the circuit of the present invention is simple, and only includes one D flip-flop and four logic gates, while the shift register is controlled by a clock generated by a dynamic comparator; the calibration process is fast and efficient, and only one capacitor charging process is required, that is, only one sampling process of time information occurs, which greatly improves the calibration efficiency. The present invention also avoids the influence of parasitic capacitance other than the capacitor array, especially the parasitic capacitance at the input end of the comparator, on the calibration accuracy. The present invention can realize fast calibration, and provide more accurate resistance and capacitance time constants in scenarios where the chip ambient temperature or power supply voltage fluctuates greatly, thereby ensuring the performance robustness of the system. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 A structural diagram of an existing circuit for calibrating an on-chip RC constant using a switched capacitor;

[0019] Figure 2 A structural diagram of a circuit for calibrating an on-chip RC time constant according to an embodiment of the present invention;

[0020] Figure 3 A logic control circuit diagram of the charge and discharge state of the capacitor array Cbank in a specific embodiment of the present invention;

[0021] Figure 4 FIG. 1 is a circuit structure diagram of a capacitor array Cbank in a specific implementation period of the present invention;

[0022] Figure 5 A circuit structure diagram of a circuit for calibrating an on-chip RC time constant in a charge zeroing stage in a specific embodiment of the present invention;

[0023] Figure 6 A circuit structure diagram of a circuit for calibrating an on-chip RC time constant in a sampling and holding stage according to a specific embodiment of the present invention;

[0024] Figure 7 A circuit structure diagram of a circuit for calibrating an on-chip RC time constant in a charge redistribution stage according to a specific embodiment of the present invention;

[0025] Figure 8 A calibration timing diagram in a specific embodiment of the present invention. DETAILED DESCRIPTION

[0026] A circuit and method for calibrating an on-chip RC time constant proposed by the present invention are described in detail below in conjunction with the accompanying drawings and embodiments:

[0027] The embodiment of the present invention provides a circuit for calibrating an on-chip RC time constant, the structure of which is as follows: Figure 2As shown, it includes: an operational amplifier AMP, two identical transistors I1 and I2, a resistor R, a comparator CMP, a shift register Shift REG, a capacitor array Cbank, and four switches S1, S2, S3 and S4. The output end of the operational amplifier AMP is connected to the gates of transistors I1 and I2 respectively, the source of transistor I1 is connected to the positive electrode of resistor R and the negative input end of the operational amplifier AMP, and is used to control the transistors I1 and I2 to output reference current; the source of transistor I2 is connected to one end of switch S1, and is used to charge the capacitor array Cbank; the other end of switch S1 is connected to one end of switches S2 and S4, the upper plate of the capacitor array Cbank and the negative input of the operational amplifier CMP respectively; switch S1 is used to control the on and off of the output current of transistor I2; when S1 is connected, transistor I2 is used to charge the capacitor array Cbank; the other end of switch S2 is connected to the lower plate of the capacitor array Cbank and one end of switch S3, and is used to clear the charge of the capacitor array Cbank in the charge clearing stage; switch S3 is connected between the negative end of Cbank and the ground, and is used to disconnect the connection between the negative end of Cbank and the ground; switch S4 is connected between the two input ends of the comparator CMP, and is used to pre-charge the two input ends of the comparator CMP to eliminate the influence of parasitic capacitance; the output end DATA of the comparator CMP is connected to the shift register Shift REG is used to transmit data. The comparator CMP also generates an asynchronous clock ASYN_CLK to control the reading of data by the shift register Shift REG. The two differential output control words CCFG_X<4:0> and CCFG_Y<4:0> of the shift register Shift REG are connected to the capacitor array Cbank to adjust the capacitance of Cbank.

[0028] The circuits described in this embodiment are all implemented using conventional components or processes.

[0029] Furthermore, the circuit for calibrating the on-chip RC time constant described in this embodiment also includes: a clock unit CLKCell, a D flip-flop DFF, logic gates OR1, NOR1, AND2 and AND3; the clock unit CLK Cell is used to generate two inverted clocks CLK and CLKB for controlling the state of the calibration circuit.

[0030] Furthermore, the logic control circuit of the charge and discharge state of the capacitor array Cbank in this embodiment is as follows: Figure 3As shown, the output CLK of the clock unit CLK Cell is respectively connected to the trigger DFF, logic gates OR1, NOR1, and AND2, and CLKB is connected to one end of the comparator CMP and the logic gate AND3; the other ends of the logic gates OR1 and NOR1 are connected to the Q end of the trigger DFF, and the other ends of the logic gates AND2 and AND3 are connected to the QB end of the trigger DFF; the outputs of the OR1, NOR1, AND2, and AND3 are respectively connected to switches S1, S2, S3, and S4 for controlling the charging and discharging process of the capacitor array Cbank.

[0031] Furthermore, the capacitor array Cbank described in this embodiment is designed by adopting SAR (successive approximation) logic calibration, and its structure is as follows: Figure 4 As shown, it includes capacitors Cfix, 8Ca, 8Cb, 4Ca, 4Cb, 2Ca, 2Cb, 1Ca, 1Cb, 05Ca, 05Cb (wherein the number before the symbol represents the number of capacitors, Ca and Cb are capacitors with equal capacitance but controlled by CCFG_X and CCFG_Y respectively) and switches S5, S6, S7, S8, S9, S10, S11, S12, S13, S14. The upper plates of the capacitors Cfix, 8Ca, 8Cb, 4Ca, 4Cb, 2Ca, 2Cb, 1Ca, 1Cb, 05Ca, and 05Cb are connected together, the lower plate of the capacitor Cfix is ​​connected to the ground, the lower plates of the capacitors 8Ca, 8Cb, 4Ca, 4Cb, 2Ca, 2Cb, 1Ca, 1Cb, 05Ca, and 05Cb are respectively connected to one end of switches S14, S13, S12, S11, S10, S9, S8, S7, S6, and S5, and the other ends of the switches S14, S13, S12, S11, S10, S9, S8, S7, S6, and S5 are connected to the ground; the control ends of the switches S14, S12, S10, S8, and S6 are connected to the shift register Shift The output CCFG_X<4:0> of REG, the control ends of the switches S13, S11, S9, S7, S5 are connected to the output CCFG_Y<4:0> of the shift register Shift REG.

[0032] It should be noted that the capacitance values ​​of Ca and Cb in the above Cbank need to be determined by the specific calibration target RC time constant.

[0033] Furthermore, the clock unit CLK Cell in this embodiment has two implementation modes. The first implementation mode is that only two inverted clocks CLK and CLKB are output, wherein CLK is connected to the comparator CMP as a sampling clock.

[0034] Furthermore, an embodiment of the present invention also provides a method for calibrating an on-chip RC time constant based on the above circuit, comprising:

[0035] The system's precise clock can obtain two inverse clock signals CLK and CLKB with accurate duty cycles by simply dividing the clock unit CLK Cell, where the duty cycle time Tint of CLK is the target value of RC calibration. The calibration method of the circuit described in this embodiment is only applicable to low-frequency clocks. If there is only a high-frequency clock, it is necessary to reduce the frequency to obtain a suitable duty cycle time. This calibration method is divided into three stages in each calibration cycle, namely the charge zeroing stage, the sampling and holding stage, and the charge redistribution stage. First, the calibration enters the charge zeroing stage, when CLK is "0", CLKB is "1", S1, S2, S3, and S4 are "0", "1", "0", and "1", respectively. At this time, the circuit structure is as follows Figure 5 As shown, switches S1 and S3 are disconnected, and switches S2 and S4 are closed. At this time, the charge of the capacitor array Cbank is cleared, and the negative input terminal of the comparator CMP is charged to VREF. Then the rising edge of CLK arrives, CLK is "1", CLKB is "0", and the sampling and holding phase begins. S1, S2, S3, and S4 are "1", "0", "1", and "0" respectively. At this time, the circuit structure is as follows Figure 6 As shown, switches S1 and S3 are closed, switches S2 and S4 are open, and transistor I2 charges Cbank. Finally, after the falling edge of CLK arrives, the D flip-flop works and the calibration enters the charge redistribution stage. At this time, S1, S2, S3, and S4 are "0", "0", "1", and "0" respectively. At this time, the circuit structure is as follows Figure 7 As shown, switches S1, S2, and S4 are opened, and switch S3 is closed. The charge number stored in the capacitor array Cbank is Tint*VREF / R. The comparator CMP outputs the comparison result and the accompanying clock to the shift register Shift REG, which changes CCFG_X<4:0> or CCFG_Y<4:0> in a high-to-low manner.

[0036] Furthermore, in this embodiment, the capacitor array Cbank is designed for SAR (Successive Approximation Register) logic calibration, and the initial values ​​of the control words CCFG_X<4:0> and CCFG_Y<4:0> are 5'B11111 and 5'B00000 respectively, in order to obtain an intermediate capacitance value. In each calibration cycle, the control word is adjusted accordingly according to the result of the comparator CMP; if the charging voltage Vc is greater than VREF, the comparator CMP outputs 0, CCFG_X<4:0> remains unchanged, and the control word of CCFG_Y<4:0> corresponding to the cycle changes from 0 to 1, completing one comparison. For example, if the charging voltage Vc is greater than VREF during the first comparison, the comparator CMP outputs "0", and CCFG_X<4:0> and CCFG_Y<4:0> become 5'B11111 and 5'B10000 respectively; on the contrary, if the charging voltage Vc is less than VREF, the comparator CMP outputs 1, CCFG_Y<4:0> remains unchanged, and the control word of CCFG_X<4:0> corresponding to the cycle changes from 1 to 0, completing one comparison; after repeating the comparison five times, the calibration of the cycle ends. The calibration timing diagram of a specific embodiment of the present invention is shown as follows: Figure 8 As shown in the figure, at the beginning of the calibration, CLK is "0", S1, S2, S3, S4 are "0", "1", "0", "1" respectively, and CCFG_X<4:0> and CCFG_Y<4:0> are reset to "11111" and "00000" respectively; after the calibration starts, the rising edge of CLK arrives, S1, S2, S3, S4 become "1", "0", "1", "0", and the capacitor array Cbank is charged during the high level period of CLK, and Vc rises linearly; with the arrival of the falling edge of CLK, S1, S2, S3, S4 become "0", "0", "1", "0", and the sampling of the capacitor array Cbank is completed. At this time, if Vc is greater than VREF, CCFG_X<4:0> remains unchanged, and CCFG_Y<4:0> becomes "10000", and the calibration enters the charge redistribution stage; the subsequent process is similar.

[0037] The following further describes the above-mentioned features and beneficial effects of the present invention:

[0038] In summary, the circuit for calibrating an on-chip RC time constant described in this embodiment has the following advantages: the logic control of the switch is simple, because it only needs to be converted in the first two stages of calibration, and this process only requires 1 D flip-flop, 1 OR gate OR1, 1 NOR gate NOR1 and two AND gates AND1 and AND2 to complete; secondly, the calibration process only requires one charge and discharge, that is, the capacitor array Cbank only needs one discharge and charge, and there is no need to repeat the discharge and charge every time the capacitor array control word is switched, because the amount of information related to time has been converted into charge and stored on the capacitor array Cbank, and the change of the control word does not change its charge number. Therefore, the waste of power consumption is avoided, the calibration time is greatly shortened, and the calibration efficiency is improved. Finally, when the capacitor array Cbank is small, the input capacitance Cp of the comparator cannot be ignored, which will cause deviation in the calibration result. In this embodiment, the negative input terminal of the comparator CMP is pre-charged in the charge clearing stage, so that the Vc node stores the charge amount of Cp*VREF in advance. Therefore, after the calibration is completed, that is, after Vc is adjusted to the vicinity of VREF, the charging charge Tint*VREF / R is almost completely stored on the capacitor array Cbank, and will not be shared by the parasitic capacitance of the comparator, thereby improving the calibration accuracy.

[0039] The description and application of the present invention here are illustrative and are not intended to limit the scope of the present invention to the above-described embodiments. Variations and changes of the embodiments disclosed here are possible, and component replacements and equivalences in the embodiments are well known to those of ordinary skill in the art. Without departing from the basic principles and essential features of the present invention, the present invention can be implemented in other forms, structures, different parameters, different proportions, and using different components and materials. These variations and changes to the disclosed embodiments are considered to be part of the present invention based on the principles and spirit of the present invention.

Claims

1. A circuit for calibrating an on-chip RC time constant, characterized in that: include: An operational amplifier AMP, two identical transistors I1 and I2, a resistor R, a comparator CMP, a shift register Shift REG, a capacitor array Cbank, and four switches S1, S2, S3, and S4; wherein the output end of the operational amplifier AMP is connected to the gates of the transistors I1 and I2 respectively, and the source of the transistor I1 is connected to the positive electrode of the resistor R and the negative input end of the operational amplifier AMP, so as to control the transistors I1 and I2 to output a reference current; The source of transistor I2 is connected to one end of switch S1, which is used to charge capacitor array Cbank; the other end of switch S1 is respectively connected to one end of switches S2 and S4, the upper plate of capacitor array Cbank and the negative input of operational amplifier CMP; switch S1 is used to control the on and off of transistor I2 output current; when S1 is connected, transistor I2 is used to charge capacitor array Cbank; the other end of switch S2 is connected to the lower plate of capacitor array Cbank and one end of switch S3, which is used to clear the charge of capacitor array Cbank in the charge clearing stage; switch S3 is connected between the negative end of Cbank and the ground, which is used to disconnect the connection between the negative end of Cbank and the ground; switch S4 is connected between the two input ends of comparator CMP, which is used to pre-charge the two input ends of comparator CMP to eliminate the influence of parasitic capacitance; the output end DATA of comparator CMP is connected to shift register Shift REG for data transmission, and comparator CMP also generates a follow-up asynchronous clock ASYN_CLK, which is used to control the reading of data by shift register Shift REG; shift register Shift The two differential output control words CCFG_X<4:0> and CCFG_Y<4:0> of REG are connected to the capacitor array Cbank to adjust the capacitance of Cbank.

2. The circuit according to claim 1, characterized in that The circuit further comprises: a clock unit CLK Cell, a D flip-flop DFF, logic gates OR1, NOR1, AND2 and AND3; the clock unit CLK Cell is used to generate two inverted clock signals CLK and CLKB for controlling the state of the calibration circuit.

3. The circuit according to claim 2, characterized in that Also includes: The output CLK of the clock unit CLK Cell is connected to the flip-flop DFF, logic gates OR1, NOR1, and AND2 respectively; CLKB is connected to one end of the comparator CMP and the logic gate AND3; the other ends of the logic gates OR1 and NOR1 are connected to the Q end of the trigger DFF; the other ends of the logic gates AND2 and AND3 are connected to the QB end of the trigger DFF; the outputs of OR1, NOR1, AND2, and AND3 are respectively connected to switches S1, S2, S3, and S4 to control the charging and discharging process of the capacitor array Cbank.

4. The circuit according to claim 3, characterized in that The capacitor array Cbank includes: capacitors Cfix, 8Ca, 8Cb, 4Ca, 4Cb, 2Ca, 2Cb, 1Ca, 1Cb, 05Ca, 05Cb, and switches S5, S6, S7, S8, S9, S10, S11, S12, S13, S14; wherein Ca and Cb are capacitors with equal capacitances controlled by CCFG_X and CCFG_Y respectively; the upper plates of all capacitors in the capacitor array Cbank are connected together; the lower plate of the capacitor Cfix Connected to ground, the lower plates of capacitors 8Ca, 8Cb, 4Ca, 4Cb, 2Ca, 2Cb, 1Ca, 1Cb, 05Ca, and 05Cb are respectively connected to one end of switches S14, S13, S12, S11, S10, S9, S8, S7, S6, and S5; the other ends of switches S14, S13, S12, S11, S10, S9, S8, S7, S6, and S5 are connected to ground; the control ends of switches S14, S12, S10, S8, and S6 are connected to the output CCFG_X<4:0> of shift register Shift REG, and the control ends of switches S13, S11, S9, S7, and S5 are connected to the output CCFG_Y<4:0> of shift register Shift REG.

5. A method for calibrating an on-chip RC time constant based on the circuit as claimed in any one of claims 3 to 4, characterized in that: include: Each calibration cycle is divided into: charge clearing stage, sampling and holding stage, and charge redistribution stage; in the charge clearing stage, the clock signal CLK output by CLK Cell is 0, CLKB is 1, S1, S2, S3, and S4 are 0, 1, 0, and 1 respectively, switches S1 and S3 are opened, switches S2 and S4 are closed, the charge of the capacitor array Cbank is cleared, and the negative input terminal of the comparator CMP is charged to VREF; In the sampling and holding stage, the rising edge of CLK arrives, CLK is 1, CLKB is 0, S1, S2, S3, S4 are 1, 0, 1, 0 respectively, switches S1 and S3 are closed, switches S2 and S4 are open, and transistor I2 charges Cbank; in the charge redistribution stage, the falling edge of CLK arrives, the D flip-flop works, S1, S2, S3, S4 are 0, 0, 1, 0 respectively, switches S1, S2, S4 are open, switch S3 is closed, the number of charges stored in the capacitor array Cbank is Tint*VREF / R, and the comparator CMP outputs the comparison result and the accompanying clock to the shift register Shift REG, and ShiftREG changes CCFG_X<4:0> or CCFG_Y<4:0> in a high-to-low manner; where Tint is the duty cycle time of CLK, that is, the target value of RC calibration.

6. The method according to claim 5, characterized in that Also includes: In the charge clearing stage, the initial values ​​of the control words CCFG_X<4:0> and CCFG_Y<4:0> are 5'B11111 and 5'B00000 respectively; in each calibration cycle, the control word is adjusted accordingly according to the result of the comparator CMP; among them, if the charging voltage Vc is greater than VREF, the comparator CMP outputs 0, CCFG_X<4:0> remains unchanged, and the control word of CCFG_Y<4:0> corresponding to this cycle changes from 0 to 1, completing one comparison; if the charging voltage Vc is less than VREF, the comparator CMP outputs 1, CCFG_Y<4:0> remains unchanged, and the control word of CCFG_X<4:0> corresponding to this cycle changes from 1 to 0, completing one comparison; after completing 5 comparisons, the calibration of this cycle ends.

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