Ultrasonic echo acquisition system

Abstract

The invention relates to the field of ultrasonic echo acquisition, in particular to an ultrasonic echo acquisition system which comprises an ultrasonic transceiving module, an echo signal processing module, a data transmission module and an upper computer. The echo signal processing module comprises a variable gain amplification circuit, a differential drive circuit, an analog-to-digital conversion circuit, a first-in first-out cache circuit and a main controller module; and the upper computer is used for receiving the digital signal of the main controller module through the data transmission module and sending a command to the main controller so as to adjust the sampling rate of the digital signal or the amplification factor of the variable gain amplification circuit. A fixed sampling rate is adopted in the analog-to-digital conversion circuit, and the sampling rate is changed without changing the clock frequency; when the sampling rate needs to be adjusted, the digital signal is extracted and resampled in the master controller module, so that the situation that the working condition of a sampling and holding circuit in the ADC chip is influenced due to too low clock frequency, and the sampling error is too large can be avoided.

Description

Technical Field

[0001] The invention relates to the field of ultrasonic echo acquisition, and in particular to an ultrasonic echo acquisition system. Background Art

[0002] The existing ultrasonic echo acquisition system has the following main problems: 1. Insufficient data transmission rate and efficiency: The existing high-speed data acquisition system has bottlenecks in data transmission rate and efficiency, especially for large-scale data transmission, data transmission delay and data loss are prone to occur. 2. Data acquisition accuracy and synchronization issues: The multi-channel data acquisition system may have deficiencies in acquisition accuracy and synchronization, resulting in the collected data not accurately reflecting the real situation, especially when high-frequency signals are collected. Synchronization errors are prone to occur. 3. Complex memory management and data processing: The existing system has high complexity in managing large-capacity data storage and processing, and is prone to data reading and writing bottlenecks, affecting the overall performance of the system. Especially in high-speed data flow environments, effective memory management is a challenge. 4. USB communication protocol complexity and stability: The USB communication protocol is complex, and the existing USB transmission module may face stability issues in actual use, especially in high-speed data transmission, transmission errors and data corruption may occur. 5. Insufficient data analysis and processing tools: The existing test and measurement system is insufficient in data analysis and processing tools, lacks flexibility and efficiency, and cannot meet the needs of real-time data processing and analysis. Summary of the invention

[0003] In view of the above problems, the present invention proposes a technical solution:

[0004] An ultrasonic echo acquisition system comprises an ultrasonic transceiver module, an echo signal processing module, a data transmission module and a host computer;

[0005] The ultrasonic transceiver module is used to send ultrasonic signals and receive original echo signals;

[0006] The echo signal processing module includes a variable gain amplifier circuit, a differential drive circuit, an analog-to-digital conversion circuit, a first-in-first-out buffer circuit, and a main controller module;

[0007] The variable gain amplifier circuit is used to receive the original echo signal from the ultrasonic transceiver module and amplify the original echo signal to obtain an amplified echo signal; the amplification factor is controlled by the control signal of the main controller module;

[0008] The differential driving circuit is used for receiving the amplified echo signal and converting the amplified echo signal into a differential signal;

[0009] The analog-to-digital conversion circuit is used to receive the differential signal, sample the differential signal and convert it into a digital signal with a fixed sampling rate;

[0010] The main controller module is used to send a control signal to the variable gain amplifier circuit to adjust the gain of the variable gain amplifier circuit; the main controller module is also used to receive the digital signal of the analog-to-digital conversion circuit through the first-in first-out buffer circuit; when the sampling rate of the digital signal needs to be adjusted, the main controller module implements the method of extracting and resampling the digital signal;

[0011] The data transmission module is used to transmit data between the main controller module and the host computer;

[0012] The host computer is used to receive the digital signal of the main controller module through the data transmission module and send a command to the main controller module to adjust the sampling rate of the digital signal or the amplification factor of the variable gain amplifier circuit.

[0013] Preferably, the first-in-first-out cache circuit includes an asynchronous write FIFO and a read FIFO; it also includes an SDRAM controller and an SDRAM; wherein the write FIFO is responsible for caching the digital signal of the analog-to-digital conversion circuit, which is then read and stored in the SDRAM by the SDRAM controller; the read FIFO is responsible for caching the data read from the SDRAM, and outputting it to the main controller module under the control of the SDRAM controller.

[0014] Preferably, when the amount of data in the write FIFO cache is greater than the amount of data written in one burst, the digital signal of the analog-to-digital conversion circuit is stopped from being cached; when the amount of data in the read FIFO cache is less than half of the read FIFO cache capacity, data output to the main controller module is stopped.

[0015] Preferably, the ultrasonic transceiver module includes STEVAL-IME011V2.

[0016] Preferably, the variable gain amplifier circuit uses an AD604 chip as a signal amplifier chip;

[0017] Preferably, the differential drive circuit uses AD8138 chip as the processing chip

[0018] Preferably, the analog-to-digital conversion circuit realizes analog-to-digital conversion through an ACM1030 module.

[0019] Preferably, the main controller module uses an EP4CE10 chip as a control chip.

[0020] Preferably, the data transmission module realizes data transmission by using FX2.

[0021] Beneficial effects:

[0022] 1. A fixed sampling rate is used in the analog-to-digital conversion circuit, and the sampling rate is not changed by changing the clock frequency. When the sampling rate needs to be adjusted, it is achieved by extracting and resampling the digital signal inside the main controller module. This can avoid the problem that the clock frequency is too low, affecting the working condition of the sampling and holding circuit inside the ADC chip, resulting in a large sampling error.

[0023] 2. By sending commands to the main controller module through the PyUSB tool of the host computer, key parameters such as the sampling rate and gain of the analog-to-digital conversion can be flexibly set. This flexibility ensures the controllability and adaptability of the data acquisition process, especially when the experimental conditions change, it can be adjusted quickly, avoiding the cumbersome hardware configuration process in traditional technologies. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 It is a hardware system structure diagram of the present invention;

[0025] Figure 2 It is a structural diagram of the echo signal processing module of the present invention; DETAILED DESCRIPTION

[0026] In order to make the purpose, features and advantages of the present invention more obvious and easy to understand, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the embodiments described below are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0027] like Figures 1 to 2 As shown, an ultrasonic echo acquisition system includes an ultrasonic transceiver module, an echo signal processing module, a data transmission module, and a host computer;

[0028] The ultrasonic transceiver module is used to send ultrasonic signals and receive original echo signals. In this embodiment, the ultrasonic transceiver module includes STEVAL-IME011V2, which has advanced ultrasonic transmission and reception circuits with built-in precise ultrasonic generators and receiving devices. Its main controller adopts the STM32F series, which has powerful computing and control capabilities and can accurately adjust the ultrasonic transmission frequency, waveform shape and amplitude to meet different application requirements. STEVAL-IME011V2 not only provides an advanced hardware platform and precise signal processing capabilities, but also has flexibility and scalability, making it very suitable for developing and deploying applications that require high-precision ultrasonic sensing.

[0029] The echo signal processing module includes a variable gain amplifier circuit, a differential drive circuit, an analog-to-digital conversion circuit, a first-in-first-out buffer circuit, and a main controller module;

[0030] Among them, the variable gain amplifier circuit is used to receive the original echo signal from the ultrasonic transceiver module, and amplify the original echo signal to obtain the amplified echo signal; the amplification factor is controlled by the control signal of the main controller module; in this embodiment, the variable gain amplifier circuit uses the AD604 chip as the signal amplification chip; when the ultrasonic signal emitted by the ultrasonic transceiver module passes through the muscle tissue and is reflected back, the signal strength will be small due to the absorption and scattering of the human tissue. In order to effectively process these echo signals, a gain amplifier is required to amplify the amplitude of the signal. The AD604 chip is a dual-output, low-noise variable gain amplifier, and the amplification factor of the AD604 can be set by analog voltage. This design not only provides high amplification accuracy and low noise characteristics, but also has two independent linear amplification channels. AD604 is specially optimized for time-based variable gain control in ultrasonic applications, and can maintain stable gain even when the temperature and power supply change. Through this module, the strength and clarity of the echo signal received from the ultrasonic probe can be effectively enhanced, so that the subsequent data analysis and processing work is more reliable and accurate.

[0031] The differential drive circuit is used to receive the amplified echo signal and convert the amplified echo signal into a differential signal; in this embodiment, the differential drive circuit uses the AD8138 chip as a processing chip; the AD8138 differential chip processes the amplified echo signal and converts it into a differential signal to reduce common-mode noise, and is used to drive the analog-to-digital conversion circuit to finally complete the sampling of the echo. The chip has the characteristics of low harmonic distortion, adjustable common-mode output voltage, low input noise, and short configuration time. The chip controls the output of differential and common-mode voltages through an internal feedback loop, and finally the signal component of the common-mode voltage in the output signal is zero, which can achieve an almost completely balanced differential output, and the signal amplitudes of the two differential ends are the same, and the phase difference is 180°.

[0032] The analog-to-digital conversion circuit is used to receive differential signals, sample the differential signals and convert them into digital signals with a fixed sampling rate; in this embodiment, the analog-to-digital conversion circuit realizes analog-to-digital conversion through the ACM1030 module, and the ACM1030 module realizes high-speed sampling of signals within the ±5V voltage range through the front-end analog signal conditioning circuit. The module uses 2 identical AD sampling and signal conditioning circuits to form a dual-channel high-speed AD sampling circuit. The two ADC circuits are completely independent, with the same structure and component parameters, ensuring that the two channels have high consistency. Each ADC includes a 10-bit data signal (ADC_DATA), a 1-bit clock signal (ADC_CLK), and a 1-bit over-range indication signal (ADC_OVR). The upper limit of the sampling rate of the ACM1030 module is 50Msps, and the sampling rate is equal to the clock frequency. In this embodiment, the sampling rate is fixed at 50Msps, that is, the clock frequency is fixed at 50MHz. When the sampling rate needs to be reduced, it is achieved by decimation and resampling inside the main controller module, instead of directly reducing the clock frequency to reduce the sampling rate. This can avoid affecting the working condition of the sampling and holding circuit inside the ADC chip due to the clock frequency being too low, resulting in a large sampling error.

[0033] The main controller module is used to send a control signal to the variable gain amplifier circuit to adjust the gain of the variable gain amplifier circuit; the main controller module is also used to receive the digital signal of the analog-to-digital conversion circuit through the first-in-first-out buffer circuit; when the sampling rate of the digital signal needs to be adjusted, the main controller module is implemented by extracting and resampling the digital signal; for example, the sampling rate of the digital signal of the analog-to-digital conversion circuit is fixed at 50Msps. If the required sampling rate is 1Msps, the main controller module takes one result for storage or use every 50 sampling data, and the other 49 data are directly discarded, so that the sampling rate of 1Msps can be achieved. In this embodiment, the main controller module uses the EP4CE10 chip as the control chip. The chip is an FPGA device in the CycloneIV series of Altera, with a maximum operating frequency of 200MHz, and has rich resources and flexibility. EP4CE10 has 10320 built-in logic units, integrates a large number of storage units, DSP modules and multiple I / O interfaces, provides extremely high flexibility and programmability, and is suitable for the design of complex system architectures. The chip has 1024KB of configuration memory and up to 512KB of on-chip RAM, and comes with a hardware multiplier, which has excellent performance when processing DSP tasks. It has 292 user I / O pins, a total of 120 interrupts, 8 16-bit timers, and 2 PLL modules. The number of general I / O pins of the chip can meet the configuration requirements of other functional chips in the circuit, and the number of interrupt sources and timers also meets the application requirements of type A ultrasound acquisition equipment. The 2 PLL modules can be used for frequency synthesis and clock management.

[0034] The first-in-first-out cache circuit includes an asynchronous write FIFO and a read FIFO; it also includes an SDRAM controller and an SDRAM; wherein the write FIFO is responsible for caching the digital signal of the analog-to-digital conversion circuit, which is then read and stored in the SDRAM by the SDRAM controller; the read FIFO is responsible for caching the data read from the SDRAM, and outputs it to the main controller module under the control of the SDRAM controller. When the amount of data cached by the write FIFO is greater than the amount of data written in a burst, the digital signal of the analog-to-digital conversion circuit is stopped from being cached; when the amount of data cached by the read FIFO is less than half of the read FIFO cache capacity, the data is stopped from being output to the main controller module; this design effectively solves the problem that read and write operations are easily overlooked, and avoids the phenomenon of data storage or reading omissions caused by the inability to continuously cache the data stream and only intermittent reading and writing of SDRAM data.

[0035] The data transmission module is used to transmit data between the main controller module and the host computer; in this embodiment, the data transmission module implements data transmission by using FX2, which integrates a USB2.0 microprocessor and USB2.0 transceiver, SIE (serial interface engine), an enhanced 8051 microcontroller and a programmable peripheral interface. The original structure of FX2 can achieve a data transmission rate of 480MBit / s. In FX2, the intelligent SIE can handle many USB1.1 and USB2.0 protocols in hardware, thereby reducing development time and ensuring USB compatibility.

[0036] The host computer is used to receive the digital signal of the main controller module through the data transmission module and to send commands to the main controller module to adjust the sampling rate of the digital signal or the amplification factor of the variable gain amplifier circuit; specifically, in this embodiment, the FX2 debugging tool PyUSB is used to send commands to the main controller module to adjust the sampling rate of the digital signal or the amplification factor of the variable gain amplifier circuit.

[0037] The above is only a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principle of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. An ultrasonic echo acquisition system, characterized in that: It includes ultrasonic transceiver module, echo signal processing module, data transmission module and host computer; The ultrasonic transceiver module is used to send ultrasonic signals and receive original echo signals; The echo signal processing module includes a variable gain amplifier circuit, a differential drive circuit, an analog-to-digital conversion circuit, a first-in-first-out buffer circuit, and a main controller module; The variable gain amplifier circuit is used to receive the original echo signal from the ultrasonic transceiver module and amplify the original echo signal to obtain an amplified echo signal; the amplification factor is controlled by the control signal of the main controller module; The differential driving circuit is used for receiving the amplified echo signal and converting the amplified echo signal into a differential signal; The analog-to-digital conversion circuit is used to receive the differential signal, sample the differential signal and convert it into a digital signal with a fixed sampling rate; The main controller module is used to send a control signal to the variable gain amplifier circuit to adjust the gain of the variable gain amplifier circuit; the main controller module is also used to receive the digital signal of the analog-to-digital conversion circuit through the first-in first-out buffer circuit; when the sampling rate of the digital signal needs to be adjusted, the main controller module implements the method of extracting and resampling the digital signal; The data transmission module is used to transmit data between the main controller module and the host computer; The host computer is used to receive the digital signal of the main controller module through the data transmission module and send a command to the main controller module to adjust the sampling rate of the digital signal or the amplification factor of the variable gain amplifier circuit.

2. The ultrasonic echo acquisition system according to claim 1, characterized in that: The first-in-first-out cache circuit includes an asynchronous write FIFO and a read FIFO; it also includes an SDRAM controller and an SDRAM; among them, the write FIFO is responsible for caching the digital signal of the analog-to-digital conversion circuit, which is then read and stored in the SDRAM by the SDRAM controller; the read FIFO is responsible for caching the data read from the SDRAM and outputting it to the main controller module under the control of the SDRAM controller.

3. The ultrasonic echo acquisition system according to claim 2, characterized in that: When the amount of data in the write FIFO buffer is greater than the amount of data written in one burst, the digital signal of the analog-to-digital conversion circuit is stopped from being cached; when the amount of data in the read FIFO buffer is less than half of the read FIFO buffer capacity, the data output to the main controller module is stopped.

4. The ultrasonic echo acquisition system according to claim 1, characterized in that: Ultrasonic transceiver modules include STEVAL-IME011V2.

5. The ultrasonic echo acquisition system according to claim 1, characterized in that: The variable gain amplifier circuit uses AD604 chip as the signal amplifier chip.

6. The ultrasonic echo acquisition system according to claim 1, characterized in that: The differential drive circuit uses the AD8138 chip as the processing chip.

7. The ultrasonic echo acquisition system according to claim 1, characterized in that: The analog-to-digital conversion circuit realizes analog-to-digital conversion through the ACM1030 module.

8. The ultrasonic echo acquisition system according to claim 1, characterized in that: The main controller module uses the EP4CE10 chip as the control chip.

9. The ultrasonic echo acquisition system according to claim 1, characterized in that: The data transmission module realizes data transmission by using FX2.

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