Configurable logic circuit and method based on 1T1R structure

Abstract

According to the configurable logic circuit and method based on the 1T1R structure, the 1T1R structure is adopted as an in-memory operation unit, the number of semiconductor devices is reduced, the circuit structure of storage and calculation is simplified, high-density integration is achieved, the size of an applied chip can be effectively reduced, and the calculation efficiency and energy efficiency are improved. The energy consumption caused by on-chip data transmission is reduced, the configurability and flexibility of the circuit are enhanced, different calculation requirements are met, and the calculation precision is improved. Through the design optimization of the structural units of the circuit, the influence of non-ideal characteristics of hardware is reduced, a new technical scheme is provided for the design of an FPGA chip and other programmable logic devices, and the storage and calculation integrated circuit with a larger scale and lower power consumption can be realized.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor memory, and in particular to a configurable logic circuit and method based on a 1T1R structure. Background Art

[0002] With the rapid development of integrated circuit technology, the demand for high-performance, low-power computing circuits is growing. Traditional computing circuits use separate storage units and computing units, which leads to data transmission delays and increased energy consumption. In-memory computing technology reduces data movement and improves computing efficiency by performing calculations inside the storage unit. The 1T1R (one transistor one memristor) structure has become one of the strong candidate hardware for implementing in-memory computing due to its simple structure and efficient computing power. However, there is currently no efficient logic basic operation unit based on the 1T1R structure to achieve minimum term output. Summary of the invention

[0003] In view of the problems existing in the above-mentioned traditional methods, the present invention proposes a configurable logic circuit based on a 1T1R structure and a configurable logic implementation method based on a 1T1R structure, which can realize an efficient logic basic operation unit with minimum term output, and provide a better choice for combining and realizing more complex logic function calculation functions.

[0004] In order to achieve the above objectives, the embodiments of the present invention adopt the following technical solutions:

[0005] On the one hand, a configurable logic circuit based on a 1T1R structure is provided, including a minimum term outputter, wherein the minimum term outputter includes a 1T1R structure R1, a 1T1R structure R2, a 1T1R structure R3, a 1T1R structure R4, a 1T1R structure R5 and a 1T1R structure R6;

[0006] The top electrode of the 1T1R structure R1 is used to connect to the working power supply, the gate of the 1T1R structure R1 is used to access the first input variable, the bit line electrode of the 1T1R structure R1 is grounded, the top electrode of the 1T1R structure R2 is connected to the bottom electrode of the 1T1R structure R1, the gate of the 1T1R structure R2 is used to access the second input variable, and the bit line electrode of the 1T1R structure R2 is grounded;

[0007] The top electrode of the 1T1R structure R3 is used to connect to the working power supply, the gate of the 1T1R structure R3 is used to access the second input variable, the bit line electrode of the 1T1R structure R3 is grounded, the top electrode of the 1T1R structure R4 is connected to the bottom electrode of the 1T1R structure R1, the gate of the 1T1R structure R4 is connected to the bottom electrode of the 1T1R structure R3, and the bit line electrode of the 1T1R structure R4 is grounded;

[0008] The top electrode of the 1T1R structure R5 is used to access the first input variable, the gate of the 1T1R structure R5 is connected to the gate of the 1T1R structure R2, the bit line electrode of the 1T1R structure R5 is grounded, the top electrode of the 1T1R structure R6 is used to access the first input variable, the gate of the 1T1R structure R6 is connected to the bottom electrode of the 1T1R structure R3, and the bit line electrode of the 1T1R structure R6 is grounded;

[0009] The bottom electrode of the 1T1R structure R2, the bottom electrode of the 1T1R structure R4, the bottom electrode of the 1T1R structure R5 and the bottom electrode of the 1T1R structure R6 serve as minimum term output terminals.

[0010] In one embodiment, the 1T1R structure R1 , the 1T1R structure R2 , the 1T1R structure R3 , the 1T1R structure R4 , the 1T1R structure R5 and the 1T1R structure R6 are all N-channel field effect transistors.

[0011] In one embodiment, the 1T1R structure R1 , the 1T1R structure R2 , the 1T1R structure R3 , the 1T1R structure R4 , the 1T1R structure R5 and the 1T1R structure R6 are all P-channel field effect transistors.

[0012] On the other hand, a configurable logic implementation method based on a 1T1R structure is provided, which is applied to the above-mentioned configurable logic circuit based on a 1T1R structure. The configurable logic implementation method comprises the steps of:

[0013] Connecting the working power supply to the configurable logic circuit based on the 1T1R structure;

[0014] Obtain a first input variable and a second input variable to be calculated;

[0015] Inputting a first input variable into a gate of a 1T1R structure R1, a top electrode of a 1T1R structure R5, and a top electrode of a 1T1R structure R6 of a configurable logic circuit based on a 1T1R structure;

[0016] Inputting the second input variable into the gate of the 1T1R structure R3 of the configurable logic circuit based on the 1T1R structure;

[0017] The minimum terms output after the logic calculation are obtained from the bottom electrode of the 1T1R structure R2, the bottom electrode of the 1T1R structure R4, the bottom electrode of the 1T1R structure R5, and the bottom electrode of the 1T1R structure R6, respectively.

[0018] One of the above technical solutions has the following advantages and beneficial effects:

[0019] The above-mentioned configurable logic circuit and method based on 1T1R structure, by adopting 1T1R structure as the in-memory operation unit, reduces the number of semiconductor devices, simplifies the circuit structure of storage and calculation, realizes high-density integration, can effectively reduce the size of the chip used, improves the computing efficiency and energy efficiency, reduces the energy consumption caused by intra-chip data transmission, enhances the configurability and flexibility of the circuit, adapts to different computing needs, and improves the calculation accuracy. Through the design optimization of the structural unit of the above-mentioned circuit, the influence of the non-ideal characteristics of the hardware is reduced, and a new technical solution is provided for the design of FPGA chips and other programmable logic devices, which is helpful to realize a larger-scale and lower-power storage and calculation integrated circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0021] Figure 1 is a schematic diagram of a structure of a configurable logic circuit based on a 1T1R structure in one embodiment;

[0022] Figure 2 Schematic diagram of a computing unit structure using a 1T1R structure in one embodiment, wherein (a) is a NOT logic computing unit, (b) is an AND logic computing unit, and (c) is an OR logic computing unit;

[0023] Figure 3 Schematic diagram of the calculation logic structure of a combinational logic function in an embodiment, wherein (a) represents an AND calculation logic, (b) represents an OR calculation logic, (c) represents another OR calculation logic, and (d) represents another AND calculation logic;

[0024] Figure 4 The figure is a flowchart of a configurable logic implementation method based on a 1T1R structure in one embodiment. DETAILED DESCRIPTION

[0025] In order to make the purpose, technical scheme and advantages of the present invention clearer, the present invention is further described in detail below in conjunction with the accompanying drawings and Examples. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those generally understood by those skilled in the art of the present invention. The terms used in the specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention.

[0026] It should be noted that the reference to "embodiment" in this article means that the specific features, structures or characteristics described in conjunction with the embodiment may be included in at least one embodiment of the present invention. The presentation of this phrase at various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It will be appreciated by those skilled in the art that the embodiments described herein may be combined with other embodiments. The term "and / or" used in the specification of the present invention and the appended claims refers to any combination of one or more of the associated listed items and all possible combinations, and includes these combinations.

[0027] The following will describe the implementation of the present invention in detail with reference to the accompanying drawings in the embodiment diagram of the present invention.

[0028] In one embodiment, Figure 1 As shown, a configurable logic circuit based on a 1T1R structure is provided, including a minterm outputter, the minterm outputter including a 1T1R structure R1, a 1T1R structure R2, a 1T1R structure R3, a 1T1R structure R4, a 1T1R structure R5 and a 1T1R structure R6. The top electrode of the 1T1R structure R1 is used to connect to a working power supply, the gate of the 1T1R structure R1 is used to access a first input variable, the bit line electrode of the 1T1R structure R1 is grounded, the top electrode of the 1T1R structure R2 is connected to the bottom electrode of the 1T1R structure R1, the gate of the 1T1R structure R2 is used to access a second input variable, and the bit line electrode of the 1T1R structure R2 is grounded.

[0029] The top electrode of the 1T1R structure R3 is used to connect to the working power supply, the gate of the 1T1R structure R3 is used to access the second input variable, the bit line electrode of the 1T1R structure R3 is grounded, the top electrode of the 1T1R structure R4 is connected to the bottom electrode of the 1T1R structure R1, the gate of the 1T1R structure R4 is connected to the bottom electrode of the 1T1R structure R3, and the bit line electrode of the 1T1R structure R4 is grounded. The top electrode of the 1T1R structure R5 is used to access the first input variable, the gate of the 1T1R structure R5 is connected to the gate of the 1T1R structure R2, and the bit line electrode of the 1T1R structure R5 is grounded, the top electrode of the 1T1R structure R6 is used to access the first input variable, the gate of the 1T1R structure R6 is connected to the bottom electrode of the 1T1R structure R3, and the bit line electrode of the 1T1R structure R6 is grounded. The bottom electrode of the 1T1R structure R2, the bottom electrode of the 1T1R structure R4, the bottom electrode of the 1T1R structure R5 and the bottom electrode of the 1T1R structure R6 serve as minimum term output terminals.

[0030] It can be understood that in the storage and computing integrated circuit design, if Figure 2 As shown, the characteristics of the 1T1R structure can be used to design and implement Figure 2 (b) AND, Figure 2(c) OR and Figure 2 (a) The three basic Boolean logic operation units of NOT. These operation units use the characteristics of the 1T1R structure to realize logical operations by controlling the resistance state of the memristor and the switch state of the transistor. That is, the in-memory execution of logical operations can be realized by precisely controlling the resistance state of the memristor and the switch state of the transistor. CC represents the working power supply, GND represents the ground, A represents the first input variable, and B represents the second input variable. These input variables can be specific to application scenarios, such as high-level signal 1 and low-level signal 0 in a digital system.

[0031] In this embodiment, the two-stage 1T1R structure is combined to realize all the minimum terms of the two input variables in actual storage and calculation processing. These minimum term output devices can be combined and expanded to realize any combination of logical functions, providing a basis for the realization of any combination of logical functions. Among them, the logical function can be transformed into the form of the sum of minimum terms (or the transformation form of De Morgan's theorem), for example Figure 3 As shown, Figure 3 (a) represents an AND calculation logic, Figure 3 (b) represents an OR calculation logic, Figure 3 (c) represents another or computational logic, Figure 3 (d) represents another AND calculation logic, which can be Figure 1 The configurable logic circuit combination shown is implemented.

[0032] In this embodiment, the above-mentioned configurable logic circuit based on the 1T1R structure can be integrated into the same chip circuit to form a large-scale storage and computing integrated circuit using one or more minimum term output devices according to the actual computing scale requirements.

[0033] The above-mentioned configurable logic circuit based on the 1T1R structure adopts the 1T1R structure as the in-memory operation unit, reduces the number of semiconductor devices, simplifies the circuit structure of storage and calculation, and realizes high-density integration, which can effectively reduce the size of the chip used, improve the computing efficiency and energy efficiency, reduce the energy consumption caused by intra-chip data transmission, enhance the configurability and flexibility of the circuit, adapt to different computing needs, and improve the calculation accuracy. Through the design optimization of the structural unit of the above-mentioned circuit, the influence of the non-ideal characteristics of the hardware is reduced, and a new technical solution is provided for the design of FPGA chips and other programmable logic devices, which helps to realize a larger-scale and lower-power storage and calculation integrated circuit.

[0034] In one embodiment, the transistors in the 1T1R structure R1 , the 1T1R structure R2 , the 1T1R structure R3 , the 1T1R structure R4 , the 1T1R structure R5 and the 1T1R structure R6 are all N-channel field effect transistors.

[0035] It can be understood that in this embodiment, the transistors in each 1T1R structure are N-channel field effect transistors, that is, NMOS transistors. Figure 1 As shown in , the bit line electrode of each 1T1R structure is the source of the NMOS tube. The 1T1R structure of the NMOS tube type can realize a simple circuit structure and efficient calculation response.

[0036] In one embodiment, the transistors in the 1T1R structure R1 , the 1T1R structure R2 , the 1T1R structure R3 , the 1T1R structure R4 , the 1T1R structure R5 and the 1T1R structure R6 are all P-channel field effect transistors.

[0037] It can be understood that in the present embodiment, the transistors in each 1T1R structure are P-channel field effect transistors, that is, PMOS transistors. Accordingly, the bit line electrode of each 1T1R structure is the drain of the PMOS transistor. The 1T1R structure of the PMOS transistor type can also realize a simple circuit structure and efficient computing response.

[0038] In one embodiment, Figure 4 As shown, a configurable logic implementation method based on a 1T1R structure is also provided, which is applied to the above-mentioned configurable logic circuit based on a 1T1R structure. The configurable logic implementation method may include the following steps:

[0039] S12, turning on the working power supply for the configurable logic circuit based on the 1T1R structure;

[0040] S14, obtaining a first input variable and a second input variable to be calculated;

[0041] S16, inputting the first input variable into the gate of the 1T1R structure R1, the top electrode of the 1T1R structure R5, and the top electrode of the 1T1R structure R6 of the configurable logic circuit based on the 1T1R structure;

[0042] S18, inputting the second input variable into the gate of the 1T1R structure R3 of the configurable logic circuit based on the 1T1R structure;

[0043] S20 , obtaining minimum terms output after logic calculation from the bottom electrode of the 1T1R structure R2 , the bottom electrode of the 1T1R structure R4 , the bottom electrode of the 1T1R structure R5 , and the bottom electrode of the 1T1R structure R6 , respectively.

[0044] It can be understood that turning on the working power supply is to power on the configurable logic circuit based on the 1T1R structure, and connecting V to the corresponding pins of the circuit. CCAfter completing the corresponding circuit initialization (i.e., initializing the state of each 1T1R structure memristor in the circuit), the circuit is ready for the next calculation process, and then the first input variable A and the second input variable B to be calculated can be directly input from the chip to the corresponding terminals of the configurable logic circuit based on the 1T1R structure, so that the state of each 1T1R structure memristor in the circuit changes and generates a corresponding output, and the minimum terms after the circuit logic calculation can be obtained.

[0045] The above-mentioned configurable logic implementation method based on the 1T1R structure reduces the number of semiconductor devices, simplifies the circuit structure of storage and calculation, and realizes high-density integration by adopting the 1T1R structure as the in-memory operation unit, which can effectively reduce the size of the chip used, improve the computing efficiency and energy efficiency, reduce the energy consumption caused by intra-chip data transmission, enhance the configurability and flexibility of the circuit, adapt to different computing needs, and improve the calculation accuracy. Through the design optimization of the structural unit of the above-mentioned circuit, the influence of the non-ideal characteristics of the hardware is reduced, and a new technical solution is provided for the design of FPGA chips and other programmable logic devices, which helps to realize a larger-scale and lower-power storage and computing integrated circuit.

[0046] It can be understood that the explanation of the configurable logic circuit based on the 1T1R structure in this embodiment can be understood by referring to the explanations in the above embodiments of the configurable logic circuit based on the 1T1R structure, and will not be repeated here.

[0047] It should be understood that although Figure 4 The steps in the method are shown in sequence as indicated by the arrows, but the steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of the steps, and the steps can be executed in other orders. Figure 4 At least part of the steps may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily executed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequentially, but can be executed in turn or alternately with other steps or at least part of the sub-steps or stages of other steps.

[0048] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0049] The above embodiments only express several implementation methods of the present invention, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of protection of the invention. It should be pointed out that, for those of ordinary skill in the art, several modifications and improvements can be made without departing from the concept of the present invention, which all belong to the scope of protection of the present invention. Therefore, the scope of protection of the present invention shall be subject to the attached claims.

Claims

1. A configurable logic circuit based on a 1T1R structure, characterized in that: It includes a minimum term exporter, wherein the minimum term exporter includes a 1T1R structure R1, a 1T1R structure R2, a 1T1R structure R3, a 1T1R structure R4, a 1T1R structure R5 and a 1T1R structure R6; The top electrode of the 1T1R structure R1 is used to connect to the working power supply, the gate of the 1T1R structure R1 is used to access the first input variable, the bit line electrode of the 1T1R structure R1 is grounded, the top electrode of the 1T1R structure R2 is connected to the bottom electrode of the 1T1R structure R1, the gate of the 1T1R structure R2 is used to access the second input variable, and the bit line electrode of the 1T1R structure R2 is grounded; The top electrode of the 1T1R structure R3 is used to connect to the working power supply, the gate of the 1T1R structure R3 is used to access the second input variable, the bit line electrode of the 1T1R structure R3 is grounded, the top electrode of the 1T1R structure R4 is connected to the bottom electrode of the 1T1R structure R1, the gate of the 1T1R structure R4 is connected to the bottom electrode of the 1T1R structure R3, and the bit line electrode of the 1T1R structure R4 is grounded; The top electrode of the 1T1R structure R5 is used to access the first input variable, the gate of the 1T1R structure R5 is connected to the gate of the 1T1R structure R2, the bit line electrode of the 1T1R structure R5 is grounded, the top electrode of the 1T1R structure R6 is used to access the first input variable, the gate of the 1T1R structure R6 is connected to the bottom electrode of the 1T1R structure R3, and the bit line electrode of the 1T1R structure R6 is grounded; The bottom electrode of the 1T1R structure R2, the bottom electrode of the 1T1R structure R4, the bottom electrode of the 1T1R structure R5 and the bottom electrode of the 1T1R structure R6 serve as minimum term output terminals.

2. The configurable logic circuit based on the 1T1R structure according to claim 1, characterized in that: The transistors in the 1T1R structure R1, the 1T1R structure R2, the 1T1R structure R3, the 1T1R structure R4, the 1T1R structure R5 and the 1T1R structure R6 are all N-channel field effect transistors.

3. The configurable logic circuit based on 1T1R structure according to claim 1, characterized in that: The transistors in the 1T1R structure R1, the 1T1R structure R2, the 1T1R structure R3, the 1T1R structure R4, the 1T1R structure R5 and the 1T1R structure R6 are all P-channel field effect transistors.

4. A configurable logic implementation method based on 1T1R structure, characterized in that: The configurable logic circuit based on the 1T1R structure according to any one of claims 1 to 3, wherein the configurable logic implementation method comprises the steps of: Connecting a working power supply to the configurable logic circuit based on the 1T1R structure; Obtain a first input variable and a second input variable to be calculated; Inputting the first input variable into the gate of the 1T1R structure R1, the top electrode of the 1T1R structure R5 and the top electrode of the 1T1R structure R6 of the configurable logic circuit based on the 1T1R structure; Inputting the second input variable into the gate of the 1T1R structure R3 of the configurable logic circuit based on the 1T1R structure; The minimum terms output after the logic calculation are respectively obtained from the bottom electrode of the 1T1R structure R2, the bottom electrode of the 1T1R structure R4, the bottom electrode of the 1T1R structure R5, and the bottom electrode of the 1T1R structure R6.

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