Binary translation method and device, electronic equipment and readable storage medium

Abstract

The embodiment of the invention provides a binary translation method and device, electronic equipment and a readable storage medium. The method comprises the following steps: translating and running a first process in a host machine; if it is recognized that the current instruction in the first process is a target instruction and it is determined that the target instruction comprises an operation of modifying a memory of a second process, the target instruction is translated and run, and a target signal is sent to a second translator which translates and runs the second process; wherein the target instruction is used for performing process tracking on the second process; the target signal is used for notifying the second translator to execute invalid operation on translated basic blocks in a code cache region of the second translator. According to the embodiment of the invention, the situation that in the binary translation process, after the tracking process modifies the memory of the tracked process, the dynamic translator executes the unmodified basic blocks stored in the code cache region to cause errors can be avoided, and the accuracy of binary translation operation can be ensured.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and in particular to a binary translation method, device, electronic device and readable storage medium. Background Art

[0002] Binary translation can convert a source program running on one instruction set architecture (ISA) into a target program running on another instruction set architecture to achieve cross-architecture and cross-instruction set program compatibility. The instruction set architecture on which the source program runs is called the GUEST architecture, and the instruction set architecture on which the target program runs is called the HOST architecture. For example, binary translation can enable a program on an x86 architecture platform to run on a LoongArch platform.

[0003] Process tracing is a technology for monitoring and controlling running programs. For example, process A and process B are two client programs that are run through a binary translator, and the basic block TB1 of process B has been translated and cached in the code cache. Process A performs process tracing on process B, modifies the memory of process B, and thereby modifies the source code of TB1, which refers to the executable code that process B runs on the client processor. Since process B cannot perceive that TB1 in the source code has been modified by process A, process B's execution of TB1 is still based on the unmodified TB1 that has been cached in the code cache, which will cause a runtime error in process B. Summary of the invention

[0004] In view of the above problems, an embodiment of the present invention is proposed to provide a binary translation method that overcomes the above problems or at least partially solves the above problems. It can avoid the situation in which, during the binary translation process, the tracking process (first process) modifies the memory of the tracked process (second process), and the dynamic translator causes an operation error due to the unmodified basic blocks stored in the execution code cache area, thereby ensuring the accuracy of the binary translation operation.

[0005] Correspondingly, the embodiment of the present invention also provides a binary translation device, an electronic device, and a computer program product to ensure the implementation and application of the above method.

[0006] In a first aspect, an embodiment of the present invention discloses a binary translation method, which is applied to a first translator, and the method includes:

[0007] Translate and run the first process in the host machine;

[0008] If the current instruction in the first process is identified as a target instruction, and it is determined that the target instruction includes an operation of modifying the memory of the second process, translating and executing the target instruction, and sending a target signal to a second translator that translates and executes the second process;

[0009] The target instruction is used to perform process tracking on the second process; and the target signal is used to notify the second translator to perform invalid operations on the translated basic blocks in its code cache.

[0010] In a second aspect, an embodiment of the present invention discloses a binary translation method, which is applied to a second translator, and the method includes:

[0011] Translate and run the second process in the host machine;

[0012] In the case of receiving a target signal, performing an invalidation operation on the translated basic blocks in the code buffer;

[0013] Among them, the target signal is issued by the first translator when it is translating and running the first process, identifying that the current instruction in the first process is the target instruction, and determining that the target instruction includes an operation to modify the memory of the second process; the target instruction is used to track the process of the second process.

[0014] In a third aspect, an embodiment of the present invention discloses a binary translation device, which is applied to a first translator, and the device includes:

[0015] A first translation and execution module, used for translating and executing a first process in a host machine;

[0016] a target signal sending module, configured to send a target signal to a second translator that translates and runs the second process if a current instruction in the first process is identified as a target instruction and it is determined that the target instruction includes an operation of modifying the memory of the second process;

[0017] The first translation and execution module is further used to translate and execute the target instruction;

[0018] The target instruction is used to perform process tracking on the second process; and the target signal is used to notify the second translator to perform invalid operations on the translated basic blocks in its code cache.

[0019] In a fourth aspect, an embodiment of the present invention discloses a binary translation device, which is applied to a second translator, and the device includes:

[0020] A second translation and execution module, used for translating and executing a second process in a host machine;

[0021] an invalidation operation execution module, for executing an invalidation operation on the translated basic blocks in the code buffer area when receiving a target signal;

[0022] Among them, the target signal is issued by the first translator when it is translating and running the first process, identifying that the current instruction in the first process is the target instruction, and determining that the target instruction includes an operation to modify the memory of the second process; the target instruction is used to track the process of the second process.

[0023] In a fifth aspect, an embodiment of the present invention discloses an electronic device, comprising: a processor, a memory, a communication interface and a communication bus, wherein the processor, the memory and the communication interface communicate with each other through the communication bus; the memory is used to store at least one executable instruction, and the executable instruction enables the processor to execute the steps of the binary translation method as described in any of the above.

[0024] In a sixth aspect, an embodiment of the present invention discloses a readable storage medium, on which a program or instruction is stored, and when the program or instruction is executed by a processor, the binary translation method as described in any of the above can be implemented.

[0025] In a seventh aspect, an embodiment of the present invention discloses a computer program product, including a computer program, which, when executed by a processor, performs the steps of any of the aforementioned binary translation methods.

[0026] The embodiments of the present invention include the following advantages:

[0027] In the process of translating and running a client program in a host machine according to an embodiment of the present invention, when a client program (first process) performs process tracking on another client program (second process), resulting in modification of the memory of the second process, the first translator that translates and runs the first process can identify a target instruction in the first process, and the target instruction is used to perform process tracking on the second process. When the current instruction in the first process is identified as a target instruction, and the target instruction contains an operation to modify the memory of the second process, a target signal is sent to the second translator so that the second translator performs an invalid operation on the translated basic blocks in its code cache. Thus, for the modified basic blocks in the second process, the second translator needs to re-translate the basic blocks before execution, which can avoid the occurrence of operation errors caused by executing the unmodified basic blocks stored in the code cache, and can ensure the accuracy of binary translation operation. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 is a flowchart of a binary translation method embodiment of the present invention;

[0029] Figure 2 is a schematic diagram of translating an executable program running on a client through a dynamic binary translator;

[0030] Figure 3 It is a schematic diagram of the first process in the present invention performing process tracking on the second process by calling the target instruction;

[0031] Figure 4 is a flowchart of another binary translation method embodiment of the present invention;

[0032] Figure 5 is a structural block diagram of an embodiment of a binary translation device of the present invention;

[0033] Figure 6 is a structural block diagram of another binary translation device embodiment of the present invention;

[0034] Figure 7 It is a schematic diagram of the structure of an electronic device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0035] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0036] The terms "first", "second", etc. in the specification and claims of the present invention are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable when appropriate, so that the embodiments of the present invention can be implemented in an order other than those illustrated or described here, and the objects distinguished by "first", "second", etc. are generally of one type, and the number of objects is not limited. For example, the first object can be one or more. In addition, the term "and / or" in the specification and claims is used to describe the association relationship of associated objects, indicating that three relationships can exist. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the objects associated before and after are in an "or" relationship. In the embodiments of the present invention, the term "multiple" refers to two or more, and other quantifiers are similar.

[0037] Binary translation technology can be used to solve the problem of binary-level applications running across instruction set architectures (ISAs). Specifically, binary translation technology can convert an instruction sequence in one instruction set architecture (a first instruction set architecture) into an instruction sequence in another instruction set architecture (a second instruction set architecture).

[0038] In an embodiment of the present invention, the source platform is also referred to as a client platform, and the target platform is also referred to as a host platform or a local platform. The processor of the source platform may be a processor based on a first instruction set architecture. The processor of the target platform may be a processor based on a second instruction set architecture. The second instruction set architecture is a different instruction set architecture from the first instruction set architecture. For example, the first instruction set architecture is a complex instruction set (CISC) architecture, and the second instruction set architecture is a reduced instruction set (RISC) architecture, such as the first instruction set architecture is an x86 instruction set architecture, and the second instruction set architecture is an arm instruction set architecture; for another example, the first instruction set architecture is a reduced instruction set architecture, and the second instruction set architecture is a complex instruction set architecture, such as the first instruction set architecture is an arm instruction set architecture, and the second instruction set architecture is an x86 instruction set architecture; in addition to the above examples, the reduced instruction set architecture also includes a MIPS instruction set architecture, a LoongArch instruction set architecture, PowerPC, RISC-V, etc.

[0039] The client program is an application program developed based on a source platform (client platform). That is, the client program is a program developed based on a first instruction set architecture, so the client program can run normally on the client platform. The target platform (host platform) is a machine platform to which the client program is desired to be transplanted. The client program can be run on the client platform using source binary code. The source binary code is an executable code based on a first instruction set architecture, referred to herein as source code (or client code). If it is desired to run the client program on the target platform, the source binary code needs to be translated into a target binary code. The target binary code is an executable code (or host machine code) based on a second instruction set architecture, so that the target binary code can be run on the target platform. That is, the client program can be run in a binary translation environment in the target platform through binary translation technology.

[0040] Reference Figure 1 , shows a flowchart of a binary translation method embodiment of the present invention, applied to a first translator, the method may include the following steps:

[0041] Step 101: translating and running a first process in a host machine;

[0042] Step 102: If the current instruction in the first process is identified as a target instruction, and it is determined that the target instruction includes an operation of modifying the memory of the second process, the target instruction is translated and executed, and a target signal is sent to a second translator that translates and executes the second process;

[0043] The target instruction is used to perform process tracking on the second process; and the target signal is used to notify the second translator to perform invalid operations on the translated basic blocks in its code cache.

[0044] In the implementation of the present invention, the first translator and the second translator are dynamic binary translators. The first process and the second process are both applications implemented based on the instruction set architecture of the client, that is, the first process and the second process are executable programs (also referred to as source programs) in the client. The first process and the second process can be translated and run in the host machine by the dynamic binary translator. Further, the first process is translated and run in the host machine by the first translator. The second process is translated and run in the host machine by the second translator.

[0045] In the embodiment of the present invention, the first process is also called the tracking process, and the second process is also called the tracked process. The tracking process can track the tracked process through the system call instruction on the client, that is, it can modify the executable code of the tracked process.

[0046] It should be noted that the first translator and the second translator may be two binary translators in a binary translation system; or, the first translator and the second translator may be two translation processes of a binary translator in the binary translation system, also referred to as a first translation process and a second translation process.

[0047] The embodiments of the present invention do not limit the instruction set architecture of the client and the host. For example, the instruction set architecture of the client (hereinafter referred to as the client architecture) is a complex instruction set (CISC) architecture, such as the x86 instruction set architecture; the instruction set architecture of the host (hereinafter referred to as the host architecture) is a reduced instruction set (RISC) architecture, such as the arm instruction set architecture; for another example, the client architecture is a reduced instruction set architecture, and the host architecture is a complex instruction set architecture. In addition to the above examples, the reduced instruction set architecture also includes the MIPS instruction set architecture, the LoongArch instruction set architecture, PowerPC, RISC-V, etc.

[0048] Reference Figure 2 , shows a schematic diagram of translating an executable program running on a client through a dynamic binary translator. Figure 2As shown, the dynamic binary translator uses the "translate and run" method to translate the instructions of the client architecture into the instructions of the host architecture and run them. After the translator reads the executable program of the client platform, it translates and runs it according to the granularity of the basic block, and stores the translated basic blocks in the code cache. The translated basic blocks in the code cache are the host codes obtained after the client code is translated. Before translating a basic block, first search in the code cache. If the basic block that has been translated is found, it will be run directly without re-translating the basic block. If the basic block is not found in the code cache, the basic block is translated and the translated code is stored in the code cache, and then the basic block is executed. After executing the basic block, the next basic block is searched in the code cache, and the cycle is repeated until the program execution ends.

[0049] In the embodiment of the present invention, the first translator is Figure 2 The process shown in the figure translates and runs the first process in the host machine. The second translator follows Figure 2 The process shown translates and runs the second process in the host machine.

[0050] The first translator identifies whether a current instruction to be translated in the first process is a target instruction during the process of translating and running the first process in the host machine. The target instruction is used to perform process tracking on the second process translated and run by the second translator. For example, the target instruction is a system call instruction, and the system call instruction uses a system call provided by the operating system for implementing process tracking.

[0051] System calls are functions provided by the operating system kernel to applications. Since applications generally run in user mode, processes in user mode have many restrictions (such as being unable to perform I / O operations, etc.), so some functions must be completed by the operating system kernel. The operating system kernel can provide system calls to the application layer to complete some tasks that cannot be completed in user mode. System calls need to be called using soft interrupts. In the Linux operating system, system calls are generally called using the "int 0x80" instruction (x86) or the "syscall" instruction (x64).

[0052] Therefore, when the first translator recognizes that the current instruction in the first process is a system call instruction, such as a syscall instruction, and the system call instruction uses a system call provided by the operating system for implementing process tracking, it can be determined that the current instruction is a target instruction.

[0053] Process tracing is a technology for monitoring and controlling running programs. The operating system can provide system calls for implementing process tracing, so that user programs can implement the function of process tracing through these system calls. For example, the Linux operating system provides system calls such as ptrace, which can be used for process tracing. Process tracing can be used for debugging, performance analysis, and system monitoring. By performing process tracing on the target process, the running status and behavior information of the target process can be obtained, so that the target process can be intervened when necessary. Exemplarily, the target process can be tracked using a debugger, such as the memory of the target process can be read or modified by the debugger to implement debugging functions such as breakpoints and single-step execution. For example, the first process can be a debugger, such as GDB (GNU Debugger).

[0054] Ptrace is a system call used to implement process tracing in the Linux operating system. It allows one process to trace and control the execution of another process. This control can be used for debugging purposes, or to implement, for example, a debugger or security monitoring system.

[0055] The embodiment of the present invention does not limit the system call used by the target instruction to implement process tracking. The embodiment of the present invention takes the system call ptrace as an example for explanation, and the processing procedures for other system calls used to implement process tracking are similar and can be referred to each other.

[0056] If the first translator recognizes that the current instruction in the first process is a target instruction, it further determines whether the target instruction includes an operation to modify the memory of the second process. If the target instruction includes an operation to modify the memory of the second process, the executable code of the second process may be modified.

[0057] Reference Figure 3 , which shows a schematic diagram of a first process tracing a second process by calling a target instruction. Figure 3 As shown, the first process is recorded as process A, and the second process is recorded as process B. Assume that a basic block TB1 in process B has been translated and stored in the code cache. Process A tracks process B by calling the target instruction.

[0058] Assume that the target instruction uses the system call ptrace. When the user program (process A) executes the system call ptrace, it will trigger the switch from user mode to kernel mode through the system call instruction (such as the "int 0x80" instruction or the "syscall" instruction), and jump to the corresponding system call processing function in the kernel. In the kernel state, the operating system will execute the corresponding processing function to complete the task requested by the user program, such as modifying the code of TB1 in the executable code of process B. After the system call is executed, the operating system will switch back to the user state again to allow the user program to continue executing. From the entire system call process, it can be seen that process A actively initiates a process tracking system call (such as ptrace) by executing the target instruction to track process B, which will modify the code of TB1 in the executable code of process B; while the modification operation of process B's memory is completed by the kernel, and process B cannot perceive the entire process. In other words, process B cannot perceive that TB1 in the executable code has been modified by process A. Therefore, process B still uses the unmodified TB1 cached in the code cache to execute TB1, which will cause errors in the operation of process B.

[0059] To solve this problem, the present invention further determines whether the target instruction includes an operation of modifying the memory of the second process (such as process B) when the first translator recognizes that the current instruction in the first process (such as process A) is a target instruction. If it is determined that the target instruction includes an operation of modifying the memory of the second process, it is determined that the tracking process (first process) modifies the executable code of the tracked process (second process), and then sends a target signal to the second translator running the second process, and translates and runs the target instruction. The target signal can indicate that the tracked process is modified, and instruct the second translator to perform an invalid operation on the translated basic blocks in its code cache.

[0060] After the second translator receives the target signal, it performs an invalidation operation on the translated basic blocks in the code cache of the second translator. As a result, the translated TB1 in the code cache in the above example will be invalidated, and the second translator needs to re-translate TB1 when executing TB1. At this time, the modified TB1 is re-translated, thereby avoiding the situation where the second translator causes an operation error due to executing the unmodified TB1 in the code cache.

[0061] The invalidation operation may include deleting the translated basic blocks in the code cache of the second translator; or, the invalidation operation may include setting an invalidation flag for the translated basic blocks in the code cache of the second translator, wherein the invalidation flag is used to indicate that the translated basic blocks cannot be used and need to be re-translated.

[0062] Wherein, translating and running the target instruction refers to translating the target instruction of the client architecture into the target instruction of the host architecture and running it. That is, the target instruction of the client architecture is simulated and run on the host machine through the first translator. In the case where the target instruction includes an operation of modifying the memory of the second process, the first translator translates and runs the target instruction, which will cause the memory of the second process to be modified, and further cause the executable code of the second process to be modified. Therefore, the target signal is sent to the second translator to ensure that the second process can run correctly.

[0063] Further, if the first translator recognizes that the current instruction in the first process is not the target instruction; or recognizes that the current instruction is the target instruction, but the target instruction does not include an operation to modify the memory of the second process, then the target instruction is directly translated and executed without sending a target signal to the second translator.

[0064] In an optional embodiment of the present invention, the translating and executing the target instruction may include:

[0065] Step S11, obtaining the first system call number corresponding to the target instruction;

[0066] Step S12, determining a target processing function executed by the target instruction according to the first system call number;

[0067] Step S13, determining a second system call number corresponding to the target processing function under the instruction set architecture of the host machine;

[0068] Step S14: based on the second system call number, translating the target instruction into a system call instruction under the instruction set architecture of the host machine;

[0069] Step S15: running the system call instruction under the instruction set architecture of the host machine.

[0070] The system call number is a unique number defined for each system call in the operating system. When a user program executes a system call, this number is used to indicate which system call to execute, thus ensuring the uniqueness of the system call.

[0071] For system calls with the same function, different system call numbers may be used in different instruction set architectures. For example, for the system call ptrace used for process tracing, the corresponding system call number is 101 in the x86 instruction set architecture, while the corresponding system call number is 117 in the LoongArch instruction set architecture. Therefore, system calls cannot be made directly based on system call number 101 on the host machine.

[0072] The translation and execution of the target instruction requires converting the system call number of the system call used by the target instruction in the client architecture into the system call number in the host architecture.

[0073] First, a first system call number corresponding to the target instruction is obtained, where the first system call number refers to a system call number under a client architecture.

[0074] In an example, assume that the source program includes the following system call instruction: "li v0,5001syscall". The li instruction is used to send 5001 to register v0, and 5001 is the system call number. Syscall indicates that the instruction is a system call instruction. When the system call instruction is translated, the system call number 5001 can be obtained from the system call instruction.

[0075] When the first program executes the target instruction, the system call number is passed to the operating system kernel through a system call instruction such as syscall. The operating system kernel can determine the processing function corresponding to the system call number based on the system call number passed by the user program, and execute the system call by calling the processing function, and return to the user state after the execution is completed.

[0076] In a specific implementation, a system call table may be maintained in the operating system kernel, and the system call table may include the system call number, the name of the processing function, and the entry address of the processing function. Each system call number corresponds to a corresponding processing function, which is used to implement the function of the system call corresponding to the system call number. After entering the kernel state through the system call instruction, the operating system kernel can query the system call table according to the system call number passed by the user program, and then call the corresponding processing function.

[0077] Furthermore, an embodiment of the present invention can store system call tables of different architectures in the operating system kernel of the host machine. Each system call table stores the system call numbers of the instruction set architecture matched by the system call table and the processing functions corresponding to each system call number. After obtaining the first system call number corresponding to the target instruction, the system call table corresponding to the client architecture of the first process is searched in the pre-stored system call tables of different architectures, and the function name of the processing function corresponding to the first system call number is searched in the system call table, assuming that the function name found is ptrace. According to the function name, it can be determined that the target processing function executed by the target instruction is ptrace. Then, according to the name of the target processing function, the system call table corresponding to the host machine architecture is queried to obtain the second system call number (such as 117) corresponding to the target function. Based on the second system call number, the target instruction can be translated into a system call instruction under the instruction set architecture of the host machine; and the system call instruction under the instruction set architecture of the host machine is run.

[0078] The embodiment of the present invention does not limit the specific method of identifying whether the current instruction is a target instruction. In an optional embodiment of the present invention, the method may also include:

[0079] Step S21: if the current instruction in the first process is identified as a system call instruction, obtaining a system call number corresponding to the system call instruction from the current instruction;

[0080] Step S22: compare the system call number with the preset system call number. If they match, determine that the current instruction is the target instruction; otherwise, determine that the current instruction is not the target instruction.

[0081] During the process of the first translator translating and running the first process, if the first translator recognizes that the current instruction in the first process is a system call instruction. For example, if the first process is an application of the x86 instruction set architecture, when the first translator recognizes that the current instruction is a syscall instruction, the current instruction is recognized as a system call instruction. The system call number corresponding to the system call instruction can be obtained from the current instruction, such as the system call number 101.

[0082] The system call number (such as 101) is matched with a preset system call number. The preset system call number is the system call number corresponding to the system call for process tracing. Since the first process is an application of the x86 instruction set architecture, the preset system call number is the system call number of ptrace under the x86 instruction set architecture, that is, 101. The two match, and it can be determined that the current instruction is the target instruction.

[0083] In a specific implementation, for the client instruction set architecture based on the first process, if the client instruction set architecture includes multiple system calls for process tracking, each system call for process tracking corresponds to a different preset system call number. In this case, step S22 can match the system call number obtained in step S21 with multiple preset system call numbers respectively, and if there is a matching preset system call number, the current instruction is determined to be the target instruction.

[0084] Furthermore, since system calls with the same function may correspond to different system call numbers under different instruction set architectures, the first translator may pre-store preset system call numbers corresponding to various system calls for process tracking under different instruction set architectures. In this way, when the first translator recognizes that the current instruction in the first process is a system call instruction, the system call number corresponding to the system call instruction is obtained from the current instruction, and the obtained system call number is matched with the preset system call numbers corresponding to various system calls for process tracking under the client instruction set architecture of the first process. If there is a matching preset system call number, the current instruction is determined to be the target instruction.

[0085] In an optional embodiment of the present invention, sending a target signal to a second translator that translates and runs the second process may include:

[0086] Step S31, extracting the process number of the tracked process from the call parameters of the target instruction;

[0087] Step S32: Send the target signal to the translator corresponding to the process number.

[0088] Taking the target instruction using the system call ptrace as an example, the system call ptrace is defined as follows:

[0089] long ptrace(enum__ptrace_request request,pid_t pid,void*addr,void*data)

[0090] The calling parameters of the target instruction, that is, the parameters of the system call ptrace, include: request, pid, addr and data. Among them, request is used to specify the tracking action. By passing in different request parameters, different tracking operations can be performed on the second process. pid is used to specify the PID of the process to be tracked, such as the process number of the second process. addr is used to specify the memory address to be read or modified. data has different functions for different request parameters.

[0091] Taking the system call ptrace as an example, by extracting the parameter pid, the process number of the traced process (the second process) can be obtained, and then the target signal can be sent to the translator corresponding to the process number.

[0092] A signal is a message sent by a user, system or process to a target process to notify the target process of a state change or system abnormality. The process may perform some related actions in response to the message. The essence of a signal is a soft interrupt.

[0093] Usually, a certain number of signals are reserved in the operating system for application customization, such as the real-time signals SIGRTMIN and SIGRTMAX in the Linux operating system, which represent the minimum and maximum numbers of real-time signals, respectively. The number of the target signal in the embodiment of the present invention can be any one between the minimum number and the maximum number.

[0094] Furthermore, the target signal should be distinguished from the existing general signals. In order to avoid confusion with general signals such as SIGBUS and SIGSEGV indicating program errors, since receiving a SIGSEGV or SIGBUS signal indicates a serious error, the default processing method is to terminate the process, and the embodiment of the present invention hopes that the second translator will invalidate its code buffer instead of terminating the user program. Therefore, the embodiment of the present invention defines a new signal that is different from the above-mentioned general signals as the target signal.

[0095] The embodiment of the present invention does not limit the specific manner of determining whether the target instruction includes an operation of modifying the memory of the second process. In an optional embodiment of the present invention, the method may further include:

[0096] Step S41: if the current instruction in the first process is identified as a target instruction, a target parameter indicating an operation type is obtained from a calling parameter of the target instruction;

[0097] Step S42: If the operation type indicated by the target parameter includes a memory modification operation, determining that the target instruction includes an operation of modifying the memory of the second process.

[0098] Taking the target instruction using the system call ptrace as an example, the call parameters of the target instruction, that is, the parameters of the system call (such as ptrace) used by the target instruction for process tracing. The call parameters include a request parameter, which is used to specify the tracing action. Therefore, the request parameter is the target parameter indicating the operation type.

[0099] If the operation type indicated by the target parameter request includes a memory modification operation, for example, when the request parameter is PTRACE_POKEDATA, it indicates that the system call ptrace is used to perform a write operation on the memory of the traced process (the second process), and the memory of the second process will be modified. Therefore, it can be determined that the target instruction includes an operation of modifying the memory of the second process.

[0100] If the current instruction in the first process is identified as a target instruction, but the call parameter of the target instruction does not include a target operation indicating that the operation type is a memory modification operation, it is determined that the target instruction does not include an operation to modify the executable code of the second process. In this case, the target instruction can be directly translated and executed without sending a target signal to the second translator.

[0101] Reference Figure 4 , shows a flowchart of another binary translation method embodiment of the present invention, applied to a second translator, the method may include the following steps:

[0102] Step 201: translating and running a second process in a host machine;

[0103] Step 202: When receiving the target signal, perform an invalidation operation on the translated basic blocks in the code buffer;

[0104] Among them, the target signal is issued by the first translator when it is translating and running the first process, identifying that the current instruction in the first process is the target instruction, and determining that the target instruction includes an operation to modify the memory of the second process; the target instruction is used to track the process of the second process.

[0105] In an optional embodiment of the present invention, the method before step 201 may further include:

[0106] registering a target signal processing function corresponding to the target signal in the second process, and establishing a binding relationship between the target signal processing function and the target signal; the target signal processing function is used to perform an invalidation operation on the translated basic blocks in the code buffer of the second translator;

[0107] After step 102, the method may further include:

[0108] After receiving the target signal, calling the target signal processing function according to the binding relationship.

[0109] In order to enable the second translator to process the target signal during the translation and operation of the second process, the embodiment of the present invention pre-registers a signal processing function for the target signal (referred to as the target signal processing function) in the second process, and establishes a binding relationship between the target signal processing function and the target signal. After registering the target signal processing function, when the second translator receives the target signal, no matter what state the second process is in, it will stop the current task to execute the target signal processing function.

[0110] In the embodiment of the present invention, in order to process the target signal, the target signal processing function is pre-registered with the kernel in the second process for the target signal. Exemplarily, the embodiment of the present invention uses the sigaction function to register the target signal processing function. The sigaction function includes parameters signum and act. The parameter signum represents the signal to be set, such as the target signal in the embodiment of the present invention. The parameter act is a struct sigaction type pointer, pointing to a struct sigaction data structure, which can describe the processing method of the target signal.

[0111] It is understandable that the present invention does not limit the method of registering the target signal processing function. For example, the target signal processing function can also be registered using the signal function.

[0112] In summary, the binary translation method provided by the embodiment of the present invention, in the process of translating and running a client program in a host machine, when a client program (first process) performs process tracking on another client program (second process), resulting in the modification of the memory of the second process, the first translator that translates and runs the first process can identify the target instruction in the first process, and the target instruction is used to perform process tracking on the second process. When the current instruction in the first process is identified as the target instruction, and the target instruction contains an operation to modify the memory of the second process, a target signal is sent to the second translator so that the second translator performs an invalid operation on the translated basic blocks in its code cache. Thus, for the modified basic blocks in the second process, the second translator needs to re-translate the basic blocks before it can be executed, which can avoid the occurrence of operation errors caused by executing the unmodified basic blocks stored in the code cache, and can ensure the accuracy of binary translation operation.

[0113] It should be noted that, for the sake of simplicity, the method embodiments are described as a series of action combinations, but those skilled in the art should be aware that the embodiments of the present invention are not limited by the order of the actions described, because according to the embodiments of the present invention, certain steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in the specification are all preferred embodiments, and the actions involved are not necessarily required by the embodiments of the present invention.

[0114] Reference Figure 5 , shows a structural block diagram of an embodiment of a binary translation device of the present invention, the device is applied to a first translator, and the device may include:

[0115] A first translation and execution module 501, used for translating and executing a first process in a host machine;

[0116] A target signal sending module 502 is used to send a target signal to a second translator that translates and runs the second process if the current instruction in the first process is identified as a target instruction and it is determined that the target instruction includes an operation of modifying the memory of the second process;

[0117] The first translation and execution module 501 is further used to translate and execute the target instruction;

[0118] The target instruction is used to perform process tracking on the second process; and the target signal is used to notify the second translator to perform invalid operations on the translated basic blocks in its code cache.

[0119] Optionally, the device further comprises:

[0120] A system call number extraction module, configured to obtain a system call number corresponding to the system call instruction from the current instruction if the current instruction in the first process is identified as a system call instruction;

[0121] The target instruction determination module is used to compare the system call number with the preset system call number. If they match, it is determined that the current instruction is the target instruction; otherwise, it is determined that the current instruction is not the target instruction.

[0122] Optionally, the device further comprises:

[0123] a parameter extraction module, configured to obtain a target parameter indicating an operation type from a call parameter of the target instruction if the current instruction in the first process is identified as a target instruction;

[0124] The operation determination module is used to determine that the target instruction includes an operation of modifying the memory of the second process if the operation type indicated by the target parameter includes a memory modification operation.

[0125] Optionally, the target signal sending module is specifically configured to:

[0126] Extract the process number of the tracked process from the calling parameters of the target instruction; and send the target signal to the translator corresponding to the process number.

[0127] Optionally, the first translation execution module is specifically used to:

[0128] Obtain a first system call number corresponding to the target instruction; determine a target processing function executed by the target instruction according to the first system call number; determine a second system call number corresponding to the target processing function under the instruction set architecture of the host machine; based on the second system call number, translate the target instruction into a system call instruction under the instruction set architecture of the host machine; and run the system call instruction under the instruction set architecture of the host machine.

[0129] Optionally, the first translation execution module is further used for:

[0130] If it is identified that the current instruction in the first process is not a target instruction; or if it is identified that the current instruction in the first process is a target instruction and it is determined that the target instruction does not include an operation of modifying the memory of the second process, the target instruction is translated and executed.

[0131] Reference Figure 6 , shows a structural block diagram of another binary translation device embodiment of the present invention, the device is applied to a second translator, and the device may include:

[0132] The second translation and execution module 601 is used to translate and execute the second process in the host machine;

[0133] A signal receiving and processing module 602 is used to perform an invalidation operation on the translated basic blocks in the code buffer when a target signal is received;

[0134] Among them, the target signal is issued by the first translator when it is translating and running the first process, identifying that the current instruction in the first process is the target instruction, and determining that the target instruction includes an operation to modify the memory of the second process; the target instruction is used to track the process of the second process.

[0135] Optionally, the device further comprises:

[0136] a function registration module, used for registering a target signal processing function corresponding to the target signal in the second process, and establishing a binding relationship between the target signal processing function and the target signal; the target signal processing function is used for performing an invalidation operation on the translated basic blocks in the code buffer of the second translator;

[0137] A function calling module is used to call the target signal processing function according to the binding relationship after receiving the target signal.

[0138] The binary translation device provided by the embodiment of the present invention, in the process of translating and running a client program in a host machine, when a client program (first process) performs process tracking on another client program (second process), resulting in the modification of the memory of the second process, the first translator that translates and runs the first process can identify the target instruction in the first process, and the target instruction is used to perform process tracking on the second process. When the current instruction in the first process is identified as the target instruction, and the target instruction contains an operation to modify the memory of the second process, a target signal is sent to the second translator so that the second translator performs an invalid operation on the translated basic blocks in its code cache. Thus, for the modified basic blocks in the second process, the second translator needs to re-translate the basic blocks before execution, which can avoid the occurrence of operation errors caused by executing the unmodified basic blocks stored in the code cache, and can ensure the accuracy of binary translation operation.

[0139] As for the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0140] Reference Figure 7 , is a schematic diagram of the structure of an electronic device provided by an embodiment of the present invention. Figure 7 As shown, the electronic device includes: a processor, a memory, a communication interface and a communication bus, and the processor, the memory and the communication interface communicate with each other through the communication bus; the memory is used to store at least one executable instruction, and the executable instruction enables the processor to execute the steps of the binary translation method of the above-mentioned embodiment.

[0141] An embodiment of the present invention provides a non-transitory computer-readable storage medium. When instructions in the storage medium are executed by a program or a processor of a terminal, the terminal is enabled to perform the steps of the binary translation method of the aforementioned embodiment.

[0142] An embodiment of the present invention provides an electronic device, including:

[0143] A host processor executes host programs;

[0144] A memory for storing a client program;

[0145] a binary translation system that translates the guest program into a host program that runs on the host processor; and

[0146] A code cache that stores translated basic blocks of client programs;

[0147] The binary translation system is configured as follows:

[0148] Determine that the tracking process in the client program modifies the executable code of the tracked process;

[0149] Sending, by a first translation process corresponding to the tracking process, to a second translation process corresponding to the tracked process, a target signal indicating that the tracked process has been modified; and

[0150] In response to the target signal, the second translation process performs an invalidation operation on the translated basic blocks of the tracked process in the code cache.

[0151] Optionally, the tracking process modifies the executable code of the tracked process through a system call instruction on the client, and the binary translation system determines whether the executable code of the tracked process is modified through a call parameter of the system call instruction.

[0152] Optionally, the binary translation system defines the target signal in the host machine, registers a target signal processing function corresponding to the target signal; and in response to the target signal, performs an invalidation operation on the translated basic blocks of the tracked process in the code cache area through the target signal processing function.

[0153] Optionally, the binary translation system extracts the process number of the tracked process from the call parameters of the system call instruction, and sends the target signal according to the process number.

[0154] The embodiment of the present invention provides a binary translation program product, which translates an executable program on a client machine having a different instruction set architecture ISA from a host machine into a host machine program according to basic blocks, and stores the translated basic blocks in a code cache area;

[0155] The binary translation system is further configured as follows:

[0156] Simulate the system call instructions of the tracing process on the client on the host machine;

[0157] When it is determined that the tracking process modifies the memory of the tracked process through the system call instruction, the first translation process corresponding to the tracking process sends a target signal to the second translation process corresponding to the tracked process; and

[0158] In response to the target signal, the second translation process performs an invalidation operation on the translated basic blocks of the tracked process in the code cache.

[0159] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0160] It will be appreciated by those skilled in the art that the embodiments of the present invention may be provided as methods, devices, or computer program products. Therefore, the embodiments of the present invention may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the embodiments of the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program codes.

[0161] The embodiments of the present invention are described with reference to the flowcharts and / or block diagrams of the methods, terminal devices (systems), and computer program products according to the embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of the processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing terminal device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing terminal device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0162] These computer program instructions may also be stored in a computer readable memory capable of directing a computer or other programmable data processing terminal device to operate in a predictable manner, so that the instructions stored in the computer readable memory produce a manufactured product including an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0163] These computer program instructions can also be loaded onto a computer or other programmable data processing terminal device so that a series of operating steps are executed on the computer or other programmable terminal device to produce a computer-implemented process, thereby providing instructions for executing on the computer or other programmable terminal device to implement the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0164] Finally, it should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or terminal device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or terminal device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or terminal device including the elements.

[0165] Specific examples are used herein to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. At the same time, for those skilled in the art, according to the idea of ​​the present invention, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present invention.

Claims

1. A binary translation method, characterized in that: Applied to a first translator, the method comprises: Translate and run the first process in the host machine; If the current instruction in the first process is identified as a target instruction, and it is determined that the target instruction includes an operation of modifying the memory of the second process, translating and executing the target instruction, and sending a target signal to a second translator that translates and executes the second process; The target instruction is used to perform process tracking on the second process; and the target signal is used to notify the second translator to perform invalid operations on the translated basic blocks in its code cache.

2. The method according to claim 1, characterized in that: The method further comprises: If the current instruction in the first process is identified as a system call instruction, obtaining a system call number corresponding to the system call instruction from the current instruction; The system call number is compared with a preset system call number, and if they match, it is determined that the current instruction is a target instruction; otherwise, it is determined that the current instruction is not a target instruction.

3. The method according to claim 1, characterized in that The method further comprises: If the current instruction in the first process is identified as a target instruction, obtaining a target parameter for indicating an operation type from a call parameter of the target instruction; If the operation type indicated by the target parameter includes a memory modification operation, it is determined that the target instruction includes an operation of modifying the memory of the second process.

4. The method according to claim 1, characterized in that: The sending of the target signal to the second translator that translates and runs the second process comprises: Extracting the process number of the tracked process from the call parameters of the target instruction; The target signal is sent to the translator corresponding to the process number.

5. The method according to claim 1, characterized in that The translation runs the target instruction, including: Obtaining a first system call number corresponding to the target instruction; Determine a target processing function executed by the target instruction according to the first system call number; Determine a second system call number corresponding to the target processing function under the instruction set architecture of the host machine; Based on the second system call number, translating the target instruction into a system call instruction under the instruction set architecture of the host machine; Run the system call instruction under the instruction set architecture of the host machine.

6. The method according to claim 1, characterized in that The method further comprises: If it is identified that the current instruction in the first process is not a target instruction; or if it is identified that the current instruction in the first process is a target instruction and it is determined that the target instruction does not include an operation of modifying the memory of the second process, the target instruction is translated and executed.

7. A binary translation method, characterized in that: Applied to the second translator, the method comprises: Translate and run the second process in the host machine; In the case of receiving a target signal, performing an invalidation operation on the translated basic blocks in the code buffer; Among them, the target signal is issued by the first translator when it is translating and running the first process, identifying that the current instruction in the first process is the target instruction, and determining that the target instruction includes an operation to modify the memory of the second process; the target instruction is used to track the process of the second process.

8. The method according to claim 7, characterized in that The method further comprises: registering a target signal processing function corresponding to the target signal in the second process, and establishing a binding relationship between the target signal processing function and the target signal; the target signal processing function is used to perform an invalidation operation on the translated basic blocks in the code buffer of the second translator; After receiving the target signal, calling the target signal processing function according to the binding relationship.

9. An electronic device, characterized in that: include: A processor, a memory, a communication interface and a communication bus, wherein the processor, the memory and the communication interface communicate with each other via the communication bus; The memory is used to store at least one executable instruction, and the executable instruction enables the processor to execute the steps of the binary translation method as described in any one of claims 1 to 6 or 7 to 8.

10. A computer program product, comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the binary translation method according to any one of claims 1 to 6 or 7 to 8 are performed.

11. An electronic device, comprising: A host processor executes host programs; A memory for storing a client program; A binary translation system that translates the client program into a host program that runs on the host processor; as well as A code cache that stores translated basic blocks of client programs; The binary translation system is configured as follows: Determine that the tracking process in the client program modifies the executable code of the tracked process; A target signal indicating that the tracked process is modified is sent by a first translation process corresponding to the tracking process to a second translation process corresponding to the tracked process; as well as In response to the target signal, the second translation process performs an invalidation operation on the translated basic blocks of the tracked process in the code cache.

12. The electronic device according to claim 11, wherein: The tracking process modifies the executable code of the tracked process through the system call instruction on the client, and the binary translation system determines whether the executable code of the tracked process is modified through the call parameters of the system call instruction.

13. The electronic device according to claim 12, wherein: The binary translation system defines the target signal in the host machine and registers a target signal processing function corresponding to the target signal; And in response to the target signal, an invalidation operation is performed on the translated basic blocks of the traced process in the code cache area through the target signal processing function.

14. The electronic device according to claim 12, wherein: The binary translation system extracts the process number of the tracked process from the call parameters of the system call instruction, and sends the target signal according to the process number.

15. A binary translation program product that translates an executable program on a client machine having a different instruction set architecture ISA from that of a host machine into a host machine program by basic blocks, and stores the translated basic blocks in a code cache; The binary translation system is further configured as follows: Simulate the system call instructions of the tracing process on the client on the host machine; When it is determined that the tracking process modifies the memory of the tracked process through the system call instruction, a first translation process corresponding to the tracking process sends a target signal to a second translation process corresponding to the tracked process; as well as In response to the target signal, the second translation process performs an invalidation operation on the translated basic blocks of the tracked process in the code cache.

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