IP (Internet Protocol) cascade frame-level communication method and communication device suitable for narrow floorplan

Abstract

According to the IP cascading frame-level communication method and communication device suitable for the narrow floorplan, communication of a large amount of data is achieved among different IPs in a chip with the narrow floorplan layout through the steps of communication coding and bus communication, so that the number of connecting lines among the different IPs is remarkably reduced, the number of Placement Routes during winding is reduced, the winding difficulty is reduced, and the communication efficiency is improved. Therefore, the working difficulty of the rear end Physical Design of the chip is reduced; meanwhile, the communication method can be used for configuring the master-slave number, the data transmission length and the data transmission type on hardware, and has the advantages of being small in bus number, simple in protocol and the like.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor display driving and image processing, and in particular relates to a frame-level communication method and a communication device suitable for IP cascading of a narrow floorplan. Background Art

[0002] With the widespread popularity of smart terminals (such as smartphones) and wearable devices (such as VR glasses), in order to meet the characteristics of electronic products, thinness, lightness and portability, more and more stringent physical size requirements are put forward for the chips used in electronic products. For example, most of the current electronic products have LED screens or OLED screens, and the display driver chip (DDIC, Display Drive IC) that drives the screen display is often designed to present a narrow physical size chip structure due to the location requirements and the need to drive the pixel display circuit of the entire display panel.

[0003] In chips with this specific size layout, multiple ISPIPs are often required to be cascaded for video image processing, and a large amount of frame-level data needs to be frequently transmitted between multiple IPs (Intellectual Properties). Under the constraints of this specific floorplan, data is transmitted between IPs using direct point-to-point transmission or according to ordinary bus protocols. There are disadvantages such as low communication rate, too many lines between IPs, and high difficulty in layout and routing. Ultimately, it is difficult for chip products to unleash their full performance, or the chip design size is increased due to area reasons, or the product's battery life is affected due to power consumption reasons, thereby reducing the chip's performance and cost-effectiveness, and ultimately seriously affecting the user experience.

[0004] Therefore, how to design a bus protocol that can meet the requirements of frame-based data transmission while taking into account the requirements of area, power consumption and communication rate under the physical constraints of a narrow floorplan layout and the logical constraints of IP cascading is an urgent problem to be solved. Summary of the invention

[0005] In view of this, the present invention provides a frame-level communication method and a communication device suitable for IP cascading of a narrow floorplan, so as to solve the problem that bus communication in the chip narrow floorplan physical layout and IP cascading scenario is difficult to take into account the area, power consumption, communication rate and back-end physical design.

[0006] To achieve the above object, the present invention provides a frame-level communication method for IP cascading of a narrow floorplan, wherein the narrow floorplan is formed by cascading IP_1, IP_2, ..., IP_i, where 1≤i≤M, and M is a positive integer, and comprises the following steps:

[0007] Step (1), communication coding: Encode the IPs at each level of the data link in the narrow floorplan and the data packets that the IPs at each level need to communicate, to form i data packet sets, denoted as N_1, N_2, ..., N_i;

[0008] Step (2), bus communication: starting bus communication according to the frame level signal and the communication start signal, and the bus presents distributed control during the communication process;

[0009] In the communication process, the IP_i transmits the data packet set N_i to the next-level IP_i+1 according to the bus protocol, and the IP_i+1 transmits the data packet set N_i+1 to the next-level IP_i+2 according to the bus protocol.

[0010] Furthermore, in step (2), the IP_i+1 verifies and intercepts the data packets received by the IP at the same level in the data packet set N_i.

[0011] Furthermore, in the step (2), the IP_i+1 intercepts and / or inserts the data packets that the IP_i+1 needs to send based on the data packet set N_i to form the new data packet set N_i+1.

[0012] Furthermore, the IP_i is an IP in any tool such as ASIC, FPGA or EDA.

[0013] Furthermore, the IP_i is a self-designed IP.

[0014] Furthermore, the IP_1, IP_2, ..., IP_i are connected in series in a daisy chain or in a ring connection.

[0015] Furthermore, the frame-level signal is a field synchronization signal in video image processing (ISP), or a periodic synchronization signal that requires periodic data processing.

[0016] Furthermore, the frame-level signal is a synchronization signal that needs to be processed only when powered on.

[0017] Furthermore, the bus communication is bus communication between IPs in the internal digital design of an ASIC / FPGA chip.

[0018] Furthermore, the bus communication is half-duplex communication.

[0019] Furthermore, the bus protocol includes a bus control signal and a bus data signal.

[0020] Furthermore, the verification algorithm is an error correction code ECC or a cyclic redundancy check code CRC.

[0021] At the same time, the present invention also provides a communication device using the above communication method, wherein the narrow floorplan is formed by cascading IP_1, IP_2, ..., IP_i, wherein 1≤i≤M, and M is a positive integer.

[0022] Furthermore, the IP_1, IP_2, ..., IP_i are connected in series in a daisy chain or in a ring connection.

[0023] Compared with the prior art, the present invention has the following beneficial effects:

[0024] In a chip with a narrow floorplan layout, in a scenario where a large amount of data communication needs to be performed between IPs on a frame or timing basis, the present invention can significantly reduce the number of connections between different IPs, reduce the number of Place and Route wiring, reduce the difficulty of wiring, and thus reduce the difficulty of Physical Design work at the back end of the chip; at the same time, the communication method can configure the number of masters and slaves, the length and type of data transmission in hardware, and has the advantages of a small number of buses, a simple protocol, etc. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0026] Figure 1 An example of encoding IP and communication data packets of the present invention;

[0027] Figure 2 A bus interface for cascading between IPs of the present invention;

[0028] Figure 3 The data packet encoding protocol of the present invention;

[0029] Figure 4A This is a waveform diagram of IP_1 sending a data packet according to the present invention;

[0030] Figure 4B This is a waveform diagram of IP_1 sending 2 data packets according to the present invention;

[0031] Figure 4C It is a waveform diagram of IP_1 sending multiple data packets according to the present invention;

[0032] Figure 5A schematic diagram of IP_1 sending multiple dp in the present invention;

[0033] Fig. 6A A schematic diagram of adding 1 dp_q after IP_2 reads dp_n of the present invention;

[0034] Figure 6B The datasequence diagram of adding only 2 dp (dp_i, dp_j) to IP_2 of the present invention;

[0035] Figure 7 It is a schematic diagram of the bus communication process between IPs at various levels in the present invention. DETAILED DESCRIPTION

[0036] One of the core points of the present invention is to provide a frame-level communication method and device for IP cascading suitable for a narrow floorplan, so as to solve the problem that bus communication in the chip narrow floorplan physical layout and IP cascading scenario is difficult to balance the area, power consumption, communication rate and back-end physical design.

[0037] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0038] The frame-level communication method and device for IP cascading of a narrow floorplan disclosed in this embodiment are applied to semiconductor display driving and image processing, which can be understood by those skilled in the art. The communication method and device of the present invention can be applied to electronic products. Electronic products can be implemented in various forms, including but not limited to mobile phones, tablets, computers, wearable devices, etc. The subsequent description will be explained by taking a smart phone as an example, and relevant technical personnel in the field should believe that, in addition to components specifically used for mobile phones, implementation methods designed according to the present invention also belong to the present invention.

[0039] Embodiment 1

[0040] A frame-level communication method for IP cascading applicable to a narrow floorplan disclosed in an embodiment of the present invention comprises the following steps:

[0041] Step (1) Communication encoding: encoding the IP addresses of each level of the data link in the narrow floorplan and the data packets that need to be communicated;

[0042] In step (1), it is assumed that there are M IPs that need to communicate in the data link (communication includes sending and receiving), where 1≤i≤M, and M is a positive integer. Figure 1 The following is an example of the IP addresses of each level of the data link and the data packet encoding required for communication in a narrow floorplan, such as Figure 1 As shown in the figure, the meanings of each item are as follows:

[0043] IPindex: indicates the index number of the IP according to the direction of data flow on the communication link;

[0044] IPname: indicates the name of the IP that needs to communicate;

[0045] Tx / Rx: Indicates whether the IP is a sender or a receiver during the communication process. Tx indicates the sender, and Rx indicates the receiver. Tx / Rx means that the IP can both send and receive data.

[0046] mip_id: indicates the encoding of the master IP (masterip, mip);

[0047] Ni: indicates how many packets the IP has in total;

[0048] data_id: indicates the encoding of the data packet. Note that this encoding is only for the transmitted data packet. If the IP needs to receive data packets, it can be identified and received according to the encoding rules (such as mip_id and data_id), so there is no need to encode the received data packets.

[0049] data_num: indicates how many other IPs will receive the data packet;

[0050] Data size: indicates the packet capacity of the data packet during communication.

[0051] It should be noted that, in the naming of the present invention, the signal name with an underscore “_” in the name is included in the bus signal.

[0052] Figure 1 The encoding example of IP and communication data packets of the present invention is shown. Figure 1 Taking the first column as an example, IP_1 is the sender IP, the index code of the IP is 1, and it contains 3 data packets. The codes of the above 3 data packets are 1, 2, and 3, and the sizes of the 3 data packets are 8 bytes, 16 bytes, and 18 bytes respectively; the data packets with the codes of 1, 2, and 3 need to be transmitted to 1 other IP, 1 other IP, and 2 other IPs respectively, that is, they are received by 1 other IP, 1 other IP, and 2 other IPs in turn.

[0053] Similarly, see Figure 1 In the second column, IP_2 is the receiving IP. The index code of this IP is 2, and it contains 1 data packet. Since it is a passive receiving IP, data_id and data_num are not encoded.

[0054] See also Figure 1 In the third column, IP_3 is both the receiving IP and the sending IP. The IPid is encoded as 3 and contains 4 data packets. The encoding decibels of the two sent data packets are 1 and 2, which are received by the other 3 IPs and 4 IPs respectively. The data packet sizes are 4 bytes and 10 bytes respectively. The other two data packets are received data packets and are not encoded.

[0055] In step (1), it should also be noted that the first-level IP on the data link may not need to communicate with the subsequent IP, but at this time the first-level IP is still the starting point for the VCB bus to generate communication signals, the bus control signal is still generated by the first-level IP, and the data signal can be ignored.

[0056] It should be noted that the narrow floorplan in this embodiment is not limited to chips with narrow and long physical structures, but can also be applied to floorplan circuits in non-narrow and long chips that require narrow constraints or arrangements.

[0057] Step (2) bus communication: starting bus communication according to the frame level signal and the communication start signal, and the bus presents distributed control during the communication process;

[0058] In step (2), the frame-level signal and the transmission start signal can be either a signal sent or received by the ISP in a frame-by-frame manner or a signal that needs to be sent or received only when the power is turned on. The bus uses 19 wires for transmission, including 3 control wires and 16 data wires. Figure 2 As shown, the definition is as follows:

[0059] psf: packet start flag (or packet header, ph), which is the bus control signal, indicating the start signal of data

[0060] ·Token: Transmission token, which is a bus control signal, indicating whether the IP releases the right to use the bus. When token is high, it means that the IP will release the right to control the bus. Token will be passed between IPs at all levels.

[0061] vld: bus control signal, valid identifier of data transmission

[0062] data[15:0]: bus data signal

[0063] At the beginning of the transmission, ph is pulled high for one cycle, vld is pulled high synchronously with data, token is high at the last cycle of the transmission, and vld is low in the idle state. The definition of data in the transmission is as follows Figure 3 As shown below:

[0064] mip_id: masteripid, 6 bits, indicating the ID of the master in transmission

[0065] data_id: data id, 6 bits, indicating the group of data transmitted by the master this time

[0066] data_num: data id number, 4 bits, indicating how many slaves will receive the data id during transmission. Each time the slave IP receives the data, data_num decreases by one.

[0067] data: 2n bytes, indicating the data to be transmitted. If the transmitted data is not an integer multiple of 2n bytes,

[0068] You need to add dummy data

[0069] During the transmission process, the previous level IP will release the token after the data transmission is completed, and the token will be passed to the next level IP. Therefore, the bus transmission process presents the characteristics of distributed control.

[0070] In addition, when data transmission starts, IP_1 first occupies the bus and sends out data packets to other IPs (supports multiple data packets). Vld is pulled high only during the valid period of each data_packet and pulled low when idle. The first clock cycle of each packet will pull up the packet header, and the last clock cycle of the last data packet will pull up the token for one pulse cycle.

[0071] Figure 4A The waveform diagram of IP_1 sending a data packet is shown below. Figure 4B The figure shows the waveform diagram of IP_1 sending 2 data packets. Figure 4C The figure shows a waveform diagram of IP_1 sending multiple data packets. Figure 4A , Figure 4B , Figure 4CThe bus data in is represented in the form of data_i_j, where i in data_i_j represents the number of data packets, and j represents the jth data in the i-th data packet. At the same time, in order to conveniently describe the relative timing relationship of the data packet (data packer, dp) in the bus, Figure 4C Can be converted into Figure 5 The diagram shown is a schematic diagram of IP_1 sending multiple DPs.

[0072] IP_2 receives the data packet from IP_1, and chooses whether to receive the data in the packet according to the mip_id and data_id in the packet. The data to be received is received according to the mip_id and data_id parsed from the bus psf signal, vld signal and bus data signal, and the bus data_num signal is readjusted (data_num is decremented by 1). The data that does not need to be received or the data that still needs to be transmitted after receiving will be passed on to the next level IP. At the same time, if IP_2 also needs to transmit data to the next level IP, the datapacket to be sent can be added to the datasequence in data packets.

[0073] Fig. 6A The sequence diagram of adding a dp_q after IP_2 reads dp_n in the data sequence (assuming that data_num of dp_n = 1 and is only read by IP_2). Figure 6B The schematic diagram shows the sequence of adding only two dp (dp_i, dp_j) in the data sequence of IP_2. During the data transmission process, the bus signal of IP_2 changes according to the VCB bus protocol.

[0074] Some IPs on the data link may not need to send data, so they directly transmit the token to the next-level IP. At this time, the bus control signals vld and psf are all 0. The above possible bus communication process is summarized as follows: Figure 7 The figure shows the bus communication process between IPs. IP_1 sends two data packets (dp_m, dp_n). After receiving the data packet from IP_1, IP_2 only adds two data packets (dp_i, dp_j, where data_num of dp_i=1). After receiving the data packet from IP_2, IP_3 reads dp_i. After receiving the data packet from IP_3, IP_4 transmits the data packet intact to IP_5.

[0075] During the bus transmission process, verification can be performed based on the theoretical value of data_num when each level of IP receives the bus data.

[0076] Optionally, the verification algorithm of this embodiment may be an error correction code ECC, or a cyclic redundancy check code CRC, or other data verification algorithms in the prior art, which is not specifically limited in the present invention.

[0077] It should be noted that the frame-level signal described in this embodiment is not limited to the field synchronization signal in video image processing (ISP), but can also be applicable to periodic synchronization signals that need to be processed periodically, and can also be synchronization signals that need to be processed only when powered on. In addition, the bus signal in this implementation is only applicable to bus communication between IPs in the internal digital design of ASIC / FPGA chips, and does not involve pins or interface circuits outside the chip, and does not require the electrical characteristics of the cables or interfaces of the physical entity.

[0078] Embodiment 2

[0079] Figure 2 A communication device using the communication method described in Embodiment 1 is shown. Figure 2 The narrow floorplan layout includes M IPs, IP_1, IP_2, ..., IP_i are connected in a ring relationship, that is, IP_M can also communicate with IP_1, where 1≤i≤M, and M is a positive integer.

[0080] Optionally, the connection relationship between IP_1, IP_2, ..., IP_i is not limited to a ring connection relationship, but can also be a daisy chain serial connection form, or a cascade connection form.

[0081] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to be limiting. Depending on the different requirements of the bus in actual applications, the control signal and data signal of the bus can be changed, and the data verification algorithm can be appropriately added. Although the present technical invention has been described in detail with reference to the embodiments, a person of ordinary skill in the art should understand that the above-mentioned embodiments are specific embodiments for realizing the present invention, and in actual applications, various changes can be made to them in form and detail without departing from the spirit and scope of the present invention.

Claims

1. A frame-level communication method for IP cascading of a narrow floorplan, wherein the narrow floorplan is formed by cascading IP_1, IP_2, ..., IP_i, wherein: 1≤i≤M, M is a positive integer, characterized in that it includes the following steps: Step (1), communication coding: Encode the IPs at each level of the data link in the narrow floorplan and the data packets that the IPs at each level need to communicate, to form i data packet sets, denoted as N_1, N_2, ..., N_i; Step (2), bus communication: starting bus communication according to the frame level signal and the communication start signal, and the bus presents distributed control during the communication process; In the communication process, the IP_i transmits the data packet set N_i to the next-level IP_i+1 according to the bus protocol, and the IP_i+1 transmits the data packet set N_i+1 to the next-level IP_i+2 according to the bus protocol.

2. The method according to claim 1, characterized in that In the step (2), the IP_i+1 verifies and intercepts the data packets received by the IP at the same level in the data packet set N_i.

3. The method as claimed in claim 2 is characterized in that, in the step (2), the IP_i+1 intercepts and / or inserts the data packets that the IP_i+1 needs to send based on the data packet set N_i to form the new data packet set N_i+1.

4. The method according to claim 1, characterized in that The IP_i is an IP in any tool such as ASIC, FPGA or EDA.

5. The method according to claim 1, characterized in that The IP_i is a self-designed IP.

6. The method according to claim 1, characterized in that The IP_1, IP_2, ..., IP_i are connected in series in a daisy chain or in a ring connection.

7. The method according to claim 1, characterized in that The frame-level signal is a field synchronization signal in video image processing (ISP), or a periodic synchronization signal that requires periodic data processing.

8. The method according to claim 1, characterized in that The frame-level signal is a synchronization signal that needs to be processed only when power is turned on.

9. The method according to claim 1, characterized in that The bus communication is the bus communication between IPs in the internal digital design of the ASIC / FPGA chip.

10. The method according to claim 1, characterized in that The bus communication is half-duplex communication.

11. The method according to claim 1, characterized in that The bus protocol includes a bus control signal and a bus data signal.

12. The method according to claim 2, characterized in that The verification algorithm is an error correction code ECC or a cyclic redundancy check code CRC.

13. A communication device using a frame-level communication method for IP cascading applicable to a narrow floorplan as claimed in any one of claims 1 to 12, characterized in that: The narrow floorplan is formed by cascading IP_1, IP_2, ..., IP_i, where 1≤i≤M and M is a positive integer.

14. The communication device according to claim 13, wherein: The IP_1, IP_2, ..., IP_i are connected in series in a daisy chain or in a ring connection.

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