Mathematical operation accelerator integrated circuit based on bus interface

Abstract

The invention discloses a mathematical operation accelerator integrated circuit based on a bus interface, which belongs to the technical field of IP design in a semiconductor integrated circuit, and comprises an AXI bus integrated in an SoC (System on Chip); the DMA module is in communication connection with the AXI bus and is used for reading operands and operation instructions from the SoC on-chip system through the AXI bus and storing the operands and the operation instructions into an internal operation RAM (Random Access Memory); the CMD-parser module is in communication connection with the DMA module and is used for acquiring an operand and an operation instruction and analyzing the operand and the operation instruction to generate an operand WORD and an operation instruction WORD; the MATRIX module is in communication connection with the CMD instruction code module and is used for acquiring an operand WORD and an operation instruction WORD and performing operation according to a corresponding operation function; the SRAM memory is in communication connection with the AXI bus and the CMD-parser module and is used for storing an operand WORD and an operation result; when in use, the circuit can be hung in the SoC circuit design based on the AXI bus, an independent mathematical operation circuit does not need to be used externally, the system size is reduced, and the operation efficiency is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of IP design in semiconductor integrated circuits, and in particular to a mathematical operation accelerator integrated circuit based on a bus interface. Background Art

[0002] Mathematical operation accelerator is a hardware component technology used to improve the speed and efficiency of mathematical operations. It focuses on accelerating complex or data-intensive mathematical operations. It is currently mainly implemented in the form of CPU, FPGA, GPU, hardware acceleration card, etc. With the development of modern science and technology, the rapid increase in the amount of information and the rapid growth in the demand for scientific computing have made high-performance computing essential. Due to the increasing complexity of computing tasks, traditional central processing units (CPUs) can no longer meet the demand for high-performance computing. FPGAs, GPUs, and hardware acceleration cards need to be implemented through additional hardware, which increases the hardware burden. Therefore, it is necessary to develop dedicated mathematical operation accelerators. Through their parallel processing, specialized, and efficient computing units, the system can perform computing tasks faster. Summary of the invention

[0003] The purpose of the present invention is to overcome the deficiencies in the prior art and provide a mathematical operation accelerator integrated circuit based on a bus interface, which can form a standard IP and can be easily integrated into a SoC system-on-chip design based on an AXI bus, thereby improving computing efficiency and broadening application scenarios.

[0004] To achieve the above object, the present invention is implemented by adopting the following technical solutions: The present invention provides a mathematical operation accelerator integrated circuit based on a bus interface, comprising: AXI bus, integrated into the SoC system on chip; A DMA module is connected to the AXI bus for communication, and is used to read operands and operation instructions from the SoC system on chip through the AXI bus, and store them in the internal operation RAM; A CMD-parser module, which is in communication with the DMA module and is used to obtain the operand and the operation instruction and parse and generate the operand WORD and the operation instruction WORD; A MATRIX module is connected to the CMD instruction code module for obtaining the operand WORD and the operation instruction WORD, and performing operations according to corresponding operation functions; The SRAM memory is communicatively connected with the AXI bus and the CMD-parser module, and is used for storing operand WORD and operation results.

[0005] Optionally, the AXI bus adopts a standard AXI4.0 interface.

[0006] Optionally, the operand is a matrix, a vector or a scalar.

[0007] Optionally, the SRAM memory includes a plurality of sub-SRAM memories for storing operand WORDs and a sub-SRAM memory for storing operation results.

[0008] Optionally, the SRAM memory further includes a plurality of sub-SRAM memories for storing multiplication-addition or multiplication-subtraction operation results.

[0009] Optionally, the operation functions of the MATRIX module include matrix addition, matrix subtraction, matrix multiplication, matrix transposition, matrix conjugate transposition, matrix inversion, and matrix eigenvalues ​​and eigenvectors.

[0010] Compared with the prior art, the present invention has the following beneficial effects: The present invention provides a mathematical operation accelerator integrated circuit based on a bus interface, which can form a standard IP. The IP can be directly connected to an AXI bus in a SoC system on chip. When in use, it can be hung in a SoC circuit design based on the AXI bus, and no independent mathematical operation circuit is needed externally, thereby reducing the system volume and improving the operation efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 It is a schematic diagram of the structure of a mathematical operation accelerator integrated circuit based on a bus interface provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0012] The present invention will be further described below in conjunction with the accompanying drawings. The following embodiments are only used to more clearly illustrate the technical solution of the present invention, and cannot be used to limit the protection scope of the present invention.

[0013] Embodiment 1:

[0014] like Figure 1As shown, an embodiment of the present invention provides a mathematical operation accelerator integrated circuit based on a bus interface, including an AXI bus, a DMA module, a CMD-parser module, a MATRIX module and an SRAM memory; the AXI bus is integrated in the SoC system on chip; the DMA module is communicatively connected to the AXI bus, and is used to read operands and operation instructions from the SoC system on chip through the AXI bus, and store them in the internal operation RAM; the CMD-parser module is communicatively connected to the DMA module, and is used to obtain operands and operation instructions and parse and generate operand WORDs and operation instruction WORDs; the MATRIX module is communicatively connected to the CMD instruction code module, and is used to obtain operand WORDs and operation instruction WORDs, and perform operations according to corresponding operation functions; the SRAM memory is communicatively connected to the AXI bus and the CMD-parser module, and is used to store operand WORDs and operation results.

[0015] AXI (Advanced eXtensible Interface) is a bus protocol. It is the most important part of the AMBA (Advanced Microcontroller Bus Architecture) 3.0 protocol proposed by ARM. It is an on-chip bus for high performance, high bandwidth and low latency. Its address / control and data phases are separated, supporting unaligned data transmission. At the same time, in burst transmission, only the first address is required. At the same time, the separate read and write data channels support significant transmission access and out-of-order access, and it is easier to achieve timing convergence. AXI technology enriches the existing AMBA standard content to meet the needs of ultra-high performance and complex system-on-chip (SoC) design. AXI features: unidirectional channel architecture. Information flow is transmitted only in one direction, simplifying the bridge between clock domains and reducing the number of gates. When the signal passes through a complex system-on-chip, the delay is reduced. Supports multiple data exchanges. By executing burst operations in parallel, the data throughput is greatly improved, and the task can be completed in a shorter time. While meeting high performance requirements, it also reduces power consumption. Independent address and data channels. The address and data channels are separated, and each channel can be optimized individually. The timing channel can be controlled as needed to maximize the clock frequency and minimize the delay.

[0016] In this embodiment, the AXI bus adopts a standard AXI4.0 interface. The AXI bus interface includes a clock clk, an address line paddr[31:0], an enable signal penable, a select signal psel, a data line pwdata[31:0], a write signal pwrite, and a reset signal rstn. This interface is mainly used to connect to the system bus and control the corresponding register configuration. There are mainly 5 channels, as shown in Table 1-5, a write address channel, a write data channel, a write return channel, a read address channel, and a read data channel, plus two global signals clock CLK and reset RESET. The write address, write data, and write return channel constitute a write operation; the read address channel and the read data channel constitute a read operation. The AXI bus can be directly connected to the internal bus of the SoC.

[0017] Table 1: Write address channel signals

[0018] Table 2: Write data channel information:

[0019] Table 3: Write response channel signals

[0020] Table 4: Read address channel signals

[0021] Table 5: Write data channel signals

[0022] In this embodiment, the instruction code of the CMD-parser module includes 2 control WORDs and 3 operand WORDs.

[0023] The two control WORDs are used as CMD, ROW, COL, OP, IFLAG and other command controls respectively.

[0024] The three operand WORDs include OP_A, OP_B, and OP_C.

[0025] OP_A represents operand A, OP_B represents operand B, and OP_C represents operand C. The operands are matrices, vectors, or scalars.

[0026] Each WORD is set to 32 bits, and the distribution of the five WORDs (WORD0, WORD1, WORD2, WORD3, WORD4) is shown in Table 6-10.

[0027] Table 6: WORD0 distribution

[0028] Table 7: WORD1 distribution

[0029] Table 8: WORD2 distribution

[0030] Table 9: WORD3 distribution

[0031] Table 10: WORD4 distribution

[0032] The SRAM memory includes a plurality of sub-SRAM memories for storing operand WORDs, a sub-SRAM memory for storing operation results, and a plurality of sub-SRAM memories for storing multiplication-addition or multiplication-subtraction operation results.

[0033] In this embodiment, the SRAM memory includes four 512×64 sub-SRAM memories, and the four sub-SRAM memories are allocated as follows: SRAM0 is used to store operand OP_A.

[0034] SRAM1 is used to store operand OP_B.

[0035] SRAM2 is used to store operand OP_C.

[0036] SRAM3 is used to cache the running result of the current instruction for the next instruction.

[0037] The OP_C operand is used as the output and result in multiplication and addition or multiplication and subtraction instructions, for example, OP_C = OP_C + OP_A *OP_B, and the result of multiplying A and B is added to C.

[0038] The MATRIX module is used to implement standard math library functions, matrix operations and other functions. Its operation functions include matrix addition, matrix subtraction, matrix multiplication, matrix transposition, matrix conjugate transposition, matrix inversion, and matrix eigenvalues ​​and eigenvectors.

[0039] Controlled by CMD[7:0], the control commands are as follows.

[0040] CMD = 0: M_ADD, indicating matrix addition, OP_C = OP_A + OP_B, at this time ROW_A = ROW_B, COL_A = COL_B. This instruction supports real and complex numbers, integers, single precision and double precision.

[0041] CMD = 1: M_SUB, indicating matrix subtraction, OP_C = OP_A - OP_B, at this time ROW_A = ROW_B, COL_A = COL_B. This instruction supports real and complex numbers, integers, single precision and double precision.

[0042] CMD = 2: M_MUL, means matrix multiplication, OP_C = OP_A * OP_B, at this time COL_A = ROW_B, the dimension of the result is ROW_A*COL_B, this instruction supports real and complex numbers, integers, single precision and double precision.

[0043] CMD = 3: M_TRANSPOSE, indicating matrix transposition, OP_C = transpose(OP_A), operand OP_B is invalid. This instruction supports real and complex numbers, integers, single precision, and double precision.

[0044] CMD = 4: M_TRANSPOSE_CONJU, indicating matrix conjugate transpose, OP_C = conjugate_transpose(OP_A), operand OP_B is invalid. This instruction supports real and complex numbers, integers, single precision, and double precision.

[0045] CMD = 5: M_INV, indicating matrix inversion, OP_C = inv(OP_A), operand OP_B is invalid. If ROW_A=COL_A=1, the inverse operation is performed. This instruction supports real and complex numbers, integers, single precision, and double precision.

[0046] CMD = 6: M_EIG, indicating matrix eigenvalues ​​and eigenvectors, OP_C = eig(OP_A), operand OP_B is invalid, if ROW_A=COL_A=1, OP_A is returned to OP_C, if ROW_A=COL_A>1, the returned OP_C includes ROW_A values, which are eigenvalues; after the eigenvalues, the values ​​including ROW_A are eigenvectors. This instruction supports real and complex numbers, integers, single precision and double precision.

[0047] The remaining mathematical functions can be further expanded through CMD.

[0048] This embodiment provides a mathematical operation accelerator integrated circuit based on a bus interface. In current large-scale SoC designs, the CPU processor can no longer meet the needs of large data volume operations. FPGA, GPU, etc. need to be implemented through additional hardware, which increases cost and volume. Therefore, a mathematical operation accelerator integrated IP technology based on an AXI bus interface is studied, which can be easily integrated into the SoC circuit to meet the application needs of efficient computing.

[0049] It will be appreciated by those skilled in the art that embodiments of the present invention may be provided as methods, systems, or computer program products. Therefore, the present invention may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Furthermore, the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0050] The present invention is described with reference to flowcharts and / or block diagrams of methods, devices (systems), and computer program products according to embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0051] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0052] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0053] The above is only a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the technical principles of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A mathematical operation accelerator integrated circuit based on a bus interface, characterized in that: include: AXI bus, integrated into the SoC system on chip; A DMA module is connected to the AXI bus for communication, and is used to read operands and operation instructions from the SoC system on chip through the AXI bus, and store them in the internal operation RAM; A CMD-parser module, which is in communication with the DMA module and is used to obtain the operand and the operation instruction and parse and generate the operand WORD and the operation instruction WORD; A MATRIX module is connected to the CMD instruction code module for obtaining the operand WORD and the operation instruction WORD, and performing operations according to corresponding operation functions; The SRAM memory is communicatively connected with the AXI bus and the CMD-parser module, and is used for storing operand WORD and operation results.

2. The bus interface-based mathematical operation accelerator integrated circuit according to claim 1, characterized in that: The AXI bus adopts a standard AXI4.0 interface.

3. The bus interface-based mathematical operation accelerator integrated circuit according to claim 1, characterized in that: The operand is a matrix, vector or scalar.

4. The bus interface-based mathematical operation accelerator integrated circuit according to claim 1, characterized in that: The SRAM memory includes a plurality of sub-SRAM memories for storing operand WORDs and a sub-SRAM memory for storing operation results.

5. The bus interface-based mathematical operation accelerator integrated circuit according to claim 4, characterized in that: The SRAM memory also includes a plurality of sub-SRAM memories for storing multiplication-addition or multiplication-subtraction operation results.

6. The bus interface-based mathematical operation accelerator integrated circuit according to claim 1, characterized in that: The calculation functions of the MATRIX module include matrix addition, matrix subtraction, matrix multiplication, matrix transposition, matrix conjugate transposition, matrix inversion, and matrix eigenvalues ​​and eigenvectors.

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