On-chip termination circuit module and data retention method thereof

Abstract

The on-chip termination circuit module according to the present invention realizes a desired termination resistance (RTT) by performing on-chip termination (ODT) of a DRAM, the on-chip termination circuit module comprising: a synchronization unit that operates when a clock enable signal is high and a delay locked loop is open, such that the ODT operates in a synchronization mode; the asynchronous unit acts when the clock enable signal is low and the delay phase-locked loop is closed, so that the ODT works in an asynchronous mode; and a data holding unit that, when the ODT shifts from the asynchronous mode to the synchronous mode, holds data at the RTT at a fixed conversion interval value during a period from when asynchronous data of a last beat in the asynchronous mode is shifted to the RTT to when synchronous data of a first beat in the synchronous mode is shifted to the RTT.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to an on-chip termination circuit module and a data holding method for the on-chip termination circuit module. Background Art

[0002] In DRAM (Dynamic Random Access Memory) technology, On-Die Termination (ODT) technology is a key technology introduced to improve signal integrity in high-speed memory systems. As memory data rates and frequencies continue to increase, signal integrity issues are becoming increasingly prominent, so the ODT function is particularly important. By using ODT technology, signal integrity can be improved, reflections and noise can be reduced, thereby optimizing high-speed data transmission.

[0003] The ODT function in DRAM usually has two working modes, namely synchronous mode and asynchronous mode. The synchronous mode and asynchronous mode of the ODT function are specified in detail in the DDR3 SDRAM standard (JESD79-3F). The synchronous mode is usually used in high-speed data transmission scenarios with strict timing requirements, which can ensure that ODT is accurately enabled or disabled at a predetermined clock cycle, thereby avoiding possible signal distortion and bit errors. The asynchronous mode is suitable for power saving mode (Power Down mode). However, when DRAM exits from this situation, ODT will have a transition process from asynchronous mode to synchronous mode. During this transition process, as described in detail later, an unknown and unstable state will occur, resulting in glitches. Such glitches in the circuit will reduce the stability and reliability of the DRAM system.

[0004] The present invention is completed to solve the above-mentioned problem, and its purpose is to provide an on-chip termination circuit module and a data retention method of the on-chip termination circuit module, so as to avoid glitches in the conversion process of ODT from asynchronous mode to synchronous mode, thereby improving the stability and reliability of the DRAM system. Summary of the invention The present invention relates to an on-chip termination circuit module, which realizes the required terminal resistance RTT by executing the on-chip termination of DRAM, namely ODT, and is characterized in that it comprises: a synchronization unit, which operates when a clock enable signal is high and a delay locked loop is turned on, so that the ODT operates in a synchronous mode; an asynchronous unit, which operates when the clock enable signal is low and the delay locked loop is turned off, so that the ODT operates in an asynchronous mode; and a data holding unit, which, when the ODT is transferred from the asynchronous mode to the synchronous mode, keeps the data at the RTT as a fixed conversion interval value during the period from when the asynchronous data of the last beat in the asynchronous mode is shifted to the RTT to when the synchronous data of the first beat in the synchronous mode is shifted to the RTT. Preferably, the conversion interval value is the asynchronous data of the last beat sampled in the asynchronous mode. Preferably, at the switching moment when the ODT is transferred from the asynchronous mode to the synchronous mode, both the asynchronous data of the last beat in the asynchronous mode and the synchronous data of the first beat in the synchronous mode are sampled. Preferably, the data holding unit is implemented by a logic circuit, and the logic circuit is used to generate an enable signal of the synchronization unit. Preferably, the synchronization unit includes an AL shift trigger and a WL shift trigger, and the data holding unit includes a logic circuit for generating an enable signal of the AL shift trigger and a logic circuit for generating an enable signal of the WL shift trigger. Preferably, the data holding unit is implemented by a reset signal generating circuit, and the reset signal generating circuit is used to hold the pull-up circuit in the asynchronous unit, so that the data at the RTT is held as the conversion interval value. Preferably, the synchronization unit includes an AL shift trigger and a WL shift trigger, and the reset signal generating circuit generates a reset signal based on a shutdown signal of the asynchronous circuit and an output signal of the WL shift trigger, and inputs the reset signal to a trigger corresponding to a pull-up circuit in the asynchronous circuit. The present invention also relates to a data retention method, which is used to implement an on-chip termination circuit module of a required terminal resistance RTT by executing an on-chip termination, i.e., ODT, of a DRAM, and is characterized in that the ODT has a synchronous mode and an asynchronous mode, and performs data retention processing so that when the ODT is transferred from the asynchronous mode to the synchronous mode, the data at the RTT is maintained as a fixed conversion interval value during the period from when the asynchronous data of the last beat in the asynchronous mode is shifted to the RTT to when the synchronous data of the first beat in the synchronous mode is shifted to the RTT. Preferably, the conversion interval value is the asynchronous data of the last beat sampled in the asynchronous mode. Preferably, at the switching moment when the ODT is transferred from the asynchronous mode to the synchronous mode, both the asynchronous data of the last beat in the asynchronous mode and the synchronous data of the first beat in the synchronous mode are sampled. Preferably, the data retention processing includes: generating an enable signal based on the ODT data sampled at the conversion moment and the output signal of the delay locked loop of the on-chip termination circuit module, and inputting it into the AL shift trigger and WL shift trigger of the on-chip termination circuit module to keep the data at the RTT as a fixed conversion interval value. Preferably, the data retention processing includes: generating a reset signal based on a shutdown signal of the asynchronous circuit possessed by the on-chip termination circuit module and an output signal of a WL shift trigger possessed by the on-chip termination circuit module, and inputting the reset signal into a trigger corresponding to a pull-up circuit in the asynchronous circuit, maintaining the pull-up circuit in the asynchronous circuit, so as to keep the data at the RTT as a fixed conversion interval value. The present invention also relates to a memory, characterized by comprising any one of the above-mentioned on-chip termination circuit modules. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Figure 1 FIG. 2 is a timing diagram illustrating a synchronization mode of the ODT function.

[0006] Figure 2 is a timing diagram illustrating an asynchronous mode of the ODT function.

[0007] Figure 3 1 is a timing diagram showing the conversion of the ODT function involved in the present invention from the asynchronous mode to the synchronous mode.

[0008] Figure 4a is a schematic circuit diagram showing synchronous and asynchronous units of an on-chip termination circuit module according to Embodiment 1 of the present invention. Figure 4b is a schematic circuit diagram showing an enable signal generating unit of the on-chip termination circuit module according to the first embodiment of the present invention, Figure 4c This is a schematic circuit diagram showing a data holding unit included in the on-die termination circuit module according to the first embodiment of the present invention.

[0009] Figure 5 This is a flowchart showing the data holding process according to the first embodiment of the present invention.

[0010] Figure 6 This is a timing chart showing the data holding process according to the first embodiment of the present invention.

[0011] Figure 7 This is a schematic diagram showing an on-chip termination circuit module according to the second embodiment of the present invention.

[0012] Figure 8 This is a timing chart showing the data holding process according to the second embodiment of the present invention. DETAILED DESCRIPTION

[0013] The following will describe the specific embodiments of the present invention. By reading the detailed description of the specific embodiments below, the various advantages and benefits of the present invention will become clear to those of ordinary skill in the art. However, it should be understood that the present invention can be implemented in various forms and should not be limited by the various embodiments described here. The following embodiments are provided to enable a more thorough understanding of the present invention. It should be noted that in the specific description of these embodiments, in order to be concise and concise, this specification cannot provide a detailed description of all the features of the actual embodiments. It should be understood that in the actual implementation of any embodiment, just as in the process of any engineering project or design project, in order to achieve the specific goals of the developer, in order to meet system-related or business-related restrictions, various specific decisions are often made, and this will also change from one embodiment to another. In addition, it can also be understood that although the efforts made in this development process may be complex and lengthy, for those of ordinary skill in the art related to the content disclosed in the present invention, some changes such as design, manufacturing or production based on the technical content disclosed in the present disclosure are only conventional technical means, and should not be understood as insufficient content of the present disclosure.

[0014] Unless otherwise defined, the technical or scientific terms used in the claims and the specification shall have the usual meaning understood by persons with ordinary skills in the technical field to which the invention belongs. The words "first", "second" and similar words used in the patent application specification and the claims of the present invention do not indicate any order, quantity or importance, but are only used to distinguish different components. "One" or "one" and other similar words do not indicate a quantitative limitation, but indicate the existence of at least one. "Include" or "comprises" and other similar words mean that the elements or objects appearing before "include" or "comprises" include the elements or objects listed after "include" or "comprises" and their equivalent elements, and do not exclude other elements or objects. "Connected" or "connected" and other similar words are not limited to physical or mechanical connections, nor are they limited to direct or indirect connections.

[0015] In addition, in order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the specific embodiments of the present invention will be described in detail in conjunction with the accompanying drawings, so that the features, objects and advantages of the present invention will be more clearly understood by those skilled in the art. The flowcharts and block diagrams in the accompanying drawings show the system architecture, functions and operations that may be implemented by the systems and methods according to the embodiments of the present invention. The accompanying drawings are only used for the purpose of illustrating preferred embodiments and are not considered to be limitations of the present invention. Moreover, the same reference symbols are used to represent the same components throughout the accompanying drawings.

[0016] First, based on Figure 1 and Figure 2 The two working modes of the ODT function of DRAM are briefly described. As mentioned above, the ODT function of DRAM has two working modes: synchronous mode and asynchronous mode. Figure 1 is a timing diagram showing the synchronization mode of the ODT function in the DRAM. Figure 2 is a timing diagram showing the asynchronous mode of the ODT function in DRAM.

[0017] Figure 1 In the figure, based on the JEDEC protocol, an example of the timing of synchronous ODT is shown with AL (Additive Latency) = 3 (clock cycles); CWL (CAS Write Latency) = 5 (clock cycles); ODTLon (ODT Turn-On Latency) = AL + CWL-2 = 6.0 (clock cycles); ODTLoff (ODT Turn-Off Latency) = AL + CWL-2 = 6 (clock cycles) as an example.

[0018] also, Figure 1 The meanings of the signals and parameters shown in are as follows (in addition, when there are signals, numbers or parameters that are not explicitly stated, they can be interpreted according to the conventional meanings in the art): CK and CK# (inverted): clock signal; CKE: clock enable signal; ODT: ODT function enable signal; DRAM_RTT: internal terminal resistance (RTT) parameter; ODTH4,min: The ODT signal remains active for at least 4 clock cycles; tAONmin: Minimum RTT turn-on time; tAONmax: Maximum RTT turn on time; RTT_NOM: Nominal ODT terminal resistance, that is, the standard or nominal terminal resistance value set in the configuration, Used to determine the resistor value used in ODT; tAOFmin: Minimum RTT turn-off time; tAOFmax: Maximum RTT turn off time.

[0019] like Figure 1 As shown, when the input pin ODT is sampled high by the rising edge of CK, RTT (DRAM_RTT) will be enabled after ODTLon; when the input pin ODT is sampled low by the rising edge of CLK, RTT will be disabled after ODTLOff. The JEDEC protocol defines the calculation formula of ODTLon and ODTLOff as CWL+AL-2, which is a timing in units of one clock cycle, so it is called synchronous mode. When the clock enable signal CKE is high (High) and the DLL (Delay-Locked Loop) is turned on and locked, the ODT of DRAM works in synchronous mode. At this time, the circuit of asynchronous mode is turned off and bypassed.

[0020] Next, based on Figure 2 The asynchronous mode of the ODT function is briefly described.

[0021] Figure 2 The meanings of the signals and parameters shown in are as follows: tIH: Hold time of external input pin for clock input; tIS: setup time of external input pin for clock input; tAONPDmin: Minimum Asynchronous RTT turn-on delay; tAONPDmax: Maximum Asynchronous RTT turn-on delay; tAOFPDmin: Minimum Asynchronous RTT tun-off delay; tAOFPDmax: Maximum Asynchronous RTT tun-off delay.

[0022] In addition, for Figure 1The same signals and parameters in the above description will not be described again. In addition, similarly, when there are signals, numbers or parameters that are not clearly described, they can be interpreted according to the conventional meaning in the art with reference to the JEDEC protocol.

[0023] like Figure 2 As shown, when the input pin ODT is sampled high by the rising edge of CLK, RTT will be enabled after tAONPD; when the input pin ODT is sampled low by the rising edge of CLK, RTT will be disabled after tAOFPD. The JEDEC protocol defines the interval of tAONPD and tAOFPD as greater than 2ns and less than 8.5ns, which is not a timing in units of one clock cycle. When the DRAM enters the Power Down mode (power saving mode), that is, the clock enable signal CKE is low (Low) and the DLL is turned off, ODT works in asynchronous mode. At this time, the synchronous mode circuit is reset and bypassed.

[0024] When exiting asynchronous mode and entering synchronous mode, a transition interval will appear. For example, based on the JEDEC standard, if tCK = 2.5ns, CWL = 5tCK, AL = 5tCK configuration, ODTLon = CWL + AL-2 = 20ns, and tAONPD and tAOFPD are approximately equal to 3.5ns. Therefore, if no special processing is done, RTT will eventually appear between the last beat of asynchronous data and the first beat of synchronous data shifted to RTT (3.5ns-20ns). The appearance of this glitch in the circuit will reduce the stability and reliability of the DRAM system.

[0025] like Figure 3 As shown, the present invention solves the problem of unknown and unstable results in this conversion interval, allowing the RTT to be stabilized at the last beat asynchronous result during this period without any glitches. Figure 3 1 is a timing diagram showing the conversion of the ODT function involved in the present invention from the asynchronous mode to the synchronous mode.

[0026] First, the transition time (TransitionClk) of the ODT function from the asynchronous mode to the synchronous mode in the present invention is defined. Assuming that the first clock rising edge after the DRAM exits the Power Down mode, that is, CKE is pulled high, is defined as T0, then the transition time is Ttr=T0+tCK*tr (tCK represents a clock cycle, tr is an integer value), then the timing of ODT is expressed as: 1) The delay of ODT before Ttr (including Ttr) adopts the above-mentioned asynchronous timing tAONPD and tAOFPD. 2) The delay of ODT after Ttr adopts the above-mentioned synchronous timing tODTLon and tODTLoff.

[0027] The Ttr time is defined according to the JEDEC standard tCKE (min). Specifically, according to the JEDEC standard, the transition time (Ttr) is selected based on different speed grades.

[0028] As shown in Table 1, different speed grades correspond to different Ttr. For example, when the speed grade is SG1333, T3 becomes the conversion time from asynchronous mode to synchronous mode, T3 = T0 + 3 * tCK. Therefore, ODT uses asynchronous timing before (including T3) and synchronous timing after T3.

[0029] In addition, in the present invention, the conversion time Ttr is both the last beat of the asynchronous clock and the first beat of the synchronous clock. At this moment, ODT will be sampled by these two clocks simultaneously.

[0030] Figure 3 In the example, the case where WL (Write Latency) = 7 and the transition time Ttr (Transition clk) is T3 is used for explanation. Figure 3 , which shows the asynchronous data AsyncD-1, AsyncD0, AsyncD1, AsyncD2, and AsyncD3 shifted to the terminal resistor RTT in the asynchronous mode, respectively representing the data sampled at time T-1, T0, T1, T2, and T3. Figure 3 The figure also shows, as an example, synchronous data SyncD3 and SyncD4 shifted to the terminal resistor RTT in the synchronous mode, which respectively represent the data sampled at time T3 and T4.

[0031] like Figure 3 As shown, at time T0, DRAM exits Power Down mode, and then at the conversion time T3, ODT switches from asynchronous mode to synchronous mode. As mentioned above, the conversion time T3 is both the last beat of the asynchronous clock and the first beat of the synchronous clock. At this moment, ODT will be sampled by these two clocks at the same time. Therefore, at the conversion time T3, both the last beat of asynchronous data AsyncD3 and the first beat of synchronous data SyncD3 are sampled. Moreover, during the period from the time when the last beat of the sampled asynchronous data AsyncD3 in the asynchronous mode is shifted to RTT to the time when the first beat of the sampled synchronous data SyncD3 in the synchronous mode is shifted to RTT, the data at RTT is maintained as a fixed conversion interval value. Figure 3It is recorded as TransitionD3.

[0032] Therefore, by sampling both the asynchronous data of the last beat in the asynchronous mode and the synchronous data of the first beat in the synchronous mode at the conversion moment, and during the period from the shift of the sampled asynchronous data AsyncD3 of the last beat in the asynchronous mode to RTT to the shift of the sampled synchronous data SyncD3 of the first beat in the synchronous mode to RTT, the data at RTT is kept as a fixed conversion interval value, thereby avoiding the problem of glitches in the conversion interval when the asynchronous mode is converted to the synchronous mode in the prior art, thereby improving the stability and reliability of the DRAM system.

[0033] Hereinafter, each embodiment of the present invention will be described in detail.

[0034] Implementation Method 1

[0035] Figures 4a to 4c 1 is a schematic diagram showing an on-die termination circuit module 100 according to the first embodiment of the present invention. Figure 4a 1 is a schematic circuit diagram showing a synchronous unit 101 and an asynchronous unit 102 included in an on-chip termination circuit module 100 according to Embodiment 1 of the present invention. Figure 4b 1 is a schematic circuit diagram showing an enable signal generating unit 103 of the on-chip termination circuit module 100 according to the first embodiment of the present invention. Figure 4c 1 is a schematic circuit diagram showing the data holding unit 104 included in the on-die termination circuit module according to the first embodiment of the present invention.

[0036] The on-die termination circuit module 100 according to the first embodiment includes a synchronous unit 101 , an asynchronous unit 102 , an enable signal generating unit 103 , a data holding unit 104 , and an RTT flip-flop 105 .

[0037] like Figure 4aAs shown, the on-chip termination circuit module 100 involved in Embodiment 1 includes a synchronous unit 101 and an asynchronous unit 102 (hereinafter, sometimes referred to as the synchronous circuit 101 and the asynchronous circuit 102). The synchronous circuit 101 includes a plurality of AL shift flip-flops 1011, a DLL (delay locked loop) 1012, and a plurality of WL shift flip-flops 1013. The asynchronous circuit 102 includes a flip-flop 1021 corresponding to an asynchronous pull-down circuit and a flip-flop 1022 corresponding to an asynchronous pull-up circuit. As described above, the synchronous unit 101 operates when the clock enable signal CKE is high (High) and the DLL1012 is turned on, so that the ODT operates in the synchronous mode. The asynchronous unit 102 operates when the clock enable signal CKE is low (Low) and the DLL1012 is turned off, so that the ODT operates in the asynchronous mode.

[0038] First, assuming that the current clock enable signal CKE is low (Low) and DLL1012 is turned off (Power Down mode), the ODT works in asynchronous mode, and the synchronization circuit 101 is reset and bypassed. At this time, each shift flip-flop (AL (Additive Latency) shift flip-flop 1011 and WL (Write latency) shift flip-flop 1012) in the synchronization circuit 101 is reset to 0.

[0039] Next, when the clock enable signal CKE becomes high (High) to exit the Power Down mode, and the DLL1012 is turned on, the working mode of the ODT will be converted from the asynchronous mode to the synchronous mode.

[0040] If Speed ​​Grade is SG1333, T3 is defined as the conversion time Ttr. In implementation mode 1, the conversion time T3 is set to the asynchronous clock of the last beat and the synchronous clock of the first beat, which means that at the conversion time T3, both the asynchronous data of the last beat in the asynchronous mode and the synchronous data of the first beat in the synchronous mode are sampled. Figure 4b The enable signal generating unit 103 shown shifts the time when the clock enable signal CKE is pulled high back by 3 beats (3*tCK) to serve as the shutdown signal SlowPDb of the asynchronous circuit and the enable signal SlowPD of the synchronous circuit.

[0041] At the switching time T3, if Figure 4aAs shown, the enable signal SlowPD of the synchronous circuit 101 generated by the enable signal generating unit 103 is input to the AL shift flip-flop 1011 and the WL shift flip-flop 1013 to enable the synchronous circuit 101. At the same time, the shutdown signal SlowPDb of the asynchronous circuit 102, which is also generated by the enable signal generating unit 103, is input to the flip-flops 1021 and 1022 in the asynchronous circuit 102 to shut down the asynchronous circuit 102. Thus, the ODT enters the synchronous mode from the asynchronous mode.

[0042] When the synchronization circuit 101 is re-enabled, even if the input of the ODT pin is always 1 during this period, the state that was previously reset to 0 in the synchronization circuit 101 will be shifted to RTT via the trigger 105 along with the clock. Therefore, the "glitch" existing in the prior art is generated. Therefore, in order to solve this problem, the on-chip termination circuit module 100 involved in this embodiment 1 also includes a data holding unit 104. When ODT is converted from asynchronous mode to synchronous mode, from the time when the asynchronous data of the last beat in the asynchronous mode is shifted to RTT to the time when the synchronous data of the first beat in the synchronous mode is shifted to RTT, the data at RTT is kept as a fixed conversion interval value. At the conversion time T3, both the asynchronous data of the last beat in the asynchronous mode and the synchronous data of the first beat in the synchronous mode are sampled.

[0043] Figure 4c FIG. 2 shows a schematic circuit diagram of the data holding unit 104 according to the first embodiment. Figure 4c As shown, in the first embodiment, the data holding unit 104 is composed of a logic circuit, and the logic circuit is used to generate the enable signals OdtForceHb and OdtForceALHb of the synchronization circuit 101 for holding the data at the RTT at a fixed conversion interval value.

[0044] The data holding unit 104 includes a logic circuit for generating an enable signal OdtForceALHb of the AL shift flip-flop and a logic circuit for generating an enable signal OdtForceHb of the WL shift flip-flop.

[0045] like Figure 4c As shown, the data holding unit 104 generates enable signals OdtForceHb and OdtForceALHb for maintaining the data at RTT as fixed conversion interval values ​​based on the ODT data sampled at the conversion time Ttr and the output signal of DLL1012 (the input signal of the WL shift trigger 1013) odtdllout, and uses them as reset signals of each shift trigger in the synchronization circuit 101, and inputs them to the reset terminals (Sf terminals) of the AL shift trigger 1011 and the WL shift trigger 1013, respectively.

[0046] Specifically, if Figure 4c As shown, the logic circuit for generating the enable signal OdtForceALHb of the AL shift flip-flop is composed of a NOT gate, a NAND gate, and a buffer. The input signal of the set end of the NAND gate is the ODT data sampled at the time Ttr. When ODT is 1 (High) at the conversion time Ttr, the pulse signal OdtForceALHb is generated as the input signal of the reset end of the AL shift flip-flop (0 is valid).

[0047] In addition, the logic circuit for generating the enable signal OdtForceHb of the WL shift trigger is a commonly used standard RS trigger, which is composed of two NAND gates and a buffer, and the output of each NAND gate is respectively connected to the exclusive OR of another NAND gate. The input signal of the set end of the RS trigger is the ODT data sampled at the time Ttr. When ODT is 1 (High) at the conversion time Ttr, a pulse signal OdtForceHb is generated as the input signal of the reset end of the WL shift trigger (0 is valid). The input signal of the reset end of the RS trigger is the output signal (odtdllout) of DLL1012. When the output signal odtdllout of DLL1012 is 1, OdtForceHb is reset to 1.

[0048] Therefore, the OdtForceHb signal and the OdtForceALHb signal are used to correct the reset state of each shift trigger of the synchronization circuit 101, so that the data at RTT remains the asynchronous data of the last beat in the asynchronous mode obtained by sampling at the conversion time Ttr, and it is used as a fixed conversion interval value (in Figure 6 In the timing diagram shown, it is marked as TransitionD3).

[0049] Specifically, there are two situations: (1) If the asynchronous data of the last beat sampled at the conversion time Ttr is 0, then it will not be The ODT data generates a conflict, so there is no need to process the data previously reset to 0 in the synchronization circuit 101 . (2) If the asynchronous data of the last beat sampled at the conversion time Ttr is 1, OdtForceALHb will be set to 0 by the currently sampled ODT=1, so that the Sf terminal of the AL shift flip-flop 1011 is set to 0. The output of the AL shift flip-flop 1011 is set to 1 by Sf=0, and this 1 is transmitted to DLL1012 with the next clock. For the next WL shift flip-flop 1013, OdtForceHb is set to 0 by the currently sampled ODT=1, so that the output signal of the WL shift flip-flop 1013 ODT_NOM is set to 1 by Sf = 0. Then OdtForceHb will remain at 0 until The output signal of DLL1012 (the input signal of WL shift flip-flop 1013) odtdllout also becomes 1 This is because when the input of WL shift trigger 1013 becomes 1, it means that the asynchronous data 1 sampled at the conversion time Ttr has been delayed by AL shift trigger 1011 and DLL1012 and has arrived at WL shift trigger 1013, which also means that ODT has entered the synchronous mode at this time, so the first beat of the synchronous data will be transmitted to ODT_NOM with the delay of CWL-2 with the next clock and finally reflected to RTT through trigger 105. At this time, the OdtForceHb signal is released, thereby completing the connection from asynchronous mode to synchronous mode.

[0050] Next, based on Figure 5 The data holding process performed by the data holding unit 104 in the first embodiment will be described. Figure 5 This is a flowchart showing the data holding process according to the first embodiment of the present invention.

[0051] like Figure 5 As shown, first in step S101, the input of the ODT pin is sampled at the conversion time Ttr, which is recorded as "sampling ODT@Ttr" in the figure, and then proceeds to step S102.

[0052] In step S102, it is determined whether the sampled ODT data is equal to 1 (represented as ODT==1 in the figure). If not equal to 1, proceed to step S200 and continue to wait for the next clock to sample. If equal to 1, proceed to step S103, set the output signal of the AL shift flip-flop 1011 to high (set to 1) and release it, and then proceed to step S104.

[0053] In step S104, the output signal of the WL shift flip-flop 1013 is set high (set to 1), and then proceeds to step S105.

[0054] In step S105, it is determined whether the output signal of DLL1012, i.e., the input signal odtdllout of WL shift flip-flop 1013, is equal to 1 (represented as odtdllout==1 in the figure). If it is not equal to 1, it returns to step S104 and keeps the state of setting WL shift flip-flop 1013 to high. If it is equal to 1, it proceeds to step S106 and releases the signal that sets WL shift flip-flop 1013 to high, i.e., releases the OdtForceHb signal, thereby completing the data retention process and entering S200 to wait for the next clock.

[0055] Figure 6 This is a timing chart showing the data holding process according to the first embodiment of the present invention. Figure 6 It is a timing diagram taking tODTLON=5tCK as an example, and shows the timing relationship between the signals CK, ODT, CKE, AsyncODT CLK (synchronous ODT clock), SyncODT CLK (asynchronous ODT clock), ODTForceHb, odtdllout, and RTT respectively.

[0056] like Figure 6 As shown, before time T-1, the clock enable signal, i.e., the CKE signal, is low, and the ODT operates in the PowerDown mode, i.e., the asynchronous mode. After that, the CKE signal becomes high, and at time T1, the ODT enable signal becomes high. Then, at the transition time, i.e., T3, the transition from the asynchronous mode to the synchronous mode is performed.

[0057] When ODT works in asynchronous mode, the output signal odtdllout of DLL1012 will be reset to 0, and the reset signal will be released when enabled after T3. At this time, odtdllout reflects the value of the external ODT after a certain delay. When the ODT sampled at T3 is 1, the odtdllout signal becomes 1 after passing through each shift trigger and DLL. At this time, the output signal ODTForcceHb of the data holding unit 104 is reset to 1, thereby releasing the set end of the WL shift trigger, and thus the conversion from asynchronous mode to synchronous mode is completed.

[0058] According to the on-chip termination circuit module involved in the first embodiment of the present invention, since the data holding unit 104 is provided to generate the enable signals OdtForceHb and OdtForceALHb, and the OdtForceHb signal and the OdtForceALHb signal are used to correct the state reset to 0 in each shift trigger of the synchronization circuit, when ODT is converted from the asynchronous mode to the synchronous mode, from the time when the last beat of the asynchronous data in the asynchronous mode is shifted to RTT to the time when the first beat of the synchronous data in the synchronous mode is shifted to RTT, the data at RTT can be forced to be maintained as the last beat of the asynchronous data in the asynchronous mode sampled at the conversion time Ttr, and the data is used as a fixed conversion interval value. Thus, the burrs appearing in the conversion interval when the asynchronous mode is converted to the synchronous mode in the prior art are eliminated, thereby improving the stability and reliability of the DRAM system.

[0059] Implementation Method 2

[0060] Figure 72 is a schematic diagram showing an on-chip termination circuit module 200 according to Embodiment 2 of the present invention. Figures 4a to 4c Similar to the on-chip termination circuit module 100 involved in the embodiment 1 shown, the on-chip termination circuit module 200 involved in the embodiment 2 also includes a synchronous unit 201, an asynchronous unit 202 and a data holding unit 203. The synchronous circuit 201 includes a plurality of AL shift flip-flops 2011, a DLL (delay locked loop) 2012, and a plurality of WL shift flip-flops 2013. The asynchronous circuit 202 includes a flip-flop 2021 corresponding to an asynchronous pull-down circuit, and a flip-flop 2022 corresponding to an asynchronous pull-up circuit. In the following, only the differences between the embodiment 2 and the embodiment 1 are described, and the same parts are not repeated. In addition, since it is the same as the embodiment 1, in the embodiments 2 and Figure 7 The description of the enable signal generating unit that generates the shutdown signal SlowPDb of the asynchronous circuit and the enable signal SlowPD of the synchronous circuit is omitted.

[0061] In the on-chip termination circuit module 200 involved in the second embodiment, the data holding unit 203 is implemented by a reset signal generating circuit. By using the reset signal generating circuit, when the ODT is converted from the asynchronous mode to the synchronous mode, from the time when the last beat of the asynchronous data in the asynchronous mode sampled at the conversion time Ttr is shifted to RTT to the time when the first beat of the synchronous data in the synchronous mode sampled at the conversion time Ttr is shifted to RTT, the data at RTT can be kept as the last beat of the asynchronous data in the asynchronous circuit as a fixed conversion interval value ( Figure 8 It is recorded as TransitionD3).

[0062] Specifically, as in Implementation 1, there are two cases: (1) If the asynchronous data of the last beat sampled at the conversion time Ttr is 0, it will not conflict with the ODT data, so there is no need to process the data previously reset to 0 in the synchronization circuit 201. (2) If the asynchronous data of the last beat sampled at the conversion time Ttr is 1, it will conflict with the data reset to 0 in the previous synchronous circuit 201 as described above. Therefore, in this embodiment 2, as a function of the data holding unit 203, the reset signal generation circuit is used to modify the reset signal of the trigger 2022 corresponding to the pull-up circuit in the asynchronous circuit 202, until the ODT data (the first beat of the synchronous data) in the synchronous mode sampled at the conversion time Ttr is transmitted to ODT_NOM through the AL shift trigger 2011, DLL2012 and WL shift trigger 2013 and finally reflected to RTT via the trigger 204. At this time, it means that the asynchronous circuit 202 can be closed and handed over to the synchronous circuit 201, thereby completing the connection work from the asynchronous mode to the synchronous mode.

[0063] The reset signal generating circuit involved in the present embodiment 2 is composed of an inverter and a NAND gate, and the shutdown signal SlowPDb of the asynchronous circuit is inverted and used as the input of the NAND gate together with the ODT_NOM signal, and the output Rfin of the NAND gate is input to the Rf end of the trigger 2022 corresponding to the pull-up circuit in the asynchronous circuit 202. Therefore, the input signal of the Rf end is the result of CKE being high and ODT_NOM being high, so that even if the Power Down mode has been exited, the result of the trigger 2022 will still be locked, so that the pull-up circuit of the asynchronous circuit 202 can be maintained, and then the asynchronous data of the last beat in the asynchronous circuit 202 can be maintained as a fixed conversion interval value.

[0064] Figure 8 2 is a timing chart showing the data retention process according to the second embodiment of the present invention. Figure 8 The timing diagram also takes tODTLON=5tCK as an example, and shows the timing relationship between the signals CK, ODT, CKE, AsyncODT CLK (synchronous ODT clock), SyncODT CLK (asynchronous ODT clock), Rfin, ODT_NOM, and RTT respectively.

[0065] like Figure 8 As shown, before time T-1, the clock enable signal, i.e., the CKE signal, is low, and the ODT operates in the PowerDown mode, i.e., the asynchronous mode. After that, the CKE signal becomes high, and at time T1, the ODT enable signal becomes high. Then, at the transition time, i.e., T3, the transition from the asynchronous mode to the synchronous mode is performed.

[0066] like Figure 8As shown, when ODT works in asynchronous mode, ODT_NOM will be reset to 0, and the reset signal will be released when enabled after T3. When the 1 on ODT sampled at T3 is transmitted to ODT_NOM through AL shift trigger 2011, DLL2012, and WL shift trigger 2013, the reset end of the trigger 2022 corresponding to the pull-up circuit in the asynchronous circuit 202 will take effect (0 is valid). Before the reset end changes from 1 to 0, that is, takes effect, the asynchronous data 1 of the last beat will be maintained by the pull-up circuit of the asynchronous circuit 202 as a fixed conversion interval value.

[0067] According to the on-chip termination circuit module 200 involved in the second embodiment of the present invention, since it has a data holding unit 203 (reset signal generating circuit) to generate a reset signal for holding the trigger of the pull-up circuit of the asynchronous circuit 202, it can still hold the pull-up circuit of the asynchronous circuit when the DRAM has exited the Power Down mode, so that when the ODT is converted from the asynchronous mode to the synchronous mode, from the time when the last beat of the asynchronous data in the asynchronous mode sampled at the conversion time Ttr is shifted to RTT to the time when the first beat of the synchronous data in the synchronous mode sampled at the conversion time Ttr is shifted to RTT, the data at RTT can be forced to be held as the last beat of the asynchronous data in the asynchronous mode sampled at the conversion time Ttr, and it is used as a fixed conversion interval value. Thus, the burrs that appear in the conversion interval when the asynchronous mode is converted to the synchronous mode in the prior art are eliminated, thereby improving the stability and reliability of the system.

[0068] In addition, the present invention also relates to a memory including the on-die termination circuit module 100 or 200 described in the above-mentioned embodiment 1 or 2. According to the memory including such an on-die termination circuit module, the stability and reliability of the system can be improved.

[0069] The above describes the various embodiments of the present invention, but the present invention can freely combine the various embodiments within the scope of the invention, or appropriately modify or omit the various embodiments. Although the present invention is described in detail above, the above description is illustrative in all aspects, and the present invention is not limited thereto. Countless modifications not illustrated can be interpreted as being conceivable without departing from the scope of the present invention.

Claims

1. An on-chip termination circuit module, which implements the required terminal resistance RTT by performing on-chip termination (ODT) of DRAM, characterized in that: include: A synchronization unit, which operates when the clock enable signal is high and the delay locked loop is turned on, so that the ODT operates in a synchronization mode; an asynchronous unit, which operates when the clock enable signal is low and the delay locked loop is closed, so that the ODT operates in an asynchronous mode; A data holding unit, which, when the ODT is transferred from the asynchronous mode to the synchronous mode, keeps the data at the RTT as a fixed conversion interval value during the period from when the asynchronous data of the last beat in the asynchronous mode is shifted to the RTT to when the synchronous data of the first beat in the synchronous mode is shifted to the RTT.

2. The on-chip termination circuit module according to claim 1, characterized in that: The conversion interval value is the asynchronous data of the last beat sampled in the asynchronous mode.

3. The on-chip termination circuit module according to claim 1 or 2, characterized in that: At the switching moment when the ODT is transferred from the asynchronous mode to the synchronous mode, both the asynchronous data of the last beat in the asynchronous mode and the synchronous data of the first beat in the synchronous mode are sampled.

4. The on-chip termination circuit module according to claim 1 or 2, characterized in that: The data holding unit is implemented by a logic circuit, and the logic circuit is used to generate an enable signal of the synchronization unit.

5. The on-chip termination circuit module according to claim 4, characterized in that: The synchronization unit includes an AL shift trigger and a WL shift trigger, The data holding unit includes a logic circuit for generating an enable signal of the AL shift flip-flop and a logic circuit for generating an enable signal of the WL shift flip-flop.

6. The on-chip termination circuit module according to claim 1 or 2, characterized in that: The data holding unit is implemented by a reset signal generating circuit, and the reset signal generating circuit is used to hold the pull-up circuit in the asynchronous unit, so that the data at the RTT is held as the conversion interval value.

7. The on-chip termination circuit module according to claim 6, characterized in that: The synchronization unit includes an AL shift trigger and a WL shift trigger, The reset signal generating circuit generates a reset signal based on a shutdown signal of the asynchronous circuit and an output signal of the WL shift flip-flop, and inputs the reset signal to a flip-flop corresponding to a pull-up circuit in the asynchronous circuit.

8. A data retention method for implementing an on-chip termination circuit module of a required terminal resistance RTT by performing on-chip termination (ODT) of a DRAM, characterized in that: The ODT has a synchronous mode and an asynchronous mode. Data retention processing is performed so that when the ODT is transferred from the asynchronous mode to the synchronous mode, the data at the RTT is maintained as a fixed conversion interval value during the period from when the asynchronous data of the last beat in the asynchronous mode is shifted to the RTT to when the synchronous data of the first beat in the synchronous mode is shifted to the RTT.

9. The data holding method according to claim 8, wherein: The conversion interval value is the asynchronous data of the last beat sampled in the asynchronous mode.

10. The data holding method according to claim 8 or 9, characterized in that: At the switching moment when the ODT is transferred from the asynchronous mode to the synchronous mode, both the asynchronous data of the last beat in the asynchronous mode and the synchronous data of the first beat in the synchronous mode are sampled.

11. The data holding method according to claim 8 or 9, characterized in that: The data retention processing includes: generating an enable signal based on the ODT data sampled at the conversion time and the output signal of the delay locked loop of the on-chip termination circuit module, and inputting it into the AL shift trigger and WL shift trigger of the on-chip termination circuit module to keep the data at the RTT as a fixed conversion interval value.

12. The data holding method according to claim 8 or 9, characterized in that: The data retention processing includes: generating a reset signal based on a shutdown signal of the asynchronous circuit possessed by the on-chip termination circuit module and an output signal of a WL shift trigger possessed by the on-chip termination circuit module, and inputting the reset signal into a trigger corresponding to a pull-up circuit in the asynchronous circuit, maintaining the pull-up circuit in the asynchronous circuit to maintain the data at the RTT as a fixed conversion interval value.

13. A memory, characterized in that: A chip termination circuit module comprising the on-chip termination circuit module according to any one of claims 1 to 7.

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