Device assembling method and device, electronic equipment and computer program product

Abstract

The invention provides a device assembling method and device, electronic equipment and a computer program product. The overall power consumption performance difference after chip assembling is reduced. The method comprises the steps that first quantile information corresponding to at least one chip is obtained, the first quantile information is obtained by testing the chip, and the first quantile information is used for representing the power consumption performance of the corresponding chip; second quantile information corresponding to at least one target device is obtained, the second quantile information is obtained by testing the target device, and the second quantile information is used for representing the power consumption performance of the corresponding target device; and according to the first quantile information corresponding to each chip and the second quantile information corresponding to each target device, assembling each chip and at least one target device, wherein the overall power consumption performance of the assembled chip and target device is superior to the power consumption performance of the chip before assembly and / or the power consumption performance of the target device before assembly.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to a device assembly method and apparatus, electronic equipment, and a computer program product. Background Art

[0002] As the chip manufacturing nodes of electronic devices continue to improve, the consistency dispersion of the chip manufacturing process is getting larger and larger, resulting in greater differences in power consumption performance between electronic devices assembled with different chips. Therefore, there is an urgent need for a device assembly method for electronic devices that can reduce the power consumption performance differences. Summary of the invention

[0003] The present application provides a device assembly method and apparatus, electronic equipment, and computer program product, which can reduce the overall power consumption performance difference after chip assembly and improve the power consumption performance of electronic equipment.

[0004] In a first aspect, a device assembly method is provided, comprising: obtaining first quantile information corresponding to at least one chip, the first quantile information being obtained by testing the chip, and the first quantile information being used to characterize the power consumption performance of the corresponding chip; obtaining second quantile information corresponding to at least one target device, the second quantile information being obtained by testing the target device, and the second quantile information being used to characterize the power consumption performance of the corresponding target device; assembling each of the above-mentioned chips with at least one target device according to the first quantile information corresponding to each of the above-mentioned chips, and the second quantile information corresponding to each of the above-mentioned target devices; wherein the overall power consumption performance of the assembled chip and target device is better than the power consumption performance of the chip before assembly and / or the power consumption performance of the target device before assembly.

[0005] In an embodiment of the present application, first quantile information corresponding to at least one chip is obtained by testing the chip, and second quantile information corresponding to at least one target device is obtained by testing the target device, and based on the first quantile information corresponding to each of the above chips, and the second quantile information corresponding to each of the above target devices, wherein the first quantile information is used to characterize the power consumption performance of the corresponding chip, and the second quantile information is used to characterize the power consumption performance of the corresponding target device, each of the above chips is assembled with at least one target device, so that the overall power consumption performance of the assembled chip and the target device is better than the power consumption performance of the chip before assembly and / or the power consumption performance of the target device before assembly. The embodiment of the present application can flexibly assemble the above chips and at least one target device according to the first quantile information corresponding to the chip and the second quantile information corresponding to the target device, so that the power consumption performance of the chip complements the power consumption performance of the target device, so that the overall power consumption performance of the assembled chip and the target device is better than the power consumption performance of the chip before assembly and / or the power consumption performance of the target device before assembly, which can reduce the overall power consumption performance difference after chip assembly and improve the power consumption performance of electronic equipment.

[0006] In the second aspect, an electronic device is provided, comprising: an acquisition module and a processing module. The acquisition module is used to acquire first quantile information corresponding to at least one chip, the first quantile information is obtained by testing the chip, and the first quantile information is used to characterize the power consumption performance of the corresponding chip; acquire second quantile information corresponding to at least one target device, the second quantile information is obtained by testing the target device, and the second quantile information is used to characterize the power consumption performance of the corresponding target device; the processing module is used to assemble each of the above chips with at least one target device according to the first quantile information corresponding to each of the above chips and the second quantile information corresponding to each of the above target devices; wherein the overall power consumption performance of the assembled chip and target device is better than the power consumption performance of the chip before assembly and / or the power consumption performance of the target device before assembly.

[0007] In a third aspect, another device assembly apparatus is provided, including a processor, the processor is coupled to a memory, and can be used to execute instructions in the memory to implement the method in any possible implementation of the first aspect. Optionally, the device assembly apparatus also includes a memory. Optionally, the device assembly apparatus also includes a communication interface, and the processor is coupled to the communication interface.

[0008] In a fourth aspect, a computer program product is provided, comprising: a computer program (also referred to as code, or instruction), which, when executed, enables a computer to execute a method in any possible implementation of the first aspect.

[0009] In a fifth aspect, a computer-readable storage medium is provided, which stores a computer program (also referred to as code, or instructions) which, when executed on a computer, enables the computer to execute a method in any possible implementation of the first aspect. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 It is a schematic diagram of the system architecture provided by the embodiment of the present application;

[0011] Figure 2 is a schematic flow chart of a device assembly method provided in an embodiment of the present application;

[0012] Figure 3 is a schematic flow chart of a first specific example of a device assembly method provided in an embodiment of the present application;

[0013] Figure 4 is a schematic flow chart of a second specific example of the device assembly method provided in an embodiment of the present application;

[0014] Figure 5 is a schematic flow chart of a third specific example of the device assembly method provided in an embodiment of the present application;

[0015] Figure 6 is a schematic diagram of a first statistical histogram provided in an embodiment of the present application;

[0016] Figure 7 is a schematic flow chart of a fourth specific example of a device assembly method provided in an embodiment of the present application;

[0017] Figure 8 is a schematic flow chart of a fifth specific example of a device assembly method provided in an embodiment of the present application;

[0018] Fig. 9 It is a schematic diagram of the test results provided in the embodiment of the present application;

[0019] Fig.10 is a schematic diagram of the device assembly provided in the embodiment of the present application;

[0020] Fig.11 is a schematic flow chart of a sixth specific example of a device assembly method provided in an embodiment of the present application;

[0021] Fig.12 is a schematic diagram of a chip provided in an embodiment of the present application;

[0022] Fig.13 is a schematic block diagram of a device assembly apparatus provided in an embodiment of the present application;

[0023] Fig.14It is a schematic block diagram of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0024] The technical solution in this application will be described below in conjunction with the accompanying drawings.

[0025] In order to clearly describe the technical solutions of the embodiments of the present application, in the embodiments of the present application, words such as "first" and "second" are used to distinguish the same or similar items with substantially the same functions and effects. Those skilled in the art can understand that words such as "first" and "second" do not limit the quantity and execution order, and words such as "first" and "second" do not necessarily limit the difference.

[0026] It should be noted that, in this application, words such as "exemplarily" or "for example" are used to indicate examples, illustrations or explanations. Any embodiment or design described as "exemplarily" or "for example" in this application should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of words such as "exemplarily" or "for example" is intended to present related concepts in a specific way.

[0027] In addition, "at least one" means one or more, and "plurality" means two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone, where A and B can be singular or plural. The character " / " generally indicates that the previous and next associated objects are in an "or" relationship. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single or plural items. For example, at least one of a, b and c can mean: a, or b, or c, or a and b, or a and c, or b and c, or a, b and c, where a, b, c can be single or multiple.

[0028] In order to make the purpose and technical solution of the present application clearer and more intuitive, the device assembly method and apparatus, electronic device, and computer program product provided by the embodiments of the present application will be described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0029] With the continuous improvement of chip process nodes of electronic devices, the process yield and process deviation of the production process have brought different electrical characteristic parameter differences to the chip. For example, the process yield and process deviation of the chip production process have brought about differences in electrical characteristic parameters such as operating voltage and static leakage current of different chips. These differences, namely, inconsistency between individual chips, have led to increasing differences in power consumption performance between electronic devices corresponding to different chips.

[0030] For example, electronic devices of the same model may exhibit different power consumption performance due to differences in electrical characteristic parameters between chips.

[0031] Therefore, there is an urgent need for a method for assembling components of electronic devices that can reduce power consumption performance differences.

[0032] The embodiments of the present application provide a device assembly method and apparatus, an electronic device, and a computer program product, wherein the first quantile information corresponding to at least one chip is obtained by testing the chip, the second quantile information corresponding to at least one target device is obtained by testing the target device, and the first quantile information corresponding to each of the above chips and the second quantile information corresponding to each of the above target devices are assembled with at least one target device, so that the overall power consumption performance of the assembled chip and the target device is better than the power consumption performance of the chip before assembly and / or the power consumption performance of the target device before assembly. The embodiments of the present application can flexibly assemble the above chips and at least one target device according to the first quantile information corresponding to the chip and the second quantile information corresponding to the target device, so that the power consumption performance of the chip is complementary to the power consumption performance of the target device, so that the overall power consumption performance of the assembled chip and the target device is better than the power consumption performance of the chip before assembly and / or the power consumption performance of the target device before assembly, which can reduce the overall power consumption performance difference after chip assembly and improve the power consumption performance of the electronic device.

[0033] Figure 1 Schematic diagram of the system architecture 100 provided in this application. Figure 1 The system architecture includes a test device 101, a device assembly device 102 and an electronic device 103. The test device 101 can test a chip and a target device to obtain first quantile information corresponding to the chip and second quantile information corresponding to the target device, respectively. The device assembly device 102 can flexibly assemble the chip and the target device to obtain the electronic device 103 based on the first quantile information of the chip and the second quantile information of the target device.

[0034] In one embodiment, the test device 101 may include a plurality of different test devices.

[0035] Exemplarily, the test device 101 includes a chip test device and a target device test device. The chip test device can be used to test the chip to obtain first quantile information of the chip, and the target device test device can be used to test the target device to obtain second quantile information of the target device.

[0036] In some embodiments, the above-mentioned testing equipment 101 and device assembly equipment 102 can also be one device, that is, the functions of the testing equipment 101 and the functions of the device assembly equipment 102 can be integrated in one device (such as a processing device), so as to obtain the first quantile information corresponding to the chip and the second quantile information corresponding to the target device through the processing device, and based on the first quantile information of the chip and the second quantile information of the target device, flexibly assemble the chip and the target device to obtain the electronic device 103.

[0037] It should be understood that the assembled electronic device 103 may include not only the chip and target device used for assembly, but also devices or modules that can realize respective functions, etc., which is not limited in the present application.

[0038] The electronic device 103 involved in the embodiment of the present application can be a mobile phone, a watch, a laptop computer, a PDA, a mobile internet device (MID), a personal computer (PC), a wearable device, a virtual reality (VR) device, an augmented reality (AR) device, a wireless terminal in self-driving, a wireless terminal in a smart grid, a wireless terminal in transportation safety, a wireless terminal in a smart city, a wireless terminal in a smart home, a personal digital assistant (PDA), etc., and the embodiment of the present application is not limited to this.

[0039] Figure 2 is a schematic flow chart of a device assembly method 200 provided in an embodiment of the present application. The device assembly method 200 can be applied to Figure 1 The system architecture 100 is shown. Figure 2 As shown, the method 200 may include the following steps:

[0040] S201, obtaining first quantile information corresponding to at least one chip, where the first quantile information is obtained by testing the chip, and the first quantile information is used to characterize the power consumption performance of the corresponding chip.

[0041] The first quantile information is the result of performing power consumption tests on the chip and grading the test results of the chip. For example, the chip data (such as electrical characteristic parameters related to power consumption performance) is analyzed through testing, and the quantile of the analysis results of each chip in the overall chip is determined to obtain the first quantile information. The first quantile information can be used to reflect the level of power consumption of the chip in the overall chip, thereby characterizing the power consumption performance of the chip.

[0042] Power consumption performance refers to the amount of energy consumed by a chip per unit time, and the unit of power consumption is W (watt).

[0043] In some embodiments, the chip testing device may perform a single-chip test on each of the at least one chip to obtain first quantile information of each chip.

[0044] Exemplarily, the at least one chip includes a first chip, and when the first chip is powered on, the chip testing device can test the first chip to obtain electrical characteristic parameters corresponding to the first chip, and determine the first quantile information of the first chip according to the electrical characteristic parameters. The electrical characteristic parameters may include parameters that cause the power consumption performance of the first chip to change.

[0045] In some embodiments, the chip testing device may collect multiple first test quantile information corresponding to the first chip, and determine the first quantile information of the at least one chip based on the multiple first test quantile information. The first test quantile information may be multiple first quantile information corresponding to the first chip collected during the test time, and the multiple first quantile information may contain the same first quantile information, or may contain different first quantile information due to the instability of the electrical characteristic parameters of the first chip.

[0046] Exemplarily, the chip testing device may collect a plurality of first test quantile information of the first chip, and determine an average of the plurality of first test quantile information within a test interval as the first quantile information of the first chip.

[0047] Exemplarily, the chip testing device may collect multiple first test quantile information of the first chip, and determine the first test quantile information with the highest occurrence probability among the multiple first test quantile information as the first quantile information of the first chip.

[0048] In one possible case, the larger the first quantile information of a chip is, the worse the power consumption performance of the chip is.

[0049] In another possible case, the larger the first quantile information of the chip is, the better the power consumption performance of the chip represented may be.

[0050] In some embodiments, the first quantile information of the chip may be quantile gear information, and the first quantile information of each chip may be the same or different quantile gear information. The quantile gear information is the gear corresponding to the first quantile, and each gear includes at least one first quantile.

[0051] S202, obtaining second quantile information corresponding to at least one target device, where the second quantile information is obtained by testing the target device, and the second quantile information is used to characterize the power consumption performance of the corresponding target device.

[0052] The target device is a device in an electronic device that realizes different functions and consumes energy, and can cause changes in the overall power consumption performance of the electronic device.

[0053] The second quantile information is the result of performing power consumption tests on the target device and grading the test results of the target device. For example, the second quantile information is obtained by analyzing data (such as electrical characteristic parameters related to power consumption performance) of the target device through testing and determining the quantile of the analysis results of each target device in the overall target device. The second quantile information can be used to reflect the level of power consumption of the target device in the overall target device, thereby characterizing the power consumption performance of the target device.

[0054] In some embodiments, the target device testing equipment may perform a single-unit test on each of the at least one target device to obtain the second quantile information of each target device.

[0055] The target device testing equipment can test the target device, obtain electrical characteristic parameters corresponding to the target device, and determine the second quantile information of the target device according to the electrical characteristic parameters. The electrical characteristic parameters may include parameters that cause power consumption performance changes.

[0056] Optionally, the target device may include multiple different types of devices, for example, it may include power-consuming type target devices and power-supply type target devices, wherein the power-consuming type target devices may refer to devices that consume electrical energy during operation, such as display screens, cameras, etc.; the power-supply type target devices may refer to devices that can be used to provide electrical energy to other devices, such as batteries, etc.

[0057] In some embodiments, the target device testing equipment may collect a plurality of second test quantile information corresponding to the target device, and determine the first quantile information of each target device based on the plurality of second test quantile information.

[0058] Exemplarily, the target device testing equipment may collect a plurality of second test quantile information of the target device, and determine an average of the plurality of second test quantile information within the test interval as the second quantile information of the target device.

[0059] Exemplarily, the target device testing equipment may collect a plurality of second test quantile information of the target device, and determine the second test quantile information with the highest occurrence probability among the plurality of second test quantile information as the second quantile information of the target device.

[0060] In one possible case, the larger the second quantile information of the target device is, the worse the power consumption performance of the target device is.

[0061] In another possible case, the larger the second quantile information of the target device is, the better the power consumption performance of the target device represented may be.

[0062] In some embodiments, the second quantile information of the target device may include multiple gears, and the second quantile information of each target device may be the same or different quantile gear information.

[0063] S203, assembling each of the above chips with at least one target device according to the first quantile information corresponding to each of the above chips and the second quantile information corresponding to each of the above target devices; wherein the overall power consumption performance of the assembled chip and target device is better than the power consumption performance of the chip before assembly and / or the power consumption performance of the target device before assembly.

[0064] According to the first quantile information corresponding to each of the above chips and the second quantile information corresponding to each of the above target devices, each of the above chips can be assembled with at least one target device, so that the power consumption performance of the assembled chip and the target device complement each other. As an implementation method, a chip with poor power consumption performance can be assembled with a target device with better power consumption performance. As another implementation method, a chip with better power consumption performance can also be assembled with a target device with poor power consumption performance, so that the overall power consumption performance of the assembled chip and the target device is better than the power consumption performance of the chip before assembly and / or the power consumption performance of the target device before assembly, and the power consumption performance difference between the multiple groups of chips and target devices after assembly can be ensured to be small.

[0065] In some embodiments, the higher the quantile information is, the worse the power consumption performance is, and the quantile information of at least part of the assembled chip and the target device is less than the preset quantile information.

[0066] As a specific implementation, multiple first power consumption levels corresponding to the chip and multiple second power consumption levels corresponding to each type of target device may be pre-configured, wherein the multiple first power consumption levels may correspond to different ranges of first quantile information, and the multiple second power consumption levels may correspond to different ranges of second quantile information of different types of template devices. For example, the first quantile information corresponding to the chip includes first quantile information 1, first quantile information 2 and third quantile information 3, and the multiple first quantile information may correspond to different first power consumption levels, so as to characterize different power consumption performances of the chip, such as first quantile information 1 corresponds to first power consumption level 1, first quantile information 2 corresponds to first power consumption level 2, and the first quantile information 3 corresponds to first power consumption level 3. In the case where the target device is a class, the second quantile information corresponding to the class of target devices may include second quantile information 1, second quantile information 2 and second quantile information 3, and the multiple second quantile information may also correspond to different second power consumption levels, so as to characterize different power consumption performances of the target device, such as second quantile information 1 corresponds to second power consumption level 1, second quantile information 2 corresponds to second power consumption level 2, and second quantile information 3 corresponds to second power consumption level 3. In addition, the multiple first quantile information may include first quantile information corresponding to the same first power consumption level, and the multiple second quantile information may include second quantile information corresponding to the same second power consumption level, and the present application does not limit this.

[0067] Exemplarily, Table 1 shows at least one chip and corresponding first quantile information, and at least one target device and corresponding second quantile information.

[0068] Table 1

[0069]

[0070] As shown in Table 1, the at least one chip includes a first chip, a second chip and a third chip. The at least one target device (a target device of the same type) includes a first target device, a second target device and a third target device. Wherein, the first quantile information corresponding to the at least one chip is obtained by testing, such as the first quantile information 1 corresponding to the first chip, the first quantile information 2 corresponding to the second chip and the third quantile information 3 corresponding to the second chip, wherein the power consumption performance of the first chip is better than that of the second chip, and the power consumption performance of the second chip is better than that of the third chip. The second quantile information corresponding to the at least one target device can be obtained by testing, such as the second quantile information 1 corresponding to the first target device, the second quantile information 2 corresponding to the second target device and the second quantile information 3 corresponding to the third target device, wherein the power consumption performance of the first target device is better than that of the second target device, and the power consumption performance of the second target device is better than that of the third target device.

[0071] In some embodiments, each of the above chips can be assembled with at least one target device based on the first quantile information of the chip and the second quantile information of the target device. The quantile information of the chip and the target device used for the combination is not greater than or equal to the corresponding preset quantile information at the same time. The preset quantile information is the smallest quantile information in the corresponding preset quantile gear, and the preset quantile gear is the quantile gear representing the worst power consumption performance among the multiple quantile gears corresponding to the chip. That is, the quantile information of at least part of the assembled chip and the target device can be less than the preset quantile information.

[0072] Corresponding to the above Table 1, the power consumption performance of the first chip represented by the first quantile information 1 is better than the first quantile information 2, the power consumption performance of the second chip represented by the second quantile information 2 is better than the power consumption performance of the third chip represented by the first quantile information 3, the power consumption performance of the first target device represented by the second quantile information 1 is better than the power consumption performance of the second target device represented by the second quantile information 2, and the power consumption performance of the second target device represented by the second quantile information 2 is better than the power consumption performance of the third target device represented by the second quantile information 3, and the quantile information shown in Table 1 are respectively in different quantile gears, such as the first quantile information 1 is in the first quantile gear corresponding to the chip, the first quantile information 2 is in the second quantile gear corresponding to the chip, the first quantile information 3 is in the third quantile gear corresponding to the chip, the second quantile information 1 is in the first quantile gear corresponding to the target device, the second quantile information 2 is in the second quantile gear corresponding to the target device, and the second quantile information 3 is in the third quantile gear corresponding to the target device.

[0073] It should be understood that the above-mentioned quantile levels are merely exemplary. In addition, the above-mentioned quantile levels may also include other quantile information.

[0074] In the case where the first quantile information 3 is the smallest quantile information in the third quantile level corresponding to the chip, the first quantile information 3 can be determined as the preset quantile information in the first quantile information corresponding to the chip, and the third quantile level corresponding to the chip can be determined as the preset quantile level corresponding to the chip. In the case where the second quantile information 3 is the smallest quantile information in the third quantile level corresponding to the target device, the second quantile information 3 can be determined as the preset quantile information in the second quantile information corresponding to the target device, and the third quantile level corresponding to the target device can be determined as the preset quantile level corresponding to the target device. That is, the third chip corresponding to the first quantile information 3 can be avoided from being combined with the third target device corresponding to the second quantile information 3, and the chip corresponding to any other first quantile information in the third quantile level corresponding to the chip can be combined with the target device corresponding to any other second quantile information in the third quantile level corresponding to the target device, so as to avoid obtaining an electronic device with poor power consumption performance.

[0075] In a possible case, a chip corresponding to any first quantile information in a first quantile level corresponding to the chip may be combined with a target device corresponding to any second quantile information in a first quantile level corresponding to the target device.

[0076] Exemplarily, the first chip corresponding to the first quantile information 1 is combined with the first target device corresponding to the second quantile information 1 to obtain a combined first electronic device.

[0077] In a possible case, a chip corresponding to any first quantile information in a first quantile level corresponding to the chip may be combined with a target device corresponding to any second quantile information in a second quantile level corresponding to the target device.

[0078] Exemplarily, the first chip corresponding to the first quantile information 1 is combined with the second target device corresponding to the second quantile information 2 to obtain a combined second electronic device.

[0079] In a possible case, a chip corresponding to any first quantile information in a first quantile level corresponding to the chip may be combined with a target device corresponding to any second quantile information in a third quantile level corresponding to the target device.

[0080] Exemplarily, the first chip corresponding to the first quantile information 1 is combined with the third target device corresponding to the second quantile information 3 to obtain a combined third electronic device.

[0081] In a possible case, a chip corresponding to any first quantile information in a second quantile level corresponding to the chip may be combined with a target device corresponding to any second quantile information in a first quantile level corresponding to the target device.

[0082] Exemplarily, the second chip corresponding to the first quantile information 2 is combined with the first target device corresponding to the second quantile information 1 to obtain a combined fourth electronic device.

[0083] In a possible case, a chip corresponding to any first quantile information in a second quantile level corresponding to the chip may be combined with a target device corresponding to any second quantile information in a second quantile level corresponding to the target device.

[0084] Exemplarily, the second chip corresponding to the first quantile information 2 is combined with the second target device corresponding to the second quantile information 2 to obtain a combined fifth electronic device.

[0085] In a possible case, a chip corresponding to any first quantile information in a second quantile level corresponding to the chip may be combined with a target device corresponding to any second quantile information in a third quantile level corresponding to the target device.

[0086] Exemplarily, the second chip corresponding to the first quantile information 2 is combined with the third target device corresponding to the second quantile information 3 to obtain a combined sixth electronic device.

[0087] In a possible case, a chip corresponding to any first quantile information in a third quantile level corresponding to the chip may be combined with a target device corresponding to any second quantile information in a first quantile level corresponding to the target device.

[0088] Exemplarily, the third chip corresponding to the first quantile information 3 is combined with the first target device corresponding to the second quantile information 1 to obtain a combined seventh electronic device.

[0089] In a possible case, a chip corresponding to any first quantile information in a third quantile level corresponding to the chip may be combined with a target device corresponding to any second quantile information in a second quantile level corresponding to the target device.

[0090] Exemplarily, the third chip corresponding to the first quantile information 3 is combined with the second target device corresponding to the second quantile information 2 to obtain a combined eighth electronic device.

[0091] In summary, the preset quantile information may be other quantile information except the first quantile information 3 and the second quantile information 3 in the above Table 1.

[0092] In the present application, first quantile information corresponding to at least one chip is obtained by testing the chip, and second quantile information corresponding to at least one target device is obtained by testing the target device, and based on the first quantile information corresponding to each of the above chips and the second quantile information corresponding to each of the above target devices, wherein the first quantile information is used to characterize the power consumption performance of the corresponding chip, and the second quantile information is used to characterize the power consumption performance of the corresponding target device, each of the above chips is assembled with at least one target device, so that the overall power consumption performance of the assembled chip and the target device is better than the power consumption performance of the chip before assembly and / or the power consumption performance of the target device before assembly. The embodiment of the present application can flexibly assemble the above chips and at least one target device according to the first quantile information corresponding to the chip and the second quantile information corresponding to the target device, so that the power consumption performance of the chip complements the power consumption performance of the target device, so that the overall power consumption performance of the assembled chip and the target device is better than the power consumption performance of the chip before assembly and / or the power consumption performance of the target device before assembly, which can reduce the overall power consumption performance difference after chip assembly and improve the power consumption performance of the electronic device.

[0093] In some embodiments, current information of the at least one chip may be collected to implement testing of each of the chips and obtain first quantile information corresponding to each chip.

[0094] Illustratively, Table 2 shows the relationship between the current and power consumption performance of chips in different electronic devices under the same usage scenario provided by this application.

[0095] Table 2

[0096] Electronic devices Usage scenarios Power consumption Electronic equipment 1 First use scenario 1206.55mA Electronic equipment 2 First use scenario 1006.96mA Electronic equipment 3 First use scenario 1037.66mA Electronic equipment 4 First use scenario 933.81mA

[0097] As shown in Table 2, the power consumption of multiple electronic devices in the first usage scenario is shown. For example, the power consumption of electronic device 1 in the first usage scenario is 1206.55 mA (milliamperes), the power consumption of electronic device 2 in the first usage scenario is 1006.96 mA, the power consumption of electronic device 3 in the first usage scenario is 1037.66 mA, and the power consumption of electronic device 4 in the first usage scenario is 933.81 mA.

[0098] Due to the continuous improvement of chip manufacturing process, the process yield and process deviation of the production process, even if the electronic device 1 and the electronic device 2 are electronic devices of the same type (such as the same model), the power consumption of the electronic device 1 is greater than that of the electronic device 2, that is, the power consumption performance of the electronic device 2 is better than that of the electronic device 1. In addition, the electronic device 3 and the electronic device 4 are electronic devices of the same type, but the power consumption of the electronic device 3 is greater than that of the electronic device 4, that is, the power consumption performance of the electronic device 4 is better than that of the electronic device 3.

[0099] Through testing, it is learned that the higher the current information of the chip in the above-mentioned electronic device, the worse the power consumption performance of the chip, and the greater the power consumption and the worse the temperature rise of the corresponding electronic device. For example, the current information of the first chip in electronic device 1 is higher than the current information of the second chip in electronic device 2, and correspondingly, the power consumption of electronic device 1 is greater than the power consumption of electronic device 2. The current information of the third chip in electronic device 3 is higher than the current information of the fourth chip in electronic device 4, and correspondingly, the power consumption of electronic device 3 is greater than the power consumption of electronic device 4. Therefore, the present application can collect the current information of at least one of the above-mentioned chips to implement the test of each of the above-mentioned chips and obtain the first quantile information corresponding to each chip.

[0100] The device assembly method provided in the present application is described below by taking the first chip included in the at least one chip as an example.

[0101] Figure 3 is a schematic flow chart of a device assembly method 300 provided in an embodiment of the present application. Figure 3 As shown, the method 300 may include the following steps:

[0102] S301 , when the first chip is powered on, collecting current information of the first chip.

[0103] In some embodiments, a single-chip test is performed on the first chip to collect current information of the first chip when the first chip is powered on.

[0104] Exemplarily, the chip testing device can collect test current information of the first chip when the first chip is powered on, and determine the average value of current information in a test interval as the current information of the first chip. The test interval can be an interval in which the current information of the first chip tends to be stable.

[0105] Exemplarily, the chip testing device may also collect test current information of the first chip when the first chip is powered on, and determine the test current information with the highest probability of appearing in the test current information as the current information of the first chip.

[0106] S302, determining a first quantile at which the current information of the first chip is located, and determining first quantile information corresponding to the first chip according to the first quantile.

[0107] In some embodiments, the first quantile of the first chip may be determined based on the current information of the first chip and the first quantile corresponding to the current information, and first quantile information corresponding to the first chip may be determined according to the first quantile.

[0108] Exemplarily, Table 3 shows the first quantile of the chip and the current information of the corresponding chip.

[0109] Table 3

[0110] First chip first quartile Chip current information First quartile 1 Current information 1 First quartile 2 Current information 2 First quartile 3 Current information 3

[0111] As shown in Table 3, the first quantile of the chip may include first quantile 1, first quantile 2, and first quantile 3. The current information of the chip corresponding to different first quantiles is different. As shown in Table 3, the current information of the chip corresponding to the first quantile 1 is current information 1, the current information of the chip corresponding to the first quantile 2 is current information 2, and the current information of the chip corresponding to the first quantile 3 is current information 3.

[0112] Exemplarily, when the current information of the first chip is current information 1, based on the corresponding relationship shown in Table 3, the first quantile 1 corresponding to the current information 1 can be determined as the first quantile of the first chip; when the current information of the first chip is current information 2, the first quantile 2 corresponding to the current information 2 can be determined as the first quantile of the first chip; or, when the current information of the first chip is current information 3, the first quantile 3 corresponding to the current information 3 can be determined as the first quantile of the first chip.

[0113] It should be understood that the corresponding relationship shown in Table 3 above is merely exemplary. In addition, it may also include other specific first quantiles and corresponding chip current information, which is not limited in the present application.

[0114] In some embodiments, the first quantile of the first chip is the same as the first quantile information of the first chip.

[0115] In some embodiments, the first quantile of the first chip may be different from the first quantile information of the first chip. The first quantiles of different chips correspond to different quantile bins, and the chip testing device may determine the first quantile of the first chip based on the multiple first quantiles in the first statistical histogram, and determine the first quantile information corresponding to the first chip based on the quantile bin corresponding to the first quantile of the first chip.

[0116] Exemplarily, the first quantile 1 and the second quantile 2 correspond to the first quantile gear, and the first quantile 3 corresponds to the second quantile gear. When the first quantile of the first chip is the first quantile 1 or the first quantile 2, it can be determined that the first quantile information corresponding to the first chip is the first quantile gear. Alternatively, when the first quantile of the first chip is the first quantile 3, it can be determined that the first quantile information corresponding to the first chip is the third quantile gear.

[0117] S303, obtaining second quantile information corresponding to at least one target device, where the second quantile information is obtained by testing the target device, and the second quantile information is used to characterize the power consumption performance of the corresponding target device.

[0118] In some embodiments, the target device testing equipment may perform a single-unit test on each of the at least one target device to obtain the second quantile information of each target device.

[0119] In a possible case, the at least one target device includes a first target device. When the first target device is a power-consuming device, the target device testing equipment can obtain the second quantile information of the first target device when the first target device is powered on.

[0120] In another possible case, the at least one target device includes a second target device. When the second target device is a non-power-consuming device, the target device testing equipment can obtain the second quantile information of the second target device when the second target device is not powered on.

[0121] S304, assembling each of the above chips with at least one target device according to the first quantile information corresponding to each of the above chips and the second quantile information corresponding to each of the above target devices; wherein the overall power consumption performance of the assembled chip and target device is better than the power consumption performance of the chip before assembly and / or the power consumption performance of the target device before assembly.

[0122] In some embodiments, the device assembly equipment can obtain the power consumption performance of the chip and the target device based on the first quantile information of the chip and the second quantile information of the target device, and then flexibly combine the chip and the target device to avoid combining a chip with poor power consumption performance with a target device with poor power consumption performance to obtain an electronic device with poor power consumption performance. For specific details, please refer to the above example, and to avoid repetition, it will not be repeated here.

[0123] In an embodiment of the present application, each of the above chips can be assembled with at least one target device according to the first quantile information corresponding to each chip and the second quantile information corresponding to each of the above target devices. The larger the current information of the chip, the worse the power consumption performance of the corresponding chip. Therefore, the present application can accurately characterize the power consumption performance of the chip through the first quantile information determined by the current information of the first chip, and then realize the flexible combination of devices based on the first quantile information of the first chip and the second quantile information of at least one target device, thereby reducing the overall power consumption performance difference after chip assembly and improving the power consumption performance of electronic equipment.

[0124] In some embodiments, in order to further improve the device assembly accuracy and obtain an electronic device with higher power consumption performance, the present application can also determine the first quantile information corresponding to the chip based on the current information of the chip in the user usage scenario.

[0125] Figure 4 4 is a schematic flow chart of a device assembly method 400 provided in an embodiment of the present application. Figure 4 As shown, the method 400 may include the following steps:

[0126] S401, configuring the operating parameters of the first chip as target operating parameters; the target operating parameters are the operating parameters of the chip in a user usage scenario.

[0127] In one embodiment, the user usage scenario may be any user usage scenario among multiple user usage scenarios.

[0128] In a possible case, any one of the user usage scenarios may be a usage scenario that occurs more frequently when the user uses the electronic device.

[0129] Exemplarily, the user usage scenario may include a game usage scenario, and the chip testing device may configure the operating parameters of the first chip as target operating parameters in the game usage scenario.

[0130] In another possible case, any one of the user usage scenarios is also a usage scenario in which the power consumption is relatively high when the user uses the electronic device.

[0131] Exemplarily, the user usage scenario may be a video usage scenario, and the chip testing device may configure the operating parameters of the first chip as target operating parameters in the video usage scenario.

[0132] In some embodiments, a chip testing device can test multiple electronic devices to determine the operating parameters of multiple chips corresponding to the multiple electronic devices in user usage scenarios, and determine target operating parameters based on the operating parameters of the multiple chips.

[0133] In one possible case, the chip testing device can determine the maximum operating parameter among the operating parameters of multiple chips obtained by testing multiple electronic devices in a user usage scenario as the operating parameter of the chip in the user scenario, that is, configure the operating parameter of the first chip as the maximum operating parameter among the operating parameters of the multiple chips.

[0134] In another possible case, the chip testing equipment may also determine the working parameters with the highest frequency among the working parameters of multiple chips obtained by testing multiple electronic devices in the user usage scenario as the working parameters of the chip in the user scenario, that is, configure the working parameters of the first chip as the working parameters with the highest frequency among the working parameters of the above-mentioned multiple chips.

[0135] S402 , when the first chip is powered on, controlling the first chip to operate based on the target operating parameters, and collecting current information of the first chip.

[0136] In some embodiments, the chip testing equipment can control the first chip to operate based on the above-mentioned target engineering parameters when the first chip is powered on, so that the first chip simulates the state of the chip running in the user usage scenario to collect the current information of the first chip in the user usage scenario.

[0137] S403, determining a first quantile at which the current information of the first chip is located, and determining first quantile information corresponding to the first chip according to the first quantile.

[0138] In some embodiments, the first quantile of the first chip can be determined based on the current information of the first chip and the first quantile in which the current information has a corresponding relationship, and the first quantile information corresponding to the first chip can be determined according to the first quantile. For specific details, please refer to the above embodiment, and will not be repeated here to avoid repetition.

[0139] S404, obtaining second quantile information corresponding to at least one target device, where the second quantile information is obtained by testing the target device, and the second quantile information is used to characterize the power consumption performance of the corresponding target device.

[0140] In some embodiments, the target device testing equipment may perform a single-unit test on each of the at least one target device to obtain the second quantile information of each target device.

[0141] In a possible case, the at least one target device includes a first target device. When the first target device is a power-consuming device, the target device testing equipment can obtain the second quantile information of the first target device when the first target device is powered on.

[0142] In another possible case, the at least one target device includes a second target device. When the second target device is a non-power-consuming device, the target device testing equipment can obtain the second quantile information of the second target device when the second target device is not powered on.

[0143] S405, assembling each of the above chips with at least one target device according to the first quantile information corresponding to each of the above chips and the second quantile information corresponding to each of the above target devices; wherein the overall power consumption performance of the assembled chip and target device is better than the power consumption performance of the chip before assembly and / or the power consumption performance of the target device before assembly.

[0144] In some embodiments, the device assembly equipment can flexibly combine the chip and the target device based on the first quantile information of the chip and the second quantile information of the target device to avoid combining a chip with poor power consumption performance with a target device with poor power consumption performance to obtain an electronic device with poor power consumption performance. For details, please refer to the above example, and to avoid repetition, it will not be repeated here.

[0145] In an embodiment of the present application, the first quantile of the current information of the first chip can be determined through the current information of the first chip, and the first quantile information corresponding to the first chip can be determined based on the first quantile, and the second quantile information corresponding to at least one target device can be obtained through testing, and each of the above chips can be assembled with at least one target device based on the first quantile information corresponding to each of the above chips and the second quantile information corresponding to each of the above target devices. Among them, the current information of the first chip is the current information in the user scenario, and a more accurate first quantile can be determined based on the current information in the user scenario, and then the first quantile information that can characterize more accurate functional performance can be determined, so as to achieve more flexible device assembly based on the first quantile information and the second quantile information, reduce the overall power consumption performance difference after chip assembly, and improve the power consumption performance of electronic equipment.

[0146] In some embodiments, the first quantile of the chip is obtained based on a statistical histogram of current information of the chip obtained by testing a plurality of different chips.

[0147] Figure 5 is a schematic flow chart of a device assembly method 500 provided in an embodiment of the present application. Figure 5 As shown, the method 500 may include the following steps:

[0148] S501 , when multiple chips are powered on, collecting current information corresponding to the multiple chips respectively.

[0149] S502: Generate a first statistical histogram according to current information corresponding to the multiple chips.

[0150] In some embodiments, the chip testing device can generate a first statistical histogram of the current information of the chip based on the current information of the plurality of chips collected above. Figure 6 .

[0151] S503: Divide the current information in the first statistical histogram into equal parts according to the target quantity.

[0152] In some embodiments, the target number may be determined based on an interval of the current information of the first statistical histogram, and the larger the interval is, the higher the target number may be.

[0153] Figure 6 This is the first statistical histogram provided by this application. Figure 6 As shown, the horizontal axis of the first statistical histogram can be current information (such as current value), and the vertical axis can be the number of chips corresponding to different current information or the proportion of the total number of chips. Figure 6 As shown, the target number can be 10, and the current values ​​in the first statistical histogram can be divided into 10 equal parts so that the current values ​​of different chips fall on different coordinate positions, that is, the first quantiles corresponding to the chips are obtained, such as the first quantile 5 and the first quantile 10.

[0154] S504, determining a first quantile at which the current information of the first chip is located in a first statistical histogram, and determining first quantile information corresponding to the first chip according to the first quantile.

[0155] In some embodiments, the chip testing equipment may determine a first quantile of the chip based on the target number, and the first quantile may include a target number of quantiles.

[0156] like Figure 6As shown, the first quantile of the chip can be obtained, and the first quantile may include first quantile 1, first quantile 2, first quantile 3, first quantile 4, first quantile 5, first quantile 6, first quantile 7, first quantile 8, first quantile 9, and first quantile 10.

[0157] In some embodiments, the first quantile of the first chip is the same as the first quantile information of the first chip.

[0158] For example, when the current information of the first chip is the current information corresponding to the first quantile 5 in the figure, it can be determined that the first quantile of the first chip is Figure 6 The first quantile 5 in the data, and it can be determined that the first quantile information of the first chip is also the first quantile 5.

[0159] In some embodiments, the first quantile of the first chip may be different from the first quantile information of the first chip. The first quantile of the chip corresponds to multiple quantile positions, and the chip testing device can determine the first quantile of the first chip based on the multiple first quantiles in the first statistical histogram, and determine the first quantile information based on the first quantile, that is, determine the quantile position corresponding to the first quantile as the first quantile information.

[0160] For example, when the current information of the first chip is the current information corresponding to the first quantile 5 in the figure, it can be determined that the first quantile of the first chip is Figure 6 The first quartile of 5. Figure 6 In the case where the first quartile 1 and the first quartile 2 correspond to the first quartile gear, the first quartile 3 and the first quartile 4 correspond to the second quartile gear, the first quartile 5 and the first quartile 6 correspond to the third quartile gear, the first quartile 7 and the first quartile 8 correspond to the fourth quartile gear, and the first quartile 9 and the first quartile 10 correspond to the fifth quartile gear, it can be determined that the first quartile information corresponding to the first chip is the third quartile gear.

[0161] S505 , obtaining second quantile information corresponding to at least one target device, where the second quantile information is obtained by testing the target device, and the second quantile information is used to characterize the power consumption performance of the corresponding target device.

[0162] In some embodiments, the target device testing equipment may perform a single-unit test on each of the at least one target device to obtain the second quantile information of each target device.

[0163] In a possible case, the at least one target device includes a first target device. When the first target device is a power-consuming device, the target device testing equipment can obtain the second quantile information of the first target device when the first target device is powered on.

[0164] In another possible case, the at least one target device includes a second target device. When the second target device is a non-power-consuming device, the target device testing equipment can obtain the second quantile information of the second target device when the second target device is not powered on.

[0165] S506, assembling each of the above chips with at least one target device according to the first quantile information corresponding to each of the above chips and the second quantile information corresponding to each of the above target devices; wherein the overall power consumption performance of the assembled chip and target device is better than the power consumption performance of the chip before assembly and / or the power consumption performance of the target device before assembly.

[0166] In some embodiments, the device assembly equipment can flexibly combine the chip and the target device based on the first quantile information of the chip and the second quantile information of the target device to avoid combining a chip with poor power consumption performance with a target device with poor power consumption performance to obtain an electronic device with poor power consumption performance. For details, please refer to the above example, and to avoid repetition, it will not be repeated here.

[0167] In an embodiment of the present application, the first quantile of the current information of the first chip can be determined through the current information and the first quantile of the first chip, and the first quantile information corresponding to the first chip can be determined according to the first quantile, and each of the above chips can be assembled with at least one target device according to the first quantile information corresponding to each chip and the second quantile information corresponding to each of the above target devices. Among them, the larger the current information of the chip, the worse the power consumption performance of the corresponding chip, so the present application can obtain the first quantile of the first chip through the statistical histogram of the current information of the chip obtained by testing multiple different chips through the current information of the first chip, and then determine the first quantile information that can accurately characterize the power consumption performance of the chip based on the first quantile, and realize flexible combination of devices based on the first quantile information of the first chip and the second quantile information of at least one target device, thereby reducing the overall power consumption performance difference after chip assembly and improving the power consumption performance of electronic equipment.

[0168] In some embodiments, the target device includes a display screen, and when the display screen displays a test image, current information of the display screen can be collected, and the second percentile of the current information of the display screen can be determined based on the current information of the display screen, and the second percentile information corresponding to the display screen can be determined based on the second percentile.

[0169] Figure 7 is a schematic flow chart of a device assembly method 700 provided in an embodiment of the present application. Figure 7 As shown, the method 700 may include the following steps:

[0170] S701 , when a first chip is powered on, collecting current information of the first chip.

[0171] S702, determine a first quantile at which the current information of the first chip is located, and determine first quantile information corresponding to the first chip according to the first quantile.

[0172] Here, the details of S701 and S702 can refer to the description of the above embodiment, and will not be described here to avoid repetition.

[0173] S703, when the display screen displays a test image, collecting current information of the display screen.

[0174] As above, the test can reveal that the current information of the display screen is related to the power consumption performance, so the target device test equipment can perform a single-body test on the display screen to collect the current information of the display screen while the display screen displays the test image.

[0175] S704, determining the second quantile of the current information of the display screen based on the current information of the display screen, and determining second quantile information corresponding to the display screen according to the second quantile.

[0176] In some embodiments, the second quantile of the display screen may be determined based on the current information of the display screen and the second quantile in which the current information has a corresponding relationship, and second quantile information corresponding to the display screen may be determined according to the second quantile.

[0177] Exemplarily, Table 4 shows the second quartile of the display screen and the corresponding current information of the display screen.

[0178] Table 4

[0179] Second quartile of display screen Current information on the display Second quartile 1 Current information 1 Second quartile 2 Current information 2 Second quartile 3 Current information 3

[0180] As shown in Table 4, the second quantile of the display screen may include second quantile 1, second quantile 2, and second quantile 3. The current information of the display screen corresponding to different second quantiles is different. As shown in Table 4, the current information of the display screen corresponding to the second quantile 1 is current information 1, the current information of the display screen corresponding to the second quantile 2 is current information 2, and the current information of the display screen corresponding to the second quantile 3 is current information 3.

[0181] Exemplarily, when the current information of the display screen of this single test is current information 1, the second quantile 1 corresponding to the current information 1 can be determined as the second quantile of the display screen based on the corresponding relationship shown in Table 4; when the current information of the display screen is current information 2, the second quantile 2 corresponding to the current information 2 can be determined as the second quantile of the display screen; or, when the current information of the display screen is current information 3, the second quantile 3 corresponding to the current information 3 can be determined as the second quantile of the display screen.

[0182] It should be understood that the corresponding relationship shown in Table 4 above is merely exemplary. In addition, it may also include other specific second quantiles and corresponding current information of the display screen, and the present application does not limit this.

[0183] In some embodiments, the multiple second quantiles of the display screen shown in the above Table 4 are obtained by testing multiple different display screens.

[0184] Exemplarily, when the test image is displayed on multiple different display screens, current information of the multiple different display screens can be collected to obtain a second statistical histogram of the current information of the multiple different display screens, and the current information in the second statistical histogram can be equally divided according to the target number to obtain multiple second quantiles shown in Table 4 above. For specific details, refer to the acquisition of the first quantile of the chip in the above embodiment.

[0185] In some embodiments, the second percentile of the display screen is the same as the second percentile information of the display screen.

[0186] In some embodiments, the second quantile of the display screen may be different from the second quantile information of the display screen. The second quantile of the display screen corresponds to multiple quantile levels, and the target device test equipment may determine the second quantile of the display screen based on the multiple second quantiles in the second statistical histogram, and determine the second quantile information of the display screen based on the second quantile, that is, determine the quantile level of the second quantile as the second quantile information of the display screen.

[0187] S705. Assemble each of the above chips with at least one target device according to the first quantile information corresponding to each of the above chips and the second quantile information corresponding to each of the above target devices; wherein the overall power consumption performance of the assembled chip and target device is better than the power consumption performance of the chip before assembly and / or the power consumption performance of the target device before assembly.

[0188] In some embodiments, the device assembly equipment can obtain the power consumption performance of the chip and the display screen based on the first quantile information of the chip and the second quantile information of the display screen, and then flexibly combine the chip and the display screen to avoid combining a chip with poor power consumption performance with a display screen with poor power consumption performance to obtain an electronic device with poor power consumption performance.

[0189] In an embodiment of the present application, each of the above chips is assembled with at least one target device according to the first quantile information corresponding to each of the above chips and the second quantile information corresponding to each of the above target devices. The first quantile information and the second quantile information can both characterize the power consumption performance of the corresponding device, and the target device can include a display screen that has a greater impact on the power consumption performance of the electronic device obtained by the combination. Therefore, the present application can flexibly combine the chip and the target device according to the first quantile information of the chip and the second quantile information of the display screen, thereby reducing the overall power consumption performance difference after the chip is assembled and improving the power consumption performance of the electronic device.

[0190] In some embodiments, the target device includes a battery, power consumption information of the battery can be collected, the third quantile of the power consumption information of the battery is determined based on the power consumption information of the battery, and the second quantile information corresponding to the battery is determined according to the third quantile.

[0191] Figure 8 8 is a schematic flow chart of a device assembly method 800 provided in an embodiment of the present application. Figure 8 As shown, the method 800 may include the following steps:

[0192] S801 , when a first chip is powered on, collecting current information of the first chip.

[0193] S802, determine a first quantile at which the current information of the first chip is located, and determine first quantile information corresponding to the first chip according to the first quantile.

[0194] Here, the details of S801 and S802 can refer to the description of the above embodiment, and will not be described here to avoid repetition.

[0195] S803, collecting battery power consumption information.

[0196] The power consumption information of the battery is related to the power consumption performance, so the target device test equipment can perform a single-cell test on the battery to collect the power consumption information of the battery. The power consumption information can be the power consumption of the battery during the test period.

[0197] S804, determining a third quantile of the power consumption information of the battery based on the power consumption information of the battery, and determining second quantile information corresponding to the battery according to the third quantile.

[0198] In some embodiments, the third quantile of the battery can be determined based on the power consumption information of the battery and the third quantile corresponding to the power consumption information, and the second quantile information corresponding to the battery can be determined according to the third quantile.

[0199] Exemplarily, Table 5 shows the third quantile of the battery and the corresponding power consumption information of the battery.

[0200] Table 5

[0201] The third quartile of the battery Battery consumption information Third quartile 1 Power consumption information 1 Third quartile 2 Power consumption information 2 Third quartile 3 Power consumption information 3

[0202] As shown in Table 5, the third quartile of the battery may include third quartile 1, third quartile 2 and third quartile 3. The power consumption information of the battery corresponding to different third quartiles is different. As shown in Table 5, the power consumption information of the battery corresponding to the third quartile 1 is power consumption information 1, the power consumption information of the battery corresponding to the third quartile 2 is power consumption information 2, and the power consumption information of the battery corresponding to the third quartile 3 is power consumption information 3.

[0203] Exemplarily, when the power consumption information of the battery is power consumption information 1, the third quantile 1 corresponding to the power consumption information 1 can be determined as the third quantile of the battery based on the corresponding relationship shown in Table 5; when the power consumption information of the battery is power consumption information 2, the third quantile 2 corresponding to the power consumption information 2 can be determined as the third quantile of the battery; or, when the power consumption information of the battery is power consumption information 3, the third quantile 3 corresponding to the power consumption information 3 can be determined as the third quantile of the battery.

[0204] It should be understood that the corresponding relationship shown in the above Table 5 is only exemplary. In addition, it may also include multiple other specific third quantiles and corresponding battery power consumption information, and the present application does not limit this.

[0205] In some embodiments, the multiple third quantiles of the battery shown in the above Table 5 are obtained by testing multiple different batteries.

[0206] Exemplarily, the power consumption information of the multiple different batteries is collected to obtain a third statistical histogram of the power consumption information of the multiple different batteries, and the power consumption information in the third statistical histogram can be equally divided according to the target number to obtain multiple third quantiles shown in the above Table 5. For specific details, refer to the acquisition of the first quantile of the chip in the above embodiment.

[0207] In some embodiments, the third quantile of the battery is the same as the second quantile information of the battery.

[0208] In some embodiments, the third quantile of the battery may be different from the second quantile information of the battery. The third quantile of the battery corresponds to multiple quantile positions, and the target device test equipment may determine the third quantile of the battery based on the multiple third quantiles in the third statistical histogram, and determine the second quantile information of the battery at the quantile position based on the third quantile.

[0209] S805. Assemble each of the above chips with at least one target device according to the first quantile information corresponding to each of the above chips and the second quantile information corresponding to each of the above target devices; wherein the overall power consumption performance of the assembled chip and target device is better than the power consumption performance of the chip before assembly and / or the power consumption performance of the target device before assembly.

[0210] In some embodiments, the device assembly equipment can obtain the power consumption performance of the chip and the battery based on the first quantile information of the chip and the second quantile information of the battery, and then flexibly combine the chip and the battery to avoid combining a chip with poor power consumption performance with a battery with poor power consumption performance to obtain an electronic device with poor power consumption performance.

[0211] In an embodiment of the present application, each of the above chips is assembled with at least one target device according to the first quantile information corresponding to each of the above chips and the second quantile information corresponding to each of the above target devices. The first quantile information and the second quantile information can both characterize the power consumption performance of the corresponding device, and the target device can include a battery that has a greater impact on the power consumption performance of the electronic device obtained by the combination. Therefore, the present application can flexibly combine the chip and the target device according to the first quantile information of the chip and the second quantile information of the display screen, thereby reducing the overall power consumption performance difference after the chip is assembled and improving the power consumption performance of the electronic device.

[0212] The device assembly method provided in the present application is described in detail below by taking the target device including a display screen and a battery as an example.

[0213] Fig. 9 A schematic diagram of the test results provided for this application. Fig. 9 The figure shows a plurality of chips and a plurality of target devices for assembly, and a schematic diagram of the position distribution and position distribution information corresponding to the plurality of chips and the plurality of target devices obtained by testing. Fig. 9As shown, the multiple chips used for assembly include chip 1, chip 2 and chip 3, the first quantile of chip 1 is any quantile in (0 to 30 quantiles), the first quantile information of chip 1 is a first quantile gear, the first quantile of chip 2 is any quantile in (30 to 70 quantiles), the first quantile information of chip 2 is a second quantile gear, the first quantile of chip 3 is any quantile in (70 to 100 quantiles), and the first quantile information of chip 3 is a third quantile gear. The target device for assembly includes multiple display screens and multiple batteries, the multiple display screens include display screen 1, display screen 2 and display screen 3, the second quantile of display screen 1 is any quantile in (0 to 30 percentiles), the second quantile information of display screen 1 is a first quantile gear, the second quantile of display screen 2 is any quantile in (30 to 70 percentiles), the second quantile information of display screen 2 is a second quantile gear, the second quantile of display screen 3 is any quantile in (70 to 100 percentiles), and the second quantile information of display screen 3 is a third quantile gear. The multiple batteries include battery 1, battery 2 and battery 3, the third quantile of battery 1 is any quantile in (0-30 quantiles), the second quantile information of battery 1 is the first quantile gear, the third quantile of battery 2 is any quantile in (30-70 quantiles), the second general quantile information of battery 2 is the second quantile gear, the third quantile of battery 3 is any quantile in (70-100 quantiles), and the second general quantile information of battery 3 is the third quantile gear.

[0214] In some embodiments, the device assembly equipment may Fig. 9 The multiple chips and multiple target devices shown are combined, and during the assembly process, chips with poor power consumption performance are avoided from being assembled with target devices with poor power consumption performance, so as to obtain an electronic device with high power consumption performance.

[0215] When the higher the percentile (the higher the percentile gear), the worse the power consumption performance represented, the device assembly equipment can avoid assembling high-percentile (high-percentile gear) chips with high-percentile (high-percentile gear) target devices. For details, see the following Fig. 9 .

[0216] Fig.10 Schematic diagram of the device assembly provided in this application. Fig.10The device assembly apparatus can assemble the chip 1, the display screen 3 and the battery 3 to obtain the assembled first electronic device. The first quantile of the chip 1 is any quantile in (0-30 quantiles), the first quantile information corresponding to the chip 1 is the first quantile gear, the second quantile of the display screen 3 is any quantile in (70-100 quantiles), the second quantile information corresponding to the display screen 3 is the third quantile gear, the third quantile of the battery 3 is any quantile in (70-100 quantiles), and the second quantile information corresponding to the battery 3 is the third quantile gear.

[0217] Exemplarily, the daily power consumption of chip 1 with the best power consumption performance among the above-mentioned multiple chips is 100mAh (milliampere-hours) less than the daily power consumption of chip 3 with the worst power consumption performance, such as 50mAh. The daily power consumption of display screen 3 with the worst power consumption performance among the above-mentioned multiple display screens is 30mAh more than that of display screen 1 with the best power consumption performance. The battery 3 with poor power consumption performance among the above-mentioned multiple batteries has a battery current of 50mAh less than that of battery 1 with the best power consumption performance. By assembling chip 3, display screen 1 and battery 1, the target device with the worst power consumption performance is compensated in hardware to reduce the difference in power consumption per day, and obtain a first electronic device with better power consumption performance.

[0218] like Fig.10 As shown, the device assembly apparatus can also assemble the chip 2, the display screen 2 and the battery 2 to obtain an assembled second electronic device. The first quantile of the chip 2 is any quantile in (30-70 quantiles), the first quantile information corresponding to the chip 2 is the second quantile position, the second quantile of the display screen 2 is any quantile in (30-70 quantiles), the second quantile information corresponding to the display screen 2 is the second quantile position, the third quantile of the battery 2 is any quantile in (30-70 quantiles), and the second quantile information corresponding to the battery 2 is the second quantile position.

[0219] Exemplarily, the daily power consumption of chip 2 with medium power consumption performance among the above-mentioned multiple chips is at most 80mAh, the daily power consumption of display screen 2 with medium power consumption performance among the above-mentioned multiple display screens may be 10mAh less than that of display screen 3 with the worst power consumption performance, such as 200mAh, and the battery 2 with medium power consumption performance among the above-mentioned multiple batteries has a battery current of 30mAh more than that of battery 3 with the worst power consumption performance, such as 100mAh. By assembling chip 2, display screen 2 and battery 2, the daily power consumption of the second electronic device obtained may be about 0mAh different, that is, through assembly from hardware complementarity, a second electronic device with better power consumption performance is obtained.

[0220] like Fig.10As shown, the device assembly apparatus can also assemble the chip 3, the display screen 1 and the battery 1 to obtain an assembled third electronic device. The first quantile of the chip 3 is any quantile in (70-100 quantiles), the first quantile information corresponding to the chip 3 is the third quantile position, the second quantile of the display screen 1 is any quantile in (0-30 quantiles), the second quantile information corresponding to the display screen 2 is the first quantile position, the third quantile of the battery 1 is any quantile in (0-30 quantiles), and the second quantile information corresponding to the battery 2 is the first quantile position.

[0221] Exemplarily, chip 3 with the worst power consumption performance among the above-mentioned multiple chips consumes a maximum of 100mAh a day, the display screen with the best power consumption performance among the above-mentioned multiple displays can consume 30mAh less power a day than display screen 3 with the worst power consumption performance, and battery 1 with the best power consumption performance among the above-mentioned multiple batteries has a battery current of 50mAh more than battery 3 with the worst power consumption performance. By assembling chip 3, display screen 1 and battery 1, the power consumption of the third electronic device obtained is only about 20mAh different per day, that is, the power consumption of the chip with the worst power consumption performance is compensated by hardware through assembly, and a third electronic device with better power consumption performance is obtained.

[0222] It should be understood that the above Fig.10 The device assembly shown is merely exemplary. In addition, the chip 1, display screen 2 and battery 2 may be assembled, the chip 1, display screen 1 and battery 1 may be assembled, the chip 2, display screen 1 and battery 1 may be assembled, the chip 2, display screen 3 and battery 3 may be assembled, and the chip 3, display screen 2 and battery 2 may be assembled. The present application does not limit this.

[0223] In some embodiments, in order to further improve the power consumption performance of the assembled electronic device, the working parameters of the chip can also be configured based on the first quantile information of the chip. The first quantile information can be written to the non-volatile storage corresponding to the first chip, so that the assembled electronic device can read the first quantile information from the non-volatile storage, and configure the working parameters of the chip based on the first quantile information.

[0224] Fig.11 1 is a schematic flow chart of a device assembly method 1100 provided in an embodiment of the present application. Fig.11 As shown, the method 1100 may include the following steps:

[0225] S1101, obtaining first quantile information corresponding to at least one chip, where the first quantile information is obtained by testing the chip, and the first quantile information is used to characterize the power consumption performance of the corresponding chip.

[0226] For specific details, please refer to the above embodiments, and will not be described again here to avoid repetition.

[0227] S1102, writing the first quantile information into the non-volatile memory corresponding to the first chip.

[0228] In some embodiments, in order to improve configuration efficiency, the acquired first quantile information of the chip can be written into the non-volatile memory corresponding to each chip, so that when the assembled electronic device is started, the first quantile information is read from the non-volatile memory corresponding to the chip, and the working parameters of the chip are configured according to the first quantile information.

[0229] Exemplarily, the first quantile information can be written into an electronic fuse (eFuse) corresponding to the first chip, so that when the assembled electronic device is started, the first quantile information is read from the eFuse corresponding to the chip, and the working parameters of the first chip are configured according to the first quantile information.

[0230] Among them, eFuse is a non-volatile memory device used to store information and protect chips. It has the characteristics of small size, low power consumption, strong programmability, high reliability, and not easy to be erased. It can meet the storage needs of the first quantile information of the chip, while enabling the assembled electronic device to efficiently obtain the first quantile information of the chip through the eFuse, and configure the working parameters of the first chip based on the first quantile information.

[0231] Optionally, the first quantile information can also be stored in a server corresponding to the chip, so that when the assembled electronic device is started, it can also obtain the above-mentioned first quantile information from the server. While improving the flexibility of obtaining the first quantile information, it also avoids the inability to read the locally stored first quantile information, resulting in the problem of obstruction of configuring the working parameters of the chip.

[0232] Exemplarily, the server may store the chip identifier of the first chip and the first quantile information of the first chip. When the assembled electronic device is started, it may also send a quantile request message carrying the chip identifier to the server. Correspondingly, the server may receive the quantile request message, determine the first quantile information of the first chip in the quantile information of the chip stored in it based on the chip identifier carried in the quantile request message, and send the first quantile information to the assembled electronic device, so that the assembled electronic device configures the working parameters of the first chip according to the first quantile information.

[0233] S1103, obtaining second quantile information corresponding to at least one target device, where the second quantile information is obtained by testing the target device, and the second quantile information is used to characterize the power consumption performance of the corresponding target device.

[0234] S1104, assembling each of the above chips with at least one target device according to the first quantile information corresponding to each of the above chips and the second quantile information corresponding to each of the above target devices; wherein the overall power consumption performance of the assembled chip and target device is better than the power consumption performance of the chip before assembly and / or the power consumption performance of the target device before assembly.

[0235] Here, the details of S1103 and S1104 can be found in the above embodiments, and will not be described again here to avoid repetition.

[0236] S1105, reading the first quantile information from the non-volatile memory corresponding to the chip, and configuring the working parameters of the first chip according to the first quantile information.

[0237] In some embodiments, the assembled electronic device can read the first quantile information from the non-volatile memory corresponding to the chip when powered on, and configure the working parameters of the first chip according to the first quantile information.

[0238] Exemplarily, when the assembled electronic device is powered on for the first time after leaving the factory, it can read the first quantile information from the non-volatile memory corresponding to the chip, and configure the working parameters of the first chip according to the first quantile information.

[0239] In some embodiments, the assembled electronic device may also respond to a configuration trigger operation on the chip, read the first quantile information from the non-volatile memory corresponding to the chip, and configure the working parameters of the first chip according to the first quantile information.

[0240] In some embodiments, the assembled electronic device can configure the working parameters of the first chip based on the first quantile information and configuration reference information of the chip.

[0241] Exemplarily, Table 6 shows configuration reference information.

[0242] Table 6

[0243] First quantile information of the chip Chip operating parameters Percentile information 1 Working parameters 1 Percentile information 2 Working parameters 2 Percentile information 3 Working parameters 3

[0244] As shown in Table 6, the configuration reference information includes first quantile information of multiple chips, such as quantile information 1, quantile information 2, and quantile information 3. And the working parameters corresponding to the first quantile information of the multiple chips, such as working parameter 1 corresponding to quantile information 1, working parameter 2 corresponding to quantile information 2, and working parameter 3 corresponding to quantile information 3, are used to instruct the assembled electronic device to configure the working parameters of the chip to the working parameters corresponding to the first quantile information when the first quantile information of the chip is different.

[0245] Exemplarily, when the first quantile information is written into the eFuse corresponding to the first chip, the assembled electronic device can read the above-mentioned first quantile information from the eFuse corresponding to the chip. When it is determined that the first quantile information is quantile information 1 shown in Table 6, the working parameters of the first chip can be configured as working parameters 1 corresponding to the quantile information 1 in Table 6; when it is determined that the first quantile information is quantile information 2 shown in Table 6, the working parameters of the first chip can be configured as working parameters 2 corresponding to the quantile information 2 in Table 6; or, when it is determined that the first quantile information is quantile information 3 shown in Table 6, the working parameters of the first chip can be configured as working parameters 3 corresponding to the quantile information 3 in Table 6.

[0246] It should be understood that the configuration reference information shown in Table 6 above is only exemplary, and in addition, the configuration reference information may also include first quantile information of other multiple chips and operating parameters corresponding to the first quantile information. This application does not limit this.

[0247] In the embodiment of the present application, the assembled electronic device can obtain the first quantile information of the chip, and configure the working parameters of the chip based on the first quantile information of the chip. The first quantile information is stored in the non-volatile memory of the corresponding chip, and the assembled electronic device can efficiently read the first quantile information from the non-volatile memory corresponding to the chip, and while achieving the efficient configuration effect of the working parameters of the chip based on the first quantile information, the power consumption performance of the assembled electronic device is further improved.

[0248] In some embodiments, the chip may include multiple chip modules, and the assembled electronic device may configure the working parameters corresponding to at least one chip module of the chip based on the first quantile information of the chip to achieve more flexible configuration of the chip's working parameters.

[0249] Exemplarily, Table 7 shows another configuration reference information.

[0250] Table 7

[0251]

[0252] As shown in Table VII, the configuration reference information includes first quantile information of multiple chips, such as quantile information 1, quantile information 2 and quantile information 3, and working parameters of chip modules corresponding to the first quantile information of the multiple chips, such as working parameter 1 of chip module 1 and working parameter 2 of chip module 2 corresponding to quantile information 1, working parameter 3 of chip module 3 and working parameter 4 of chip module 4 corresponding to quantile information 2, working parameter 5 of chip module 5 and working parameter 6 of chip module 6 corresponding to quantile information 3, so as to indicate that the assembled electronic device, in the case of different first quantile information of the chips, configures the working parameters of at least one chip module included in the chip to the working parameters of the chip module corresponding to the first quantile information.

[0253] When it is determined that the first quantile information is quantile information 1 shown in Table 7, the assembled electronic device can configure the operating parameters of the chip module included in the first chip to the operating parameters of the chip module corresponding to the quantile information 1 in Table 7.

[0254] Exemplarily, when it is determined that the first quantile information is the quantile information 1 shown in Table VII, the assembled electronic device can configure the working parameters of the chip module 1 included in the first chip to the working parameters 1 corresponding to the quantile information 1 in Table VII, and / or configure the working parameters of the chip module 2 included in the first chip to the working parameters 2 corresponding to the quantile information 1 in Table VII.

[0255] When it is determined that the first quantile information is quantile information 2 shown in Table 7, the assembled electronic device can configure the operating parameters of the chip module included in the first chip to the operating parameters corresponding to the quantile information 2 in Table 7.

[0256] Exemplarily, when it is determined that the first quantile information is the quantile information 2 shown in Table VII, the assembled electronic device can configure the working parameters of the chip module 3 included in the first chip to the working parameters 3 corresponding to the quantile information 2 in Table VII, and / or configure the working parameters of the chip module 4 included in the first chip to the working parameters 4 corresponding to the quantile information 2 in Table VII.

[0257] Optionally, the chip module 3 and the chip module 4 here may be modules with the same functions as the chip module 1 and the chip module 2 mentioned above, or may be modules with different functions.

[0258] When it is determined that the first quantile information is the quantile information 3 shown in Table 7, the assembled electronic device can configure the operating parameters of the chip module included in the first chip to the operating parameters of the chip module corresponding to the quantile information 3 in Table 7.

[0259] Exemplarily, when it is determined that the first quantile information is the quantile information 3 shown in Table VII, the assembled electronic device can configure the working parameters of the chip module 5 included in the first chip to the working parameters 5 corresponding to the quantile information 3 in Table VII, and / or configure the working parameters of the chip module 6 included in the first chip to the working parameters 6 corresponding to the quantile information 3 in Table VII.

[0260] Optionally, the chip module 5 and the chip module 6 here may be modules with the same functions as the chip module 1 and the chip module 2 described above, or may be modules with different functions.

[0261] It should be understood that the configuration reference information shown in Table 7 above is merely exemplary. In addition, the configuration reference information may also include the first quantile information of multiple other chips and the working parameters of the chip modules corresponding to the first quantile information. This application does not limit this.

[0262] Fig.12 Schematic diagram of chip 1200 provided in this application. Fig.12 As shown, the chip 1200 may include multiple chip modules, which may include a central processing unit (CPU) 1201, a graphics processing unit (GPU) 1202, a display processor (DPU) 1203, a video processor (video processing unit) 1204, a modem sub-system (MD) 1205 and a memory controller (DDRC).

[0263] It should be understood that the above Fig.12 The chip modules of the chip shown are merely exemplary. In addition, the chip may also include other chip modules, such as a neural processing unit (NPU), etc., which is not limited in this application.

[0264] In some embodiments, the chip module for performing the working parameter configuration operation is factory-set.

[0265] Exemplarily, CPU 1201, GPU 1202 and DDRC 1203 have a greater impact on power consumption performance. The assembled electronic device can configure the CPU 1201, GPU 1202 and DDRC 1203 included in the first chip according to the above-mentioned first quantile information to further improve the power consumption performance of the assembled electronic device.

[0266] In some embodiments, the chip module that performs the working parameter configuration operation is configured according to user settings.

[0267] In some embodiments, the assembled electronic device may also determine a chip module for performing working parameter configuration operations based on the status information.

[0268] In one possible case, when it is determined that the state information meets a preset condition, the assembled electronic device can determine and configure the working parameters of all chip modules.

[0269] Exemplarily, the status information may be the power of the assembled electronic device, and the preset condition may be that the power of the assembled electronic device is greater than or equal to a power threshold. When it is determined that the power of the assembled electronic device is greater than the power threshold, the assembled electronic device may configure the operating parameters of all chip modules included in the chip.

[0270] In another possible case, when it is determined that the state information does not meet the preset conditions, the assembled electronic device can also determine the working parameters of the configured part of the chip modules.

[0271] Exemplarily, when it is determined that the power level of the assembled electronic device is less than a power threshold, the assembled electronic device may further configure the operating parameters of some chip modules included in the above-mentioned chip to avoid configuring excessive power consumption, which may cause the assembled electronic device to shut down, etc., thereby affecting the continuity of the user's use of the assembled electronic device.

[0272] In some embodiments, each chip module included in the chip may correspond to a different priority, and the assembled electronic device may preferentially configure the working parameters of the chip module with a higher priority when the status information does not meet the conditions.

[0273] In some embodiments, the operating parameters of the assembled electronic device configuration may include a chip frequency and a limiting frequency temperature threshold.

[0274] In an embodiment of the present application, the chip may include multiple chip modules, and the assembled electronic device can configure the working parameters of at least one chip module based on the first quantile information of the chip. While achieving flexible configuration of the working parameters, the power consumption performance of the assembled electronic device can be further improved.

[0275] It should be understood that the above embodiments may be coupled to each other, and this application does not limit this. Moreover, the size of the sequence number of each process does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0276] Combined with the above Figures 1 to 12 , describes in detail the device assembly method of the embodiment of the present application, and will be combined with Fig.13 and Fig.14 , describe in detail the device assembly apparatus of an embodiment of the present application.

[0277] Fig.13 A device assembly device 1300 provided in an embodiment of the present application is shown. The device assembly device 1300 includes: an acquisition module 1301 and a processing module 1302. The acquisition module 1301 is used to: acquire first quantile information corresponding to at least one chip, the first quantile information is obtained by testing the chip, and the first quantile information is used to characterize the power consumption performance of the corresponding chip; and acquire second quantile information corresponding to at least one target device, the second quantile information is obtained by testing the target device, and the second quantile information is used to characterize the power consumption performance of the corresponding target device; the processing module 1302 is used to: assemble each of the above chips with at least one target device according to the first quantile information corresponding to each of the above chips and the second quantile information corresponding to each of the above target devices; wherein the overall power consumption performance of the assembled chip and the target device is better than the power consumption performance of the chip before assembly and / or the power consumption performance of the target device before assembly.

[0278] Optionally, the at least one chip includes a first chip; the processing module 1302 is used to: collect current information of the first chip when the first chip is powered on; determine the first quantile of the current information of the first chip, and determine the first quantile information corresponding to the first chip based on the first quantile.

[0279] Optionally, the processing module 1302 is used to: configure the working parameters of the above-mentioned first chip as target working parameters; the above-mentioned target working parameters are the working parameters of the above-mentioned chip in the user usage scenario; when the above-mentioned first chip is powered on, control the above-mentioned first chip to operate based on the above-mentioned target working parameters, and collect the current information of the above-mentioned first chip.

[0280] Optionally, the processing module 1302 is used to: when multiple chips are powered on, collect current information corresponding to the multiple chips respectively; generate a first statistical histogram based on the current information corresponding to the multiple chips respectively; divide the current information in the first statistical histogram equally according to the target number; and determine the first quantile of the current information of the first chip in the first statistical histogram.

[0281] Optionally, the target device includes a display screen, and the processing module 1302 is used to: collect current information of the display screen when the display screen displays a test image; determine the second quantile of the current information of the display screen based on the current information of the display screen, and determine the second quantile information corresponding to the display screen according to the second quantile.

[0282] Optionally, the target device includes a battery, and the processing module 1302 is used to: test the battery to obtain second quantile information corresponding to the battery, including: collecting power consumption information of the battery; determining the third quantile of the power consumption information of the battery based on the power consumption information of the battery, and determining the second quantile information corresponding to the battery based on the third quantile.

[0283] Optionally, in a case where higher quantile information indicates worse power consumption performance, quantile information of at least part of the assembled chip and the target device is less than the preset quantile information.

[0284] Optionally, the processing module 1302 is used to: write the first quantile information corresponding to the at least one chip into the non-volatile memory corresponding to each of the chips, so that when the assembled electronic device is started, it reads the first quantile information from the non-volatile memory corresponding to the chip and configures the working parameters of the chip according to the first quantile information.

[0285] Optionally, the chip includes multiple chip modules, and the processing module 1302 is used to: when the electronic device is started, read the first quantile information from the non-volatile memory corresponding to the chip, and configure working parameters corresponding to at least one of the chip modules according to the first quantile information.

[0286] It should be understood that the device assembly apparatus 1300 here is embodied in the form of a functional module. The term "module" here may refer to an application specific integrated circuit (ASIC), an electronic circuit, a processor (such as a shared processor, a dedicated processor or a group processor, etc.) and a memory for executing one or more software or firmware programs, a merged logic circuit and / or other suitable components that support the described functions. In an optional example, those skilled in the art may understand that the device assembly apparatus 1300 may be specifically an electronic device in the above-mentioned embodiment, or the functions of the electronic device in the above-mentioned embodiment may be integrated in the device assembly apparatus 1300, and the device assembly apparatus 1300 may be used to execute the various processes and / or steps corresponding to the electronic device in the above-mentioned method embodiment. To avoid repetition, they will not be described here. The above-mentioned device assembly apparatus 1300 has the function of implementing the corresponding steps executed by the electronic device in the above-mentioned method; the above-mentioned functions may be implemented by hardware, or may be implemented by hardware executing the corresponding software. The hardware or software includes one or more modules corresponding to the above-mentioned functions. In an embodiment of the present application, Fig.13 The device assembly apparatus 1300 in the embodiment may also be a chip or a chip system, such as a system on chip (SoC).

[0287] Fig.14 An electronic device 1400 provided in an embodiment of the present application is shown. The electronic device 1400 includes: a processor 1401 and a memory 1402, a communication interface 1403 and a bus 1404. The memory 1402 is used to store instructions, and the processor 1401 is used to execute the instructions stored in the memory 1402. The processor 1401, the memory 1402 and the communication interface 1403 are connected to each other through the bus 1404.

[0288] Among them, the processor 1401 is used to: obtain first quantile information corresponding to at least one chip, the first quantile information is obtained by testing the chip, and the first quantile information is used to characterize the power consumption performance of the corresponding chip; obtain second quantile information corresponding to at least one target device, the second quantile information is obtained by testing the target device, and the second quantile information is used to characterize the power consumption performance of the corresponding target device; and, according to the first quantile information corresponding to each of the above chips and the second quantile information corresponding to each of the above target devices, assemble each of the above chips with at least one target device; wherein the overall power consumption performance of the assembled chip and target device is better than the power consumption performance of the chip before assembly and / or the power consumption performance of the target device before assembly.

[0289] It should be understood that the electronic device 1400 can be specifically the electronic device in the above-mentioned embodiment, or the function of the electronic device in the above-mentioned embodiment can be integrated in the electronic device 1400, and the electronic device 1400 can be used to execute the various steps and / or processes corresponding to the electronic device in the above-mentioned method embodiment. Optionally, the memory 1402 may include a read-only memory and a random access memory, and provide instructions and data to the processor 1401. A part of the memory 1402 may also include a non-volatile random access memory. For example, the memory 1402 may also store information about the device type. The processor 1401 can be used to execute the instructions stored in the memory, and when the processor executes the instruction, the processor 1401 can execute the various steps and / or processes corresponding to the electronic device in the above-mentioned method embodiment.

[0290] It should be understood that in the embodiment of the present application, the processor may be a central processing unit (CPU), and the processor may also be other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field programmable gate arrays (FPGA) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components, etc. The general-purpose processor may be a microprocessor or the processor may also be any conventional processor, etc. In the implementation process, each step of the above method may be completed by an integrated logic circuit of hardware in the processor or an instruction in the form of software. The steps of the method disclosed in conjunction with the embodiment of the present application may be directly embodied as being executed by a hardware processor, or may be executed by a combination of hardware and software modules in the processor. The software module may be located in a mature storage medium in the art such as a random access memory, a flash memory, a read-only memory, a programmable read-only memory or an electrically erasable programmable memory, a register, etc. The storage medium is located in a memory, and the processor executes instructions in the memory, and completes the steps of the above method in conjunction with its hardware. To avoid repetition, it is not described in detail here.

[0291] It can be appreciated by a person skilled in the art that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or in combination with computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application. It can be clearly understood by a person skilled in the art that for the convenience and simplicity of description, the specific working process of the system, device and unit described above can refer to the corresponding process in the aforementioned method embodiment, and will not be repeated here. In several embodiments provided in this application, it should be understood that the disclosed system, device and method can be implemented in other ways. For example, the device embodiments described above are only schematic, for example, the division of the unit is only a logical function division, and there may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point, the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms. The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0292] In addition, each functional unit in each embodiment of the present application can be integrated into a processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. If the function is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the prior art or the part of the technical solution can be embodied in the form of a software product, which is stored in a storage medium, including several instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM), random access memory (RAM), disk or optical disk, etc. Various media that can store program codes. The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of changes or replacements within the technical scope disclosed in the present application, which should be covered within the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A device assembly method, characterized in that: include: Acquire first quantile information corresponding to at least one chip, where the first quantile information is obtained by testing the chip, and the first quantile information is used to characterize the power consumption performance of the corresponding chip; Acquire second quantile information corresponding to at least one target device, where the second quantile information is obtained by testing the target device, and the second quantile information is used to characterize the power consumption performance of the corresponding target device; According to the first quantile information corresponding to each of the chips and the second quantile information corresponding to each of the target devices, each of the chips is assembled with at least one target device; wherein the overall power consumption performance of the assembled chips and target devices is better than the power consumption performance of the chips before assembly and / or the power consumption performance of the target devices before assembly.

2. The method according to claim 1, characterized in that The at least one chip includes a first chip; and testing the first chip to obtain first quantile information corresponding to the first chip includes: When the first chip is powered on, collecting current information of the first chip; A first quantile at which the current information of the first chip is located is determined, and first quantile information corresponding to the first chip is determined according to the first quantile.

3. The method according to claim 2, characterized in that When the first chip is powered on, before collecting the current information of the first chip, the method includes: Configuring the operating parameters of the first chip as target operating parameters; the target operating parameters are the operating parameters of the chip in a user usage scenario; The collecting current information of the first chip when the first chip is powered on includes: When the first chip is powered on, the first chip is controlled to operate based on the target operating parameters, and current information of the first chip is collected.

4. The method according to claim 2, characterized in that: Before determining the first quantile of the current information of the first chip, the method further includes: When multiple chips are powered on, collecting current information corresponding to the multiple chips respectively; Generate a first statistical histogram according to the current information respectively corresponding to the plurality of chips; Dividing the current information in the first statistical histogram equally according to the target number; The determining the first quantile of the current information of the first chip includes: Determine a first quantile of the first statistical histogram at which the current information of the first chip is located.

5. The method according to claim 1, characterized in that The target device includes a display screen, and testing the display screen to obtain second quantile information corresponding to the display screen includes: When the display screen displays a test image, collecting current information of the display screen; The second quantile at which the current information of the display screen is located is determined based on the current information of the display screen, and the second quantile information corresponding to the display screen is determined according to the second quantile.

6. The method according to claim 1, characterized in that The target device includes a battery, and testing the battery to obtain second quantile information corresponding to the battery includes: Collecting power consumption information of the battery; The third quantile of the power consumption information of the battery is determined based on the power consumption information of the battery, and the second quantile information corresponding to the battery is determined according to the third quantile.

7. The method according to claim 1, characterized in that In the case where higher quantile information indicates worse power consumption performance, quantile information of at least part of the assembled chip and the target device is less than the preset quantile information.

8. The method according to claim 1, characterized in that After obtaining the first quantile information respectively corresponding to at least one chip, the method further includes: The first quantile information corresponding to the at least one chip is written into the non-volatile memory corresponding to each chip, so that when the assembled electronic device is started, the first quantile information is read from the non-volatile memory corresponding to the chip, and the working parameters of the chip are configured according to the first quantile information.

9. The method according to claim 8, characterized in that The chip includes a plurality of chip modules. When the electronic device is started, the first quantile information is read from a non-volatile memory corresponding to the chip, and the working parameters of the chip are configured according to the first quantile information, including: When the electronic device is started, the first quantile information is read from the non-volatile memory corresponding to the chip, and the working parameters corresponding to at least one of the chip modules are configured according to the first quantile information.

10. A device assembly apparatus, characterized in that: include: An acquisition module, used to acquire first quantile information corresponding to at least one chip, wherein the first quantile information is obtained by testing the chip, and the first quantile information is used to characterize the power consumption performance of the corresponding chip; And, obtaining second quantile information corresponding to at least one target device, wherein the second quantile information is obtained by testing the target device, and the second quantile information is used to characterize the power consumption performance of the corresponding target device; A processing module is used to assemble each of the chips with at least one target device according to the first quantile information corresponding to each of the chips and the second quantile information corresponding to each of the target devices; wherein the overall power consumption performance of the assembled chips and target devices is better than the power consumption performance of the chips before assembly and / or the power consumption performance of the target devices before assembly.

11. An electronic device, characterized in that: The system comprises a processor and a memory, wherein the memory is used to store code instructions; and the processor is used to run the code instructions to execute the method according to any one of claims 1 to 9.

12. A computer program product, comprising computer program code, characterized in that: When the computer program code is executed on a computer, the computer is caused to implement the method according to any one of claims 1 to 9.

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