Device and method for manufacturing chip number in wafer manufacturing process

Abstract

The invention discloses a device and method for manufacturing chip numbers in the wafer manufacturing process, and relates to the technical field of chip numbers.The device comprises photoetching equipment, an original mask and an additional mask, the original mask comprises a component area and a first numbering area, and the additional mask comprises a second numbering area and a third numbering area; the original mask comprises a first serial number area, a first serial number in the first serial number area is used for representing the position of the chip in the primary exposure area, the additional mask comprises a second serial number area, a second serial number in the second serial number area is used for representing the position of the primary exposure area in the wafer, and the photoetching equipment is used for photoetching the wafer based on the original mask and the additional mask. According to the method, the chip number is manufactured for each chip in the wafer, the chip number can be manufactured for each chip in the photoetching step in the wafer manufacturing process, the manufacturing complexity and cost cannot be greatly increased, and the previous process information of each chip can be continuously tracked in the subsequent process.

Description

Technical Field

[0001] The present application relates to the field of chip numbering technology, and in particular to a device and method for making chip numbers during a wafer manufacturing process. Background Art

[0002] Wafers are the basic materials of semiconductor chips. Each wafer usually goes through a series of process steps, such as lithography, doping, metallization, etc., and finally produces hundreds or thousands of chips. The wafer number is a unique identifier for each wafer, usually created and attached to the wafer in the wafer manufacturing plant. The wafer number plays a role in tracking and management throughout the manufacturing process.

[0003] Before the wafer is fully manufactured, all chips are on the same substrate and share process steps. Separately making chip numbers for each chip will greatly increase manufacturing complexity and cost, because additional equipment and processes are required to complete the chip numbering process. After the wafer is fully manufactured, it is cut into individual chips. After cutting, since the chips do not have chip numbers, it is difficult to continue to track the previous process information of each chip in subsequent processes (such as testing and packaging). Summary of the invention

[0004] The purpose of this application is to provide a device and method for generating chip numbers during the wafer manufacturing process, which can generate a unique chip number for each chip during the wafer manufacturing process without greatly increasing the manufacturing complexity and cost, and is conducive to continuing to track the previous process information of each chip in subsequent processes.

[0005] To achieve the above objectives, this application provides the following solutions:

[0006] In a first aspect, the present application provides a device for making chip numbers in a wafer manufacturing process, wherein the device for making chip numbers in a wafer manufacturing process comprises: a photolithography device, an original mask, and an additional mask;

[0007] The original mask is used to expose a single exposure area of ​​the wafer during a single exposure, and the single exposure area is a partial area of ​​the wafer; the original mask is divided into A areas, each of which corresponds to a chip in the single exposure area; each of the areas includes a component area and a first numbered area, the content and position of the component areas in different areas are the same, and the content of the first numbered areas in different areas is different; the content of the component area is a component pattern; the content of the first numbered area is a first number, and the first number is used to characterize the position of the chip in the single exposure area; wherein A is a positive integer greater than 0;

[0008] The additional mask includes a second numbering area, the content of the second numbering area is a second number, and the second number is used to characterize the position of the single exposure area in the wafer;

[0009] The photolithography equipment is used to perform photolithography on the wafer based on the original mask and the additional mask, and to generate a chip number for each chip in the wafer.

[0010] In a second aspect, the present application provides a method for making chip numbers during wafer manufacturing, based on the above-mentioned device for making chip numbers during wafer manufacturing, the method for making chip numbers during wafer manufacturing specifically includes:

[0011] Control the photolithography equipment to sequentially coat the wafer with glue, align exposure, develop, etch and remove photoresist, and create chip numbers for each chip in the wafer;

[0012] Among them, the alignment exposure includes:

[0013] Selecting a one-time exposure area of ​​the wafer as the area to be exposed; the wafer includes a plurality of one-time exposure areas;

[0014] Controlling the original mask to be aligned with the area to be exposed, and exposing the area to be exposed, so that each chip in the area to be exposed has a photoresist pattern including a component pattern and a first number;

[0015] Determine whether all the first exposure areas on the wafer have been exposed, and obtain a first determination result;

[0016] If the first judgment result is no, then selecting an unexposed once-exposure area of ​​the wafer as the area to be exposed, and returning to the step of “controlling the alignment of the original mask with the area to be exposed”;

[0017] If the first judgment result is yes, then selecting a chip as a chip to be exposed;

[0018] Controlling the additional mask to be aligned with the chip to be exposed, and exposing the chip to be exposed, so that the chip to be exposed has a photoresist pattern including a component pattern, a first number and a second number;

[0019] Determine whether all chips in the wafer have been exposed to obtain a second determination result;

[0020] If the second judgment result is no, an unexposed chip of the wafer is selected as the chip to be exposed, and the process returns to the step of "controlling the alignment of the additional mask and the chip to be exposed".

[0021] In a third aspect, the present application provides a method for making chip numbers during wafer manufacturing, based on the above-mentioned device for making chip numbers during wafer manufacturing, the method for making chip numbers during wafer manufacturing specifically includes:

[0022] Control the photolithography equipment to sequentially coat the wafer with glue, align exposure, develop, etch and remove photoresist, and create chip numbers for each chip in the wafer;

[0023] Among them, the alignment exposure includes:

[0024] Select a chip in the wafer as the chip to be exposed;

[0025] Controlling the additional mask to align with the chip to be exposed, and exposing the chip to be exposed so that the chip to be exposed has a photoresist pattern containing a second number;

[0026] Determine whether all chips in the wafer have been exposed to obtain a third determination result;

[0027] If the third judgment result is no, then an unexposed chip of the wafer is selected as the chip to be exposed, and the process returns to the step of “controlling the additional mask to be aligned with the chip to be exposed”;

[0028] If the third judgment result is yes, then selecting a one-time exposure area of ​​the wafer as the area to be exposed; the wafer includes multiple one-time exposure areas;

[0029] Controlling the original mask to align with the area to be exposed, and exposing the area to be exposed, so that each chip in the area to be exposed has a photoresist pattern including a component pattern, a first number and a second number;

[0030] Determine whether all the first exposure areas on the wafer have been exposed to obtain a fourth determination result;

[0031] If the fourth judgment result is no, then an unexposed once-exposure area of ​​the wafer is selected as the area to be exposed, and the process returns to the step of "controlling the alignment of the original mask with the area to be exposed".

[0032] According to the specific embodiments provided in this application, this application discloses the following technical effects:

[0033] The present application provides a device and method for making chip numbers in a wafer manufacturing process, the device comprising: a photolithography device, an original mask and an additional mask, the original mask comprising a component area and a first numbering area, the first number in the first numbering area is used to characterize the position of the chip in a single exposure area, the additional mask comprising a second numbering area, the second number in the second numbering area is used to characterize the position of the single exposure area in the wafer, the photolithography device is used to perform photolithography on the wafer based on the original mask and the additional mask, and make a chip number for each chip in the wafer. The present application introduces the first numbering area into the original mask, and additionally makes an additional mask including the second numbering area, so that the chip number can be made for each chip in the photolithography step of the wafer manufacturing process, and no additional equipment and additional processes are required to make a chip number for each chip, which will not greatly increase the manufacturing complexity and cost. Since each chip has a unique chip number, it is conducive to continue to track the previous process information of each chip in the subsequent process. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0035] Figure 1 A schematic diagram of the positions of the wafer, primary exposure area and chip provided in Example 1 of the present application.

[0036] Figure 2 A schematic diagram of the numbering of the positions of the single exposure areas in the wafer provided in Example 1 of the present application.

[0037] Figure 3 A schematic diagram of the numbering of the position of the chip in a single exposure area provided in Example 1 of the present application.

[0038] Figure 4 A schematic diagram of the complete chip numbering provided in Example 1 of the present application.

[0039] Figure 5 A schematic diagram of a traditional chip logo.

[0040] Figure 6 Schematic diagram of traditional wafer numbering.

[0041] Figure 7 A schematic diagram of the placement of chip numbers provided in Example 1 of the present application.

[0042] Figure 8Schematic diagram of the binary square pattern marking of the chip number in shot82 provided in Example 1 of the present application.

[0043] Fig. 9 Schematic diagram of the binary square pattern marking of the chip number in shot94 provided in Example 1 of the present application.

[0044] Fig.10 A schematic diagram of the placement of the binary square pattern mark provided in Example 1 of the present application.

[0045] Fig.11 A schematic diagram of the original mask provided in Example 1 of the present application.

[0046] Fig.12 A schematic structural diagram of the additional mask provided in Example 1 of the present application.

[0047] Fig.13 Another structural schematic diagram of the additional mask provided in Example 1 of the present application.

[0048] Fig.14 A schematic diagram of the chip numbering area after the first alignment exposure using the original mask provided in Example 1 of the present application.

[0049] Fig.15 A schematic diagram of the result of the first alignment exposure using the original mask provided in Example 1 of the present application; wherein: Fig.15 (a) is a schematic diagram of the chip numbering area; Fig.15 (b) in Fig.15 Schematic diagram of the cross section at the dotted line position in (a).

[0050] Fig.16 A schematic diagram of the chip numbering area after the second alignment exposure using an additional mask provided in Example 1 of the present application.

[0051] Fig.17 A schematic diagram of the result of a second alignment exposure using an additional mask provided in Example 1 of the present application; wherein: Fig.17 (a) is a schematic diagram of the chip numbering area; Fig.17 (b) in Fig.17 Schematic diagram of the cross section at the dotted line position in (a).

[0052] Fig.18 This is a schematic diagram of the development result provided in Example 1 of the present application.

[0053] Fig.19 This is a schematic diagram of the etching results provided in Example 1 of the present application.

[0054] Fig. 20This is a schematic diagram of the result after removing the photoresist provided in Example 1 of the present application.

[0055] Fig.21 A schematic diagram of the result of the first alignment exposure using an additional mask provided in Example 1 of the present application; wherein: Fig.21 (a) is a schematic diagram of the chip numbering area; Fig.21 (b) in Fig.21 Schematic diagram of the cross section at the dotted line position in (a).

[0056] Fig. 22 A schematic diagram of the result of a second alignment exposure using the original mask provided in Example 1 of the present application; wherein: Fig. 22 (a) is a schematic diagram of the chip numbering area; Fig. 22 (b) in Fig. 22 Schematic diagram of the cross section at the dotted line position in (a).

[0057] Fig.23 A schematic diagram of the placement of wafer numbers provided in Example 1 of the present application. DETAILED DESCRIPTION

[0058] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0059] Example 1

[0060] In the wafer manufacturing process, the photolithography step is a key step to transfer the circuit pattern from the mask to the wafer surface. In the photolithography step, using a step-and-scan lithography machine for alignment exposure is a standard practice in modern semiconductor manufacturing. The step-and-scan lithography machine repeatedly prints the circuit pattern on the mask on the wafer surface by moving step by step. This method has the advantages of high resolution and precise alignment. Because it moves step by step, the same mask is reused for each exposure, and the mask only covers a small area of ​​the wafer (called the single exposure area), so it is difficult to make individual numbers for each chip during the manufacturing process.

[0061] In order to solve the above problem, this embodiment improves the mask used in the photolithography step to realize the function of individually numbering each chip during the manufacturing process. Specifically, this embodiment provides a device for making chip numbers during wafer manufacturing, and the device for making chip numbers during wafer manufacturing includes: photolithography equipment, an original mask, and an additional mask.

[0062] The original mask is used to expose a single exposure area of ​​the wafer during a single exposure. The single exposure area is a partial area of ​​the wafer. The original mask is divided into A areas, each area corresponds to a chip in the single exposure area, and each area includes a component area and a first number area. The content and position of the component areas in different areas are the same, and the content of the first number areas in different areas is different. The content of the component area is the component pattern, and the content of the first number area is the first number. The first number is used to characterize the position of the chip in the single exposure area; wherein A is a positive integer greater than 0.

[0063] The additional mask includes a second numbered area, the content of the second numbered area is a second number, and the second number is used to characterize the position of the single exposure area in the wafer.

[0064] The photolithography equipment is used to perform photolithography on the wafer based on the original mask and the additional mask to produce a chip number for each chip in the wafer.

[0065] In this embodiment, the lithography equipment includes machines for completing each process in the lithography steps, mainly including a coating machine for completing coating, a step-and-scan lithography machine for completing alignment exposure, a developing machine for completing development, an etching machine for completing etching, and a photoresist removal machine for completing photoresist removal, etc.

[0066] This embodiment first defines a method for naming and identifying chips on a wafer, that is, first describes a specific method for determining chip numbers:

[0067] The step-and-scan lithography machine moves step by step, and each exposure only covers a small area of ​​the wafer, which is called a single exposure shot. Figure 1 As shown, when the mask pattern is completely exposed on the wafer at one time, the corresponding area on the wafer is called a one-shot area (One shot), and the wafer includes multiple one-shot areas. When the area of ​​the chip is smaller than the area of ​​the one-shot area, the one-shot area can include multiple chips. This embodiment takes the one-shot area including 9 chips as an example to introduce the method of determining the chip number. Of course, in actual applications, the one-shot area can also include other numbers of chips as needed.

[0068] At this time, if one wants to achieve the purpose of defining the accurate position of the chip in the wafer, the position of the chip in the single exposure area and the position of the single exposure area in the wafer must be numbered respectively.

[0069] like Figure 2As shown, when the position of the single exposure area in the wafer is numbered, the shot column ID and shot row ID are defined, and the digital numbering is adopted. The shot column ID indicates the column number of the single exposure area in the wafer, and the shot row ID indicates the row number of the single exposure area in the wafer. For example, shot 82 indicates that the single exposure area is located at the 8th column and the 2nd row in the wafer, and shot 94 indicates that the single exposure area is located at the 9th column and the 4th row in the wafer. Based on the shot column ID and the shot row ID, the specific position of each single exposure area in the wafer can be clearly determined.

[0070] like Figure 3 As shown, when numbering the position of the chip in the primary exposure area, the chip column ID and chip row ID are defined, and the digital numbering is adopted. The chip column ID indicates the column number of the chip in the primary exposure area, and the chip row ID indicates the row number of the chip in the primary exposure area. For example, chip 21 indicates the chip in the 2nd column and the 1st row in the primary exposure area, and chip 32 indicates the chip in the 3rd column and the 2nd row in the primary exposure area. Based on the chip column ID and the chip row ID, the specific position of each chip in the primary exposure area can be clearly determined.

[0071] like Figure 4 As shown, by using the complete numbers defined by the two methods mentioned above, the specific position of each chip in the wafer can be clearly determined. For example, the chip number is 8231, which means that the chip is located in the 3rd column and the 1st row of the single exposure area of ​​the 8th column and the 2nd row in the wafer.

[0072] The chip number of this embodiment is not used to make Figure 5 The chip logo is located at Figure 5 In the dotted box, the chip IDs of all chips are the same, but the chip numbers of all chips are different. Figure 6 The wafer number shown is used to number the wafers, not to number the chips in the wafer.

[0073] After determining the chip number, this embodiment takes the binary mark for machine reading as an example, and describes the shot column ID, shot row ID, chip column ID and chip row ID in a binary manner of "appearance" or "absence" of a square. The actual width of the square can range from a few microns to hundreds of microns, as long as it can achieve the purpose of machine reading.

[0074] In this embodiment, the precise position of each chip in the wafer is numbered by a combination of shot column ID, shot row ID, chip column ID and chip row ID. The numbering can be implemented as a binary mark, using the "appearance" or "absence" of a square to describe the digital number.

[0075] like Figure 7 As shown, based on the definition of chip numbering, in order to display the complete chip number of the chip, four rows are required to place binary marks. Specifically, the first two rows are used to define the position of the one-shot area in the wafer, including the shot column ID and shot row ID, and the last two rows are used to define the chip position in the one-shot area, including the chip column ID and chip row ID. Figure 7 In the example, four square spaces are reserved for each row. However, in actual applications, the number of square spaces reserved for each row depends on how large the number is. For example, if the number is only up to 8, 4 bits can be used, and 4 bits can represent up to 16 numbers.

[0076] like Figure 8 As shown, when the chip numbers in shot82 are 8211, 8212, 8213, 8221, 8222, 8223, 8231, 8232, 8233, the binary square pattern mark produced is specifically in the order from right to left, and the nth position represents 2 n-1 , if a square appears at that position, it means taking the value of that position, for example, Figure 8 The first row of the first black box in the binary square pattern mark in , at this time, a square appears in the 4th position, and no square appears in other positions, so the first row represents 8, such as Fig. 9 As shown, when the chip numbers in shot 94 are 9411, 9412, 9413, 9421, 9422, 9423, 9431, 9432, and 9433 respectively, the binary square pattern mark produced can be found that the areas where the chip column ID and the chip row ID are located are repeated between different shots and can be placed in the original mask. Therefore, in this embodiment, the chip column ID and the chip row ID are designed in the original mask that exists at the same time as the normal component pattern, and the shot column ID and the shot row ID are set in the additional mask. The additional mask only needs to contain simple squares, and the binary mark is formed based on the different position compositions of the squares.

[0077] The chip number does not actually occupy the entire chip, but the size and placement of the chip number are determined without affecting the main components and without increasing the chip area. Fig.10 As shown. Fig.11 As shown, it is a schematic diagram of the original mask.

[0078] In this embodiment, Figure 7 As shown, the first numbered area includes: multiple straight lines and multiple graphics. The multiple straight lines are distributed in a rectangular array, forming B rows and C columns, where B and C are both constants. Figure 7 In , B and C are both 4. The direction from the last row to the first row is defined as upward, each of the multiple graphics is located above a straight line, and different graphics are located above different straight lines. The position of the graphics is used to characterize the position of the chip in a single exposure area.

[0079] In this embodiment, B is 4, and the graphics in the graphic area on each row respectively represent the number of rows of the chip in the single exposure area, the number of columns of the chip in the single exposure area, the number of rows of the single exposure area in the wafer, and the number of columns of the single exposure area in the wafer. The graphics in the first numbered area are located in the graphic area on the row representing the number of rows of the chip in the single exposure area and in the graphic area on the row representing the number of columns of the chip in the single exposure area.

[0080] In this embodiment, Fig.12 As shown, the second numbered area includes multiple rows of first patterns, each row of first patterns has a number of graphics located in different columns, the number of columns of the graphics is the same as the number of columns of the straight lines, and one row of first patterns is used to represent the number of rows of a single exposure area in the wafer or the number of columns of a single exposure area in the wafer, and two rows of first patterns are used to represent the position of a single exposure area in the wafer.

[0081] Or, if Fig.13 As shown, the second numbered area includes a plurality of second patterns, Fig.13 The rectangular frame in the figure is a second pattern, each second pattern has two rows of third patterns, each row of the third pattern has a number of graphics located in different columns, the number of columns of the graphics is the same as the number of columns of the straight lines, and each second pattern is used to characterize the position of a single exposure area in the wafer.

[0082] As an optional embodiment, C is 4, and the graphics in the graphic area on each column respectively represent the number of rows of the chip in the single exposure area, the number of columns of the chip in the single exposure area, the number of rows of the single exposure area in the wafer, and the number of columns of the single exposure area in the wafer. The graphics in the first numbered area are located in the graphic area on the column representing the number of rows of the chip in the single exposure area and in the graphic area on the column representing the number of columns of the chip in the single exposure area.

[0083] The second numbering area includes multiple columns of first patterns, each column of first patterns has several figures located in different rows, the number of rows of the figures is the same as the number of rows of the straight lines, one column of first patterns is used to represent the number of rows of a single exposure area in the wafer or the number of columns of a single exposure area in the wafer, and two columns of first patterns are used to represent the position of a single exposure area in the wafer.

[0084] Alternatively, the second numbered area includes multiple second patterns, each second pattern has two columns of third patterns, each column of third patterns has several graphics located in different rows, the number of rows of the graphics is the same as the number of rows of straight lines, and each second pattern is used to characterize the position of a single exposure area in the wafer.

[0085] The graphics may be in any shape, such as a square, rectangle, circle, rhombus, etc. The drawings provided in this embodiment all adopt a square shape.

[0086] The first alignment exposure uses the original mask for normal exposure to form a photoresist pattern containing the chip column ID and chip row ID on the wafer surface. The second alignment exposure uses an additional mask and uses a photolithography machine shield to control the area where light passes through the additional mask, thereby achieving selective exposure of the required shot column ID and shot row ID, and forming a photoresist pattern containing the shot column ID and shot row ID on the wafer surface. During the exposure process, the shield is used to control the passage of light to achieve selective exposure of specific areas of the additional mask. The shield can also accurately control the area where light passes to ensure that an accurate numbering pattern is formed on the wafer.

[0087] In the exposure process of the stepper and scanner lithography machine, the shutter (also called the diaphragm) is a key component, and its main function is to control the passage of light, so as to achieve selective exposure of specific areas of the mask. The main function of the shutter is selective exposure, because the shutter can accurately control the passage area of ​​light, so that only specific areas of the mask are exposed, which is an important means to achieve complex graphics and precision circuits. The working principle of the shutter is that the shutter is located between the light source and the mask, and can be adjusted at the micron or even nanometer level through a precise mechanical control system. It can quickly move or adjust the open and closed state to control the shape and size of the light beam. The shutter can have many forms, such as deformable diaphragms, rotating shutters, rectangular shutters, etc. The specific form depends on the design and application requirements of the lithography system.

[0088] The shutter can be controlled by programming, and the shape and position of the shutter can be changed quickly and accurately according to the preset program, achieving higher flexibility and faster exposure speed. The shutter in a modern step-and-scan lithography machine can be moved and adjusted in a very short time, and the specific speed depends on the design and technical level of the equipment. The shutter system in a modern high-end step-and-scan lithography machine usually has a millisecond response time, which means that the shutter can complete the position adjustment or the change of the open and closed state within a few milliseconds, for example, the response time is between 1-10 milliseconds. Therefore, this embodiment is practical and feasible, and will not significantly increase the time and cost of the process.

[0089] The control accuracy of the shutter in modern step-and-scan lithography machines can usually reach sub-micron or even nanometer levels, and even the control accuracy of the shutter in traditional lithography equipment is generally between 1 micron and several microns. For some applications with lower precision requirements, this accuracy is sufficient. Therefore, the actual size of the chip number is no longer limited by the process capability, but may be limited by the recognition capability of the machine that reads the chip number.

[0090] In this embodiment, the process steps are described as follows:

[0091] (1) First alignment exposure:

[0092] During the exposure process, the original mask is used to transfer the chip column ID and chip row ID patterns to the photoresist on the wafer surface. For example, define the chip column ID as 3 and the chip row ID as 1. At this time, the binary square pattern marks the exposure area as follows Fig.14 As shown in the white area of ​​, the result of the first alignment exposure is Fig.15 shown.

[0093] (2) Second alignment exposure:

[0094] During the exposure process, an additional mask is used, and the required shot column ID and shot row ID pattern is selected using the mask to transfer the pattern to the photoresist on the wafer surface. For example, if the shot column ID is defined as 8 and the shot row ID is defined as 2, then the binary square pattern marks the exposure area as follows Fig.16 As shown in the white area of ​​, the result of the second alignment exposure is Fig.17 shown.

[0095] In this way, the exposure of the binary square pattern mark of chip number 8231 is completed.

[0096] (3) Development:

[0097] The results of the development are as follows Fig.18 As shown, it is still Fig.17 Schematic diagram of the cross section at the dotted line position.

[0098] (4) Etching:

[0099] Using photoresist as a mask, etching forms the final pattern. The etching result is as follows: Fig.19 As shown, it is still Fig.17 Schematic diagram of the cross section at the dotted line position.

[0100] (5) Photoresist removal:

[0101] The results of photoresist removal are as follows Fig. 20 As shown, it is still Fig.17 Schematic diagram of the cross section at the dotted line position.

[0102] Through the above process steps, the photolithography process can be completed.

[0103] For example, a wafer includes 52 single-exposure areas, and one single-exposure area includes 9 chips. Fig.12 For the additional mask shown, in the first alignment exposure, all chip column IDs and chip row IDs are exposed 52 times. In the second alignment exposure, the shot column ID is exposed 52*9 times, and the shot row ID is exposed 52*9 times. The exposure time of each step-and-scan lithography machine is usually between 0.1 and 1 second, which depends on the specific parameters of the lithography process, such as the light source used, the sensitivity of the photosensitive material, and the resolution to be achieved. The specific exposure time may vary depending on the equipment model and manufacturing process. Newer step-and-scan lithography machines usually optimize the exposure time to improve production efficiency and graphic accuracy. Taking an exposure time of 0.1s as an example, the exposure time of the second alignment exposure is 0.1s*52*9*2=93.6s. When using Fig.13 When the additional mask is shown, the first alignment exposure, all chip column IDs and chip row IDs are exposed 52 times, the second alignment exposure, shot column ID and shot row ID are exposed 52*9 times, and the exposure time of the second alignment exposure is 0.1 seconds*52*9=46.8 seconds. Obviously, the chip numbering method of this embodiment only introduces an additional time of less than 100 seconds, and does not require additional equipment and processes, and will not greatly increase the manufacturing complexity and cost.

[0104] In this embodiment, the original mask is used for the first alignment exposure to form the chip column ID and chip row ID on the chip, and the additional mask is used for the second alignment exposure. The required shot column ID and shot row ID are selected in combination with the mask, and the shot column ID and shot row ID are formed on the chip by controlling the selective exposure of light to achieve complete chip numbering. In this embodiment, the additional mask is used for the first alignment exposure, and the original mask is used for the second alignment exposure. The original mask contains the main components, and there is a controlled time from exposure to development. This method can increase the process window. At this time, the process flow steps are as follows:

[0105] (1) First alignment exposure:

[0106] The additional mask is used during the exposure process. The result of the first alignment exposure is as follows: Fig.21 shown.

[0107] (2) Second alignment exposure:

[0108] The original mask is used during the exposure process, and the result of the second alignment exposure is as follows: Fig. 22 shown.

[0109] (3) Development:

[0110] The development results are as follows Fig.18 shown.

[0111] (4) Etching:

[0112] Using photoresist as a mask, etching forms the final pattern. The etching result is as follows: Fig.19 shown.

[0113] (5) Photoresist removal

[0114] The photoresist removal results are as follows Fig. 20 shown.

[0115] This embodiment forms a unique chip number on the surface of the wafer through the combination of two exposure steps (original mask and additional mask), and then goes through the steps of development, baking, etching and photoresist removal to ensure the final formation of the chip number pattern. The chip number can be read by a machine to ensure that the specific information of each chip can be tracked in the subsequent process. This embodiment realizes the independent numbering of each chip without significantly increasing the process time and cost, and effectively solves the chip tracking problem in the prior art.

[0116] Among them, the materials used in the alignment exposure include the original mask and the additional mask for pattern transfer, and the process conditions are as follows: the light source can use an ultraviolet light source (usually with a wavelength of 365nm or 248nm), an extreme ultraviolet light source (EUV, usually with a wavelength of 13.5nm), an i-line light source (using light emitted by a mercury lamp with a wavelength of 365nm) and a g-line light source (using light emitted by a mercury lamp, but with a wavelength of 436nm). In contrast, ultraviolet light sources and extreme ultraviolet light sources provide higher resolution, making it possible to produce finer micro-patterns. The exposure time can be determined according to the light source power, the type of photoresist, and the complexity of the pattern, and is usually between a few seconds and tens of seconds. In this process, the wafer and the mask are precisely aligned by an alignment device.

[0117] The materials used in the development include a developer, and an alkaline developer such as tetramethylammonium hydroxide is commonly used. The process conditions are as follows: the development time can be between 30 seconds and 2 minutes, depending on the type and thickness of the photoresist. The development temperature is usually room temperature (20-25°C). The development process is that the developer dissolves the exposed photoresist (if the photoresist is a positive photoresist, the positive photoresist is dissolved after exposure) or the unexposed photoresist (if the photoresist is a negative photoresist, the negative photoresist is hardened after exposure).

[0118] Etching is divided into dry etching and wet etching. In dry etching, the material used for etching is plasma gas, such as CF 4, SF 6 , Cl 2 The process conditions are as follows: the material is etched by generating reactive ions through plasma, the etching rate and selectivity are controlled by parameters such as gas type, power, pressure, etc., the temperature is room temperature or low temperature (close to minus dozens of degrees in some cases), and the time is from a few seconds to a few minutes, depending on the thickness of the material and the etching rate. When wet etching is used, the materials required for etching are acidic or alkaline chemicals, such as HCl, H 2 、SO 4 , HF, etc. The process conditions are as follows: use liquid chemicals to dissolve the material, the temperature is from room temperature to 70°C, and the time is from a few seconds to a few minutes.

[0119] Photoresist removal can be done by dry stripping or wet stripping. When dry stripping is used, the material used is oxygen plasma, such as O 2 The process conditions are as follows: the photoresist is decomposed by oxygen plasma, the temperature is usually room temperature or lower, and the time is from tens of seconds to several minutes. When wet stripping is adopted, the materials used are solvents (such as NMP, acetone, isopropanol, etc.) or acidic chemicals, and the process conditions are as follows: the solvent or chemical dissolves the photoresist, the temperature is usually between room temperature and 60°C, and the time is from several minutes to tens of minutes.

[0120] The specific process conditions of each step will vary depending on the process node, material properties and equipment conditions of semiconductor manufacturing.

[0121] The photolithography step of this embodiment may also include baking, which is divided into pre-bake (Prebake) performed before alignment exposure, post-exposure bake (Post Exposure Bake, PEB) performed after alignment exposure, and post-bake (Postbake) performed after development, so that the photoresist maintains its stability during the baking process and avoids the occurrence of bubbles or cracks.

[0122] The process conditions are as follows:

[0123] Pre-baking: Remove the solvent in the photoresist, the temperature is usually 90℃-100℃, and the time is 1 to 2 minutes.

[0124] Post-exposure baking: Stabilize the photoresist after exposure, the temperature is usually between 110℃-130℃, and the time is 1 to 2 minutes.

[0125] Post-baking: Improve the hardness of the photoresist to increase corrosion resistance. The temperature is usually between 100℃ and 120℃ for 1 to 2 minutes.

[0126] This embodiment has the following advantages:

[0127] (1) Realize independent chip numbering:

[0128] During the wafer manufacturing process, each chip is individually numbered through photolithography technology. This ensures the traceability of each chip throughout the entire manufacturing and subsequent process flows without increasing manufacturing complexity and cost.

[0129] (2) Improve tracking management during the manufacturing process:

[0130] By directly forming numbers on the wafer during the photolithography process, the problem of number loss after chip cutting in the prior art is solved, thereby maintaining the identifiability and traceability of each chip in subsequent processes.

[0131] (3) Simplify the manufacturing process:

[0132] By adding an extra exposure to the existing photolithography step, the additional cost and complexity of traditional laser etching and electronic tracking systems are avoided, and production efficiency is improved.

[0133] (4) Improve data security and management efficiency:

[0134] The use of physical numbering reduces reliance on complex electronic tracking systems, reduces data security risks, and simplifies system complexity and maintenance costs.

[0135] (5) Support large-scale production:

[0136] Through efficient and precise lithography numbering methods, it supports large-scale chip production while maintaining the uniqueness and traceability of each chip, adapting to the high-capacity requirements of modern semiconductor manufacturing.

[0137] In summary, in the semiconductor wafer manufacturing process, this embodiment uses the current photolithography technology to achieve independent numbering of each chip, improves the tracking management efficiency and data security in the chip production process, simplifies the process and reduces costs, and supports large-scale and efficient chip production.

[0138] This embodiment can adopt the same principle. In addition to the chip number, the wafer number to which the chip belongs can also be made into each chip, such as Fig.23 As shown, ensuring tracking management throughout the entire manufacturing process.

[0139] In this embodiment, the chip number can be a combination of numbers, or the position and appearance of a graphic, as long as the required number (or graphic) can be selected by the mask using a mask, exposed and formed on the wafer, and can be identified, for example, by machine reading.

[0140] There is no practice of individually numbering each chip during the wafer manufacturing process. The current methods of tracking chips and their respective shortcomings are as follows:

[0141] (1) Introducing chip-level marking after cutting: Marking a unique number on each chip through laser etching and other technologies. Disadvantages are: 1) Increased cost: Laser etching and other marking technologies require additional equipment and consumables, increasing manufacturing costs. 2) Reduced production efficiency: The marking process may reduce production speed and affect overall production capacity.

[0142] (2) Electronic tracking system: The electronic tracking system is used to record the process and test data of each chip. The disadvantages are: 1) System complexity: Establishing and maintaining a comprehensive electronic tracking system requires complex software and hardware support, which increases the complexity of the system. 2) Data security: The electronic tracking system needs to protect a large amount of production and test data, facing data leakage and security risks. 3) Dependency: Any failure or data loss in the system may cause production line interruption or affect the tracking accuracy of the chip.

[0143] (3) Big data analysis and management: Through big data analysis, management and optimization of all production and test data from wafers to individual chips. Disadvantages are: 1) High data processing requirements: Big data analysis requires powerful computing power and storage resources, and the requirements for processing and managing large amounts of data are high. 2) Analysis complexity: Effective analysis and management of data requires professional knowledge and complex algorithms, which increases management and technical challenges. 3) Insufficient real-time performance: In some cases, the ability to process and analyze data in real time may be insufficient, affecting the timeliness of production decisions.

[0144] In summary, chip numbering is required to facilitate tracking after chip cutting, but there is currently no practice to implement independent numbering during the manufacturing process.

[0145] The beneficial effects achieved by this embodiment are as follows:

[0146] (1) Accurate tracking:

[0147] During the manufacturing process, each chip is independently numbered to ensure that the specific information of each chip can be accurately tracked in subsequent processes.

[0148] (2) Process Integration:

[0149] The numbering process is integrated into the original lithography step, and only one additional exposure step is required, which will not significantly increase the manufacturing complexity and cost. And the additional mask can be shared by different products.

[0150] (3) Cost-effectiveness:

[0151] Compared with subsequent marking technologies such as laser etching, this method completes chip numbering during the manufacturing process, does not require additional equipment and consumables, and reduces manufacturing costs.

[0152] (4)Production efficiency:

[0153] It does not affect the overall production speed and avoids the problem of reduced production efficiency caused by traditional marking methods.

[0154] (5) System simplification:

[0155] There is no need to build and maintain complex software and hardware systems, reducing system complexity and maintenance costs.

[0156] (6) Data security:

[0157] Physical numbering reduces reliance on complex electronic tracking systems, reducing data leakage and security risks.

[0158] (7) Real-time:

[0159] By directly forming numbers on the wafer through photolithography, the problem of insufficient real-time performance that may be encountered in the process of big data analysis is avoided.

[0160] (8) Application flexibility:

[0161] The same numbering concept can be applied to other markings, such as wafer numbers, etc., enhancing flexibility and adaptability in the manufacturing process.

[0162] (9) High precision and reliability:

[0163] High-precision photolithography is achieved using a stepper mask to ensure the accuracy and reliability of the numbered pattern.

[0164] Through these advantages, this embodiment improves the management and tracking efficiency in the chip manufacturing process without increasing significant costs.

[0165] This embodiment can solve the problem that after wafer manufacturing is completed and the wafer is divided into individual chips by cutting, it is difficult to continue to track the specific information of each chip in the subsequent process. This embodiment can be completed in the original normal process steps, and only needs to add an additional exposure step. It will not have the shortcomings caused by other current practices, such as too much cost increase, too complicated system, insufficient data security, high data processing requirements, analysis complexity, lack of real-time performance, etc.

[0166] Example 2

[0167] This embodiment provides a method for making chip numbers during wafer manufacturing, which is based on the device for making chip numbers during wafer manufacturing described in Embodiment 1. The method for making chip numbers during wafer manufacturing specifically includes:

[0168] Control the photolithography equipment to sequentially coat the wafer with glue, align exposure, develop, etch and remove photoresist, and create chip numbers for each chip in the wafer;

[0169] Among them, the alignment exposure includes:

[0170] (1) A one-time exposure area of ​​a wafer is selected as the area to be exposed, and the wafer includes multiple one-time exposure areas.

[0171] (2) Controlling the original mask to be aligned with the area to be exposed, and exposing the area to be exposed, so that each chip in the area to be exposed has a photoresist pattern including a component pattern and a first number.

[0172] (3) Determine whether all the first exposure areas in the wafer have been exposed, and obtain a first determination result.

[0173] (4) If the first judgment result is no, then an unexposed once-exposure area of ​​the wafer is selected as the area to be exposed, and the process returns to the step of "controlling the alignment of the original mask and the area to be exposed".

[0174] (5) If the first judgment result is yes, a chip is selected as the chip to be exposed.

[0175] (6) Controlling the additional mask to be aligned with the chip to be exposed, and exposing the chip to be exposed, so that the chip to be exposed has a photoresist pattern including a component pattern, a first number, and a second number.

[0176] (7) Determine whether all chips in the wafer have been exposed to obtain a second determination result.

[0177] (8) If the second judgment result is no, an unexposed chip of the wafer is selected as the chip to be exposed, and the process returns to the step of "controlling the alignment of the additional mask and the chip to be exposed".

[0178] Among them, controlling the additional mask to be aligned with the chip to be exposed, and exposing the chip to be exposed so that the chip to be exposed has a photoresist pattern including a component pattern, a first number and a second number, specifically includes:

[0179] The additional mask is controlled to be aligned with the chip to be exposed for the first time, so that the first pattern of the first target row in the additional mask is aligned with the graphic area on the first target row in the chip to be exposed, and other parts of the additional mask except the first pattern of the first target row are blocked, and the chip to be exposed is exposed so that the chip to be exposed has a photoresist pattern including a component pattern, a first number and a third number, and the first pattern of the first target row, the pattern in the graphic area on the first target row and the third number are all used to characterize the number of rows of the exposure area in the wafer.

[0180] The additional mask is controlled to be aligned with the chip to be exposed for the second time, so that the first pattern of the second target row in the additional mask is aligned with the graphic area on the second target row in the chip to be exposed, and other parts of the additional mask except the first pattern of the second target row are blocked, and the chip to be exposed is exposed so that the chip to be exposed has a photoresist pattern including a component pattern, a first number, a third number and a fourth number, the first pattern of the second target row, the graphic in the graphic area on the second target row and the fourth number are all used to characterize the number of columns of the single exposure area in the wafer, and the third number and the fourth number constitute the second number.

[0181] Among them, controlling the additional mask to be aligned with the chip to be exposed, and exposing the chip to be exposed so that the chip to be exposed has a photoresist pattern including a component pattern, a first number and a second number, specifically includes:

[0182] Control the additional mask to be aligned with the chip to be exposed, so that a row of the third pattern in the second pattern of the target block in the additional mask is aligned with the graphic area on the third target row in the chip to be exposed, and another row of the third pattern in the second pattern of the target block in the additional mask is aligned with the graphic area on the fourth target row in the chip to be exposed, and cover other parts of the additional mask except the second pattern of the target block, and expose the chip to be exposed so that the chip to be exposed has a photoresist pattern including a component pattern, a first number and a second number, a row of the third pattern in the second pattern of the target block and a graphic area on the third target row are both used to represent the number of rows of the single exposure area in the wafer, and another row of the third pattern in the second pattern of the target block and a graphic area on the fourth target row are both used to represent the number of columns of the single exposure area in the wafer.

[0183] Example 3

[0184] This embodiment provides a method for making chip numbers during wafer manufacturing, which is based on the device for making chip numbers during wafer manufacturing described in Embodiment 1. The method for making chip numbers during wafer manufacturing specifically includes:

[0185] Control the photolithography equipment to sequentially coat the wafer with glue, align exposure, develop, etch and remove photoresist, and create chip numbers for each chip in the wafer;

[0186] Among them, the alignment exposure includes:

[0187] (1) Select a chip in the wafer as the chip to be exposed.

[0188] (2) Controlling the additional mask to be aligned with the chip to be exposed, and exposing the chip to be exposed, so that the chip to be exposed has a photoresist pattern containing the second number.

[0189] (3) Determine whether all chips in the wafer have been exposed to obtain a third determination result.

[0190] (4) If the third judgment result is no, an unexposed chip of the wafer is selected as the chip to be exposed, and the process returns to the step of “controlling the alignment of the additional mask and the chip to be exposed”.

[0191] (5) If the third judgment result is yes, a one-time exposure area of ​​the wafer is selected as the area to be exposed, and the wafer includes multiple one-time exposure areas.

[0192] (6) Controlling the original mask to be aligned with the area to be exposed, and exposing the area to be exposed, so that each chip in the area to be exposed has a photoresist pattern including a component pattern, a first number, and a second number.

[0193] (7) Determine whether all the first exposure areas in the wafer have been exposed, and obtain a fourth determination result.

[0194] (8) If the result of the fourth judgment is no, then an unexposed once-exposure area of ​​the wafer is selected as the area to be exposed, and the process returns to the step of “controlling the alignment of the original mask and the area to be exposed”.

[0195] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0196] This article uses specific examples to illustrate the principles and implementation methods of this application. The description of the above embodiments is only used to help understand the method and core ideas of this application. At the same time, for those skilled in the art, according to the ideas of this application, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as limiting this application.

Claims

1. A device for making chip numbers in a wafer manufacturing process, characterized in that: The device for making chip numbers in the wafer manufacturing process includes: photolithography equipment, original mask and additional mask; The original mask is used to expose a single exposure area of ​​the wafer during a single exposure, and the single exposure area is a partial area of ​​the wafer; the original mask is divided into A areas, each of which corresponds to a chip in the single exposure area; each of the areas includes a component area and a first numbered area, the content and position of the component areas in different areas are the same, and the content of the first numbered areas in different areas is different; the content of the component area is a component pattern; the content of the first numbered area is a first number, and the first number is used to characterize the position of the chip in the single exposure area; wherein A is a positive integer greater than 0; The additional mask includes a second numbering area, the content of the second numbering area is a second number, and the second number is used to characterize the position of the single exposure area in the wafer; The photolithography equipment is used to perform photolithography on the wafer based on the original mask and the additional mask, and to generate a chip number for each chip in the wafer.

2. The device for making chip numbers in a wafer manufacturing process according to claim 1, characterized in that: The first numbered area includes: a plurality of straight lines and a plurality of graphics; The multiple straight lines are distributed in a rectangular array, forming B rows and C columns; where B and C are both constants; The direction from the last row to the first row is defined as upward, each of the multiple graphics is located above a straight line, and different graphics are located above different straight lines; the position of the graphics is used to characterize the position of the chip in a single exposure area.

3. The device for making chip numbers in a wafer manufacturing process according to claim 2, characterized in that: B is 4, and the graphics in the graphic area on each row respectively represent the number of rows of the chip in the single exposure area, the number of columns of the chip in the single exposure area, the number of rows of the single exposure area in the wafer, and the number of columns of the single exposure area in the wafer; the graphics in the first numbered area are located in the graphic area on the row representing the number of rows of the chip in the single exposure area and in the graphic area on the row representing the number of columns of the chip in the single exposure area.

4. The device for making chip numbers in a wafer manufacturing process according to claim 3, characterized in that: The second numbering area includes a plurality of rows of first patterns, each row of the first pattern has a plurality of graphics located in different columns, and the number of columns of the graphics is the same as the number of columns of the straight lines; a row of the first pattern is used to represent the number of rows of the single exposure area in the wafer or the number of columns of the single exposure area in the wafer, and two rows of the first pattern are used to represent the position of the single exposure area in the wafer; Alternatively, the second numbered area includes multiple second patterns, each second pattern has two rows of third patterns, each row of third patterns has a number of graphics located in different columns, and the number of columns of the graphics is the same as the number of columns of the straight lines; each second pattern is used to characterize the position of a single exposure area in the wafer.

5. The device for making chip numbers in a wafer manufacturing process according to claim 2, characterized in that: C is 4, and the graphics in the graphic area on each column respectively represent the number of rows of the chip in the single exposure area, the number of columns of the chip in the single exposure area, the number of rows of the single exposure area in the wafer, and the number of columns of the single exposure area in the wafer; the graphics in the first numbered area are located in the graphic area on the column representing the number of rows of the chip in the single exposure area and in the graphic area on the column representing the number of columns of the chip in the single exposure area.

6. The device for making chip numbers in a wafer manufacturing process according to claim 5, characterized in that: The second numbering area includes a plurality of columns of first patterns, each column of the first patterns has a plurality of graphics located in different rows, and the number of rows of the graphics is the same as the number of rows of the straight lines; one column of the first patterns is used to represent the number of rows of the single exposure area in the wafer or the number of columns of the single exposure area in the wafer, and two columns of the first patterns are used to represent the position of the single exposure area in the wafer; Alternatively, the second numbered area includes multiple second patterns, each of which has two columns of third patterns, each column of third patterns has a number of graphics located in different rows, and the number of rows of the graphics is the same as the number of rows of straight lines; each second pattern is used to characterize the position of a single exposure area in the wafer.

7. A method for making chip numbers in a wafer manufacturing process, based on the device for making chip numbers in a wafer manufacturing process according to any one of claims 1 to 6, characterized in that: The method for making chip numbers in the wafer manufacturing process specifically includes: Control the photolithography equipment to sequentially coat the wafer with glue, align exposure, develop, etch and remove photoresist, and create chip numbers for each chip in the wafer; Among them, the alignment exposure includes: Selecting a one-time exposure area of ​​the wafer as the area to be exposed; the wafer includes a plurality of one-time exposure areas; Controlling the original mask to be aligned with the area to be exposed, and exposing the area to be exposed, so that each chip in the area to be exposed has a photoresist pattern including a component pattern and a first number; Determine whether all the first exposure areas on the wafer have been exposed, and obtain a first determination result; If the first judgment result is no, then selecting an unexposed once-exposure area of ​​the wafer as the area to be exposed, and returning to the step of "controlling the alignment of the original mask with the area to be exposed"; If the first judgment result is yes, then selecting a chip as a chip to be exposed; Controlling the additional mask to be aligned with the chip to be exposed, and exposing the chip to be exposed, so that the chip to be exposed has a photoresist pattern including a component pattern, a first number and a second number; Determine whether all chips in the wafer have been exposed to obtain a second determination result; If the second judgment result is no, an unexposed chip of the wafer is selected as the chip to be exposed, and the process returns to the step of "controlling the alignment of the additional mask and the chip to be exposed".

8. The method for making chip numbers in a wafer manufacturing process according to claim 7, characterized in that: Controlling the additional mask to align with the chip to be exposed, and exposing the chip to be exposed so that the chip to be exposed has a photoresist pattern including a component pattern, a first number and a second number, specifically comprising: Controlling the additional mask to be aligned with the chip to be exposed for the first time, so that the first pattern of the first target row in the additional mask is aligned with the graphic area on the first target row in the chip to be exposed, and shielding other parts of the additional mask except the first pattern of the first target row, exposing the chip to be exposed, so that the chip to be exposed has a photoresist pattern including a component pattern, a first number and a third number; the first pattern of the first target row, the pattern in the graphic area on the first target row and the third number are all used to characterize the number of rows of the exposure area in the wafer; Control the additional mask to be aligned with the chip to be exposed for the second time, so that the first pattern of the second target row in the additional mask is aligned with the graphic area on the second target row in the chip to be exposed, and cover the other parts of the additional mask except the first pattern of the second target row, and expose the chip to be exposed so that the chip to be exposed has a photoresist pattern including a component pattern, a first number, a third number and a fourth number; the first pattern of the second target row, the graphic in the graphic area on the second target row and the fourth number are all used to characterize the number of columns of the single exposure area in the wafer; the third number and the fourth number constitute the second number.

9. The method for making chip numbers in a wafer manufacturing process according to claim 7, characterized in that: Controlling the additional mask to align with the chip to be exposed, and exposing the chip to be exposed so that the chip to be exposed has a photoresist pattern including a component pattern, a first number and a second number, specifically comprising: Control the additional mask to be aligned with the chip to be exposed, so that a row of the third pattern in the second pattern of the target block in the additional mask is aligned with the graphic area on the third target row in the chip to be exposed, and another row of the third pattern in the second pattern of the target block in the additional mask is aligned with the graphic area on the fourth target row in the chip to be exposed, and cover other parts of the additional mask except the second pattern of the target block, and expose the chip to be exposed so that the chip to be exposed has a photoresist pattern including a component pattern, a first number and a second number; the row of the third pattern in the second pattern of the target block and the graphics in the graphic area on the third target row are both used to represent the number of rows of the single exposure area in the wafer, and the another row of the third pattern in the second pattern of the target block and the graphics in the graphic area on the fourth target row are both used to represent the number of columns of the single exposure area in the wafer.

10. A method for making chip numbers in a wafer manufacturing process, based on the device for making chip numbers in a wafer manufacturing process according to any one of claims 1 to 6, characterized in that: The method for making chip numbers in the wafer manufacturing process specifically includes: Control the photolithography equipment to sequentially coat the wafer with glue, align exposure, develop, etch and remove photoresist, and create chip numbers for each chip in the wafer; Among them, the alignment exposure includes: Select a chip in the wafer as the chip to be exposed; Controlling the additional mask to align with the chip to be exposed, and exposing the chip to be exposed so that the chip to be exposed has a photoresist pattern containing a second number; Determine whether all chips in the wafer have been exposed to obtain a third determination result; If the third judgment result is no, then an unexposed chip of the wafer is selected as the chip to be exposed, and the process returns to the step of "controlling the additional mask to be aligned with the chip to be exposed"; If the third judgment result is yes, then selecting a one-time exposure area of ​​the wafer as the area to be exposed; the wafer includes multiple one-time exposure areas; Controlling the original mask to be aligned with the area to be exposed, and exposing the area to be exposed, so that each chip in the area to be exposed has a photoresist pattern including a component pattern, a first number and a second number; Determine whether all the first exposure areas on the wafer have been exposed to obtain a fourth determination result; If the fourth judgment result is no, then an unexposed once-exposure area of ​​the wafer is selected as the area to be exposed, and the process returns to the step of "controlling the alignment of the original mask with the area to be exposed".

Images