Circuit board and chip package including same

Abstract

A circuit board according to an embodiment includes: a first metal layer; and a second metal layer disposed on the first metal layer, in which the first metal layer includes an oxide layer formed by oxidizing a region of a predetermined depth from a lower surface of the first metal layer, the first metal layer and the second metal layer include a plurality of electrode patterns disposed on the oxide layer and spaced apart from each other, the oxide layer insulates the plurality of electrode patterns from each other.

Description

Technical Field

[0001] The embodiments relate to a circuit board, and more particularly, to a circuit board applied to a smart IC and a chip package including the circuit board. Background Art

[0002] A smart IC card is a card in which at least one integrated circuit chip or chip module is embedded. More specifically, a smart IC card is usually made of plastic resin into the shape of a thin card. In addition, a smart IC card has a central processing unit such as a microprocessor that can process information and input and output information without a separate power supply on the card, and a storage device that stores a certain amount of information. A smart IC card refers to a device that can perform simple operations by itself. In order to realize such a smart IC card, a chip package and a card body on which the chip package is mounted are required. In this case, the chip package includes a thin semiconductor chip mounted on a circuit pattern of a printed circuit board, and a contact terminal that electrically connects to the circuit pattern of the semiconductor chip on the opposite side of the printed circuit board to an external card reader or the like in a contact manner or a contactless manner.

[0003] The above-mentioned smart IC card is widely used in various fields such as credit cards, SIM cards, security cards and ID cards. A circuit board applied to such a smart IC card includes an insulating layer and a circuit pattern layer provided on the insulating layer.

[0004] At this time, the circuit pattern layer includes a joint and a contact portion. The joint refers to the upper surface of the circuit pattern layer. For example, the joint refers to the surface of the circuit pattern layer connected to the IC chip. In addition, the contact refers to the lower surface or second surface of the circuit pattern layer. For example, the contact refers to the surface of the circuit pattern layer that contacts an external device (e.g., a card reader).

[0005] In addition, a surface treatment layer is provided on each of the bonding part and the contact part of the circuit pattern layer. The surface treatment layer is formed to give the bonding part and the contact part of the circuit pattern layer wire bonding performance, corrosion resistance, oxidation resistance, wear resistance and hardness above a certain level.

[0006] However, the conventional circuit board as described above must form a surface treatment layer on the circuit pattern layer, so the manufacturing process of the circuit board is complicated and the manufacturing cost increases. In addition, the conventional circuit board has a problem that the thickness of the surface treatment layer is increased by the total thickness.

[0007] (Patent Document 1) KR 10-2002-0011361A Summary of the invention

[0008] Technical issues

[0009] The embodiment provides a circuit board with a novel structure and a chip package including the circuit board.

[0010] In addition, the embodiment provides a circuit board from which a surface treatment layer on at least one of a bonding portion and a contact portion of a circuit pattern layer is removed, and a chip package including the same.

[0011] In addition, the embodiment provides a circuit board that can be thinned by significantly reducing the overall thickness and a chip package including the same.

[0012] In addition, the embodiment provides a circuit board capable of removing an insulating layer included in a conventional circuit board and a chip package including the same.

[0013] In addition, the embodiment provides a circuit board capable of improving adhesion between an insulating layer and a circuit pattern layer and a chip package including the same.

[0014] In addition, the embodiment provides a circuit board including a circuit pattern layer having upper, side, and lower surfaces with different surface roughnesses, and a chip package including the circuit board.

[0015] Technical Solution

[0016] According to an embodiment, a circuit board includes: a first metal layer; and a second metal layer, which is arranged on the first metal layer, wherein the first metal layer includes an oxide layer formed by oxidizing a region at a predetermined depth from a lower surface of the first metal layer, the first metal layer and the second metal layer include a plurality of electrode patterns arranged on the oxide layer and spaced apart from each other, and the oxide layer insulates the plurality of electrode patterns.

[0017] In addition, the circuit board further includes an organic layer disposed below the lower surface of the oxide layer, and the organic layer functions together with the oxide layer as an insulating layer for insulating between the plurality of electrode patterns.

[0018] In addition, the second metal layer is an alloy layer including nickel (Ni) and iron (Fe), and the first metal layer is a metal layer electroplated or deposited below a lower surface of the second metal layer.

[0019] In addition, the second metal layer includes: a first metal, the content of the first metal is in the range of 60wt% to 80wt%; a second metal, the content of the second metal is in the range of 10wt% to 22wt%; a third metal, the content of the third metal is in the range of 3wt% to 20wt%; and a fourth metal, the content of the fourth metal is in the range of 3wt% to 10wt%, wherein the first metal contains one of nickel (Ni) and iron (Fe), the second metal contains chromium (Cr), the third metal contains one of nickel (Ni) and iron (Fe) different from the first metal, and the fourth metal contains one of silver (Ag), silicon (Si) and a silver (Ag)-silicon (Si) alloy.

[0020] In addition, the first metal layer includes copper (Cu).

[0021] In addition, the total thickness of the first metal layer including the oxide layer is in the range of 7 μm to 15 μm, the thickness of the oxide layer in the first metal layer is in the range of 3 μm to 5 μm, and the thickness of the second metal layer is in the range of 100 μm to 200 μm.

[0022] In addition, the total thickness of the first metal layer including the oxide layer is in the range of 2 μm to 10 μm, the thickness of the oxide layer in the first metal layer is in the range of 0.2 μm to 5 μm, and the thickness of the second metal layer is in the range of 20 μm to 50 μm.

[0023] In addition, the oxide layer includes at least one opening, the first metal layer includes a first region vertically overlapping the opening and a second region other than the first region, wherein a recess is formed in the first region of the first metal layer and the recess is connected to the opening, and a thickness of the first region of the first metal layer is less than a thickness of the second region of the first metal layer.

[0024] In addition, the second metal layer includes a third region vertically overlapping the opening and the recess and a fourth region other than the third region, the recess penetrates the upper and lower surfaces of the first metal layer, and the lower surface of the third region of the second metal layer does not contact the first metal layer and the oxide layer and is exposed.

[0025] In addition, the circuit board further includes a first adhesive layer disposed between the oxide layer and the organic layer, the organic layer includes at least one through hole, and the first adhesive layer includes an opening area vertically overlapping the through hole.

[0026] In addition, the lower surface of the oxide layer of the first metal layer has an arithmetic mean roughness (Rz) of 0.5 μm to 0.9 μm or a 10-point average roughness (Rz) of 1.5 μm to 2.5 μm.

[0027] On the other hand, according to an embodiment, a chip package includes: an insulating layer, the insulating layer including at least one through-hole; a circuit pattern layer, the circuit pattern layer is arranged on the insulating layer; an adhesive layer, the adhesive layer is arranged below the lower surface of the insulating layer; an IC chip, the IC chip is attached to the adhesive layer; and a connecting member, the connecting member connecting the lower surface of the circuit pattern layer vertically overlapping the through-hole with the IC chip, and wherein the circuit pattern layer includes: a first metal layer; and a second metal layer, the second metal layer is arranged on the first metal layer, and the first metal layer includes an oxide layer formed by oxidizing a region of a predetermined depth from the lower surface of the first metal layer and corresponding to the insulating layer, and the second metal layer is an alloy layer containing nickel (Ni) and iron (Fe).

[0028] Additionally, an adhesion layer is disposed below the lower surface of the oxide layer.

[0029] In addition, the chip package includes an organic layer disposed below the oxide layer, and the adhesive layer is disposed below a lower surface of the organic layer.

[0030] In addition, the chip package includes: a first surface layer, the first surface layer includes nickel (Ni), and the first surface layer is arranged below the lower surface of the first metal layer vertically overlapping with the through hole; and a second surface layer, the second surface layer includes gold (Au), the second surface layer is arranged below the lower surface of the first surface layer, and one end of the connecting member is connected to the terminal of the IC chip, and the other end of the connecting member is connected to the second surface layer.

[0031] Beneficial Effects

[0032] The circuit board of the embodiment includes an insulating layer and a circuit pattern layer disposed on the insulating layer. The circuit pattern layer includes a first metal layer and a second metal layer. In addition, the second metal layer is a rolled alloy layer, and the first metal layer is a metal layer formed on one surface of the rolled alloy layer. At this time, the oxide layer is formed by oxidizing the surface of the first metal layer and is formed on the interface between the first metal layer and the insulating layer. At this time, the oxide layer has a needle-like structure and can improve the adhesion between the first metal layer and the insulating layer.

[0033] Therefore, the embodiment may solve the reliability problem of the circuit pattern layer including the first metal layer peeled from the insulating layer by improving the adhesion between the insulating layer and the first metal layer.

[0034] Furthermore, embodiments may use an oxide layer disposed between the first metal layer and the insulating layer to further improve the insulating properties of the circuit board.

[0035] On the other hand, the embodiment allows the use of an alloy including nickel (Ni)-chromium (Cr)-iron (Fe) and at least one metal selected from the group consisting of silver (Ag), silicon (Si) and alloys thereof to form the second metal layer of the circuit pattern layer. Therefore, the second metal layer in the embodiment can have a wear resistance, corrosion resistance, oxidation resistance and hardness above a specific level. Thus, the embodiment can omit or remove the surface treatment layer that must be formed on the contact portion of the circuit pattern layer, thereby simplifying the manufacturing process of the circuit board and reducing manufacturing costs.

[0036] On the other hand, the first metal layer of the embodiment includes a recessed portion formed in a region vertically overlapping with the through hole of the insulating layer. In addition, the recessed portion can solve the electrical reliability problem caused by the oxide layer remaining on the joint of the circuit pattern layer. Therefore, the embodiment can improve the electrical reliability of the circuit board and the chip package, and further improve the product reliability.

[0037] In addition, the recessed portion of the first metal layer may have a structure that penetrates the first metal layer. Therefore, the lower surface of the second metal layer vertically overlapping the recessed portion of the first metal layer can be used as a bonding portion of the circuit pattern layer. At this time, the second metal layer of the circuit pattern layer in the embodiment may have a line bonding property above a specific level. Thus, the embodiment can not only omit or remove the surface treatment layer that must be formed on the contact portion of the circuit pattern layer, but also omit or remove the surface treatment layer that must be formed on the bonding portion of the circuit pattern layer. Thus, the embodiment can further simplify the manufacturing process of the circuit board and correspondingly further reduce the manufacturing cost.

[0038] In addition, the embodiment can form the insulating layer using only the oxide layer formed on the lower surface of the first metal layer. That is, the embodiment allows the metal oxide layer to be used as the insulating layer while removing the insulating layer of the organic material.

[0039] That is, the insulating layer of the circuit board of the embodiment can be formed only by the oxide layer formed on the lower surface of the first metal layer. Therefore, the embodiment can further reduce the thickness of the circuit board by using the oxide layer to perform the function of the insulating layer.

[0040] In addition, the embodiment can increase the thickness of the second metal layer of the circuit pattern layer by the thickness of the insulating layer of the organic material by removing the insulating layer of the organic material. At this time, the second metal layer is a rolled alloy layer. At this time, when the rolled alloy layer is manufactured to a thickness of less than 100 μm, an additional rolling process is required, thereby increasing the manufacturing cost. Therefore, the embodiment can omit the additional rolling process for reducing the thickness of the rolled alloy layer without increasing the thickness of the product. Thus, the embodiment can simplify the manufacturing process of the circuit board, thereby reducing the manufacturing cost. In addition, the embodiment can improve the overall bending characteristics of the circuit board by increasing the thickness of the second metal layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] Figure 1 is a diagram showing a chip package according to a comparative example.

[0042] Figure 2 is a diagram showing a circuit board according to a first embodiment, Figure 3 yes Figure 2 A plan view of the circuit board viewed from the top, and Figure 4 yes Figure 2 A plan view of a circuit board as viewed from the bottom.

[0043] Figure 5 It is shown Figure 2 FIG. 1 is a diagram of a first variation of a circuit board.

[0044] Figure 6 It is shown Figure 2 FIG. 1 is a diagram of a third variation of a circuit board.

[0045] Figure 7 It is shown Figure 2 FIG. 4 is a diagram of a fourth variation of a circuit board.

[0046] Figure 8 is a diagram showing a chip package according to a first embodiment.

[0047] Fig. 9 is a diagram showing a circuit board according to a second embodiment.

[0048] Fig.10 It is shown Fig. 9 FIG. 2 is a diagram of a modified example of the circuit board of the second embodiment.

[0049] Fig.11 is a diagram showing a chip package according to a second embodiment. DETAILED DESCRIPTION

[0050] Hereinafter, exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings, wherein the same reference numerals are used to represent the same or similar elements, and redundant descriptions thereof will be omitted. The suffixes "module" and "unit" of the components used in the following description are given or mixed only in consideration of the ease of preparing the description, and have no mutually distinguished meanings or functions. In addition, in the following description of the embodiments of the present disclosure, when it is determined that the key points of the embodiments disclosed herein may be obscured, the detailed description of the related art will be omitted. In addition, the accompanying drawings are included to provide a further understanding of the present invention, are incorporated into and constitute a part of the description, and it should be understood that the present invention is intended to cover all modifications, equivalents or alternatives that fall within the spirit and scope of the present invention.

[0051] Terms including ordinal numbers such as first, second, etc. may be used to describe various components, but the elements are not limited to these terms. The terms are only used to distinguish one component from another.

[0052] When a component is referred to as being "connected" or "in contact with" another component, it may be directly connected or joined to another component, but it should be understood that other components may exist between them. When a component is referred to as being "directly connected" or "in direct contact with" another component, it should be understood that other components may not exist between them.

[0053] Unless the context clearly implies otherwise, a singular expression includes a plural expression.

[0054] In this application, terms such as "include" or "have" are used to indicate the presence of features, quantities, steps, operations, components, parts, or combinations thereof described in the specification. However, it should be understood that the terms do not exclude the presence or addition of one or more other features, quantities, steps, operations, components, parts, or combinations thereof.

[0055] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0056] -Comparative Example-

[0057] Before explaining the embodiment, a comparative example compared with the circuit board of the embodiment of the present disclosure will be described.

[0058] Figure 1 is a diagram showing a chip package according to a comparative example.

[0059] Reference Figure 1 , the chip package according to the comparative example includes an insulating layer 10 , a circuit pattern layer 20 , a first surface treatment layer 30 , a second surface treatment layer 40 , an adhesive layer 50 , an IC chip 60 , and a connecting member 70 .

[0060] The chip package of the comparative example includes an insulating layer 10 , and a circuit pattern layer 20 is disposed on at least one surface of the insulating layer 10 .

[0061] At this time, the circuit pattern layer 20 in the comparative example is a copper layer including pure copper.

[0062] The insulating layer 10 includes at least one through hole 15. In addition, the circuit pattern layer 20 includes a joint portion vertically overlapping the through hole 15. For example, at least a portion of the circuit pattern layer 20 vertically overlaps the through hole 15, and the lower surface of the circuit pattern layer 20 vertically overlapping the through hole 15 serves as a joint portion electrically connected to the IC chip 60.

[0063] In addition, the upper surface of the circuit pattern layer 20 is used as a contact portion, for example, a contact portion that contacts an external device (for example, a card reader).

[0064] At this time, different characteristics are required for the bonding portion and the contact portion of the circuit pattern layer 20 .

[0065] For example, the bonding portion of the circuit pattern layer 20 needs to have a wire bonding property of a certain level or more in order to bond the connection member 70 electrically connected to the IC chip 60 .

[0066] In addition, the contact portion of the circuit pattern layer 20 is exposed to the outside of the chip package, and therefore requires corrosion resistance, oxidation resistance, wear resistance, and hardness above a certain level to achieve continuous connection with an external device.

[0067] Therefore, the circuit board of the comparative example includes a first surface treatment layer 30 formed on the joint portion of the circuit pattern layer 20 and a second surface treatment layer 40 formed on the contact portion of the circuit pattern layer 20. The first surface treatment layer 30 and the second surface treatment layer 40 each include a nickel metal layer (Ni) and a gold metal layer (Au).

[0068] The nickel metal layer is used as a barrier layer to prevent copper (Cu) from diffusing into the gold metal layer while preventing oxidation of copper (Cu) forming the circuit pattern layer 20. In addition, the gold metal layer of the first surface treatment layer 30 is formed on the outermost surface of the joint portion of the circuit pattern layer 20, thereby providing the joint portion with wire bondability above a certain level. In addition, the gold metal layer of the second surface treatment layer 40 is formed on the outermost surface of the contact portion of the circuit pattern layer 20, thereby providing the joint portion with corrosion resistance, oxidation resistance, wear resistance and hardness at a certain level.

[0069] However, the circuit board of the comparative example described above must form the first surface treatment layer 30 and the second surface treatment layer 40 on the joint portion and the contact portion of the circuit pattern layer 20. Therefore, there are problems that the manufacturing process is complicated and the manufacturing cost increases.

[0070] In addition, the circuit board of the comparative example reduces the thickness of the gold metal layer of the second surface treatment layer 40 to achieve a reduction in manufacturing cost. However, when the thickness of the gold metal layer is reduced, there is a problem that the gold metal layer is worn during long-term use of the circuit board, thereby damaging the product design.

[0071] On the other hand, in the comparative example, the circuit pattern layer 20 is formed of an aluminum alloy to remove at least one of the first surface treatment layer and the second surface treatment layer as described above. However, the aluminum alloy has a low hardness characteristic. Therefore, in order to make the contact portion of the circuit pattern layer have a certain level of corrosion resistance, oxidation resistance, wear resistance and hardness, the thickness of the aluminum alloy must be 80 μm or more.

[0072] In addition, when the thickness of the aluminum alloy exceeds 80 μm, the total thickness of the circuit board increases accordingly, and the line width or the spacing of the circuit pattern layer 20 increases, thereby reducing the circuit integration degree.

[0073] -Example-

[0074] Figure 2 is a diagram showing a circuit board according to a first embodiment, Figure 3 Observed from the top Figure 2 The plan view of the circuit board, Figure 4 Observed from the bottom Figure 2 A plan view of a circuit board.

[0075] In the following, reference will be made to Figures 2 to 4 The circuit board of the first embodiment is described in detail.

[0076] Reference Figures 2 to 4 , the circuit board of the first embodiment includes an insulating layer 110 and a circuit pattern layer.

[0077] Specifically, the circuit pattern layer includes a first metal layer 120 disposed on the insulating layer 110 and a second metal layer 130 disposed on the first metal layer 120. In addition, one surface of the first metal layer 1210 includes an oxide layer 125 formed using an oxide. For example, the oxide layer 125 of the first metal layer 120 is formed between the first metal layer 120 and the insulating layer 110.

[0078] The oxide layer 125 may have a function of improving the bonding force between the circuit pattern layer and the insulating layer 110. In addition, the oxide layer 125 may function as the insulating layer 110. For example, the oxide layer 125 formed on the surface of the first metal layer 120 has non-conductivity. Therefore, the oxide layer 125 may also be said to be an insulator that performs an insulating function together with the insulating layer 110 in the circuit board of the first embodiment.

[0079] At this time, although the oxide layer 125 is illustrated as a layer separated from the first metal layer 120 in the drawing, the oxide layer 125 actually represents a portion of the first metal layer 120 .

[0080] Therefore, the insulating layer of the circuit board of the first embodiment may include a “first insulating layer” corresponding to the insulating layer 110 and a “second insulating layer” corresponding to the oxide layer 125 of the first metal layer 120 .

[0081] The insulating layer 110 includes an insulating material.

[0082] The insulating layer 110 has a thickness in the range of 60 μm to 120 μm, or a thickness in the range of 70 μm to 110 μm, or a thickness in the range of 80 μm to 100 μm.

[0083] If the thickness of the insulating layer 110 is less than 60 μm, the rigidity of the circuit board may be weakened, and thus the warping characteristics of the circuit board may be reduced. If the thickness of the insulating layer 110 is less than 60 μm, the circuit pattern layer may not be stably formed on the circuit board. For example, if the thickness of the insulating layer 110 is less than 60 μm, the processability of the patterning process for forming the circuit pattern layer is reduced.

[0084] If the thickness of the insulating layer 110 exceeds 120 μm, the overall thickness of the circuit board increases, and thus the thickness of the chip package increases.

[0085] The insulating layer 110 includes at least one through hole 110T.

[0086] The through hole 110T penetrates the upper and lower surfaces of the insulating layer 110 .

[0087] The circuit pattern layer is formed on the insulating layer 110. The circuit pattern layer is formed on the upper surface of the insulating layer 110. However, the embodiment is not limited thereto, and the circuit pattern layer may be formed on the lower surface of the insulating layer 110.

[0088] The circuit pattern layer includes a plurality of metal layers.

[0089] For example, the circuit pattern layer includes a first metal layer 120 disposed on an upper surface of the insulating layer 110. In addition, the circuit pattern layer includes a second metal layer 130 disposed on an upper surface of the first metal layer 120.

[0090] The second metal layer 130 is an alloy layer. In addition, the first metal layer 120 can be said to be a plated metal layer or a deposited metal layer formed on one surface of the second metal layer 130 as an alloy layer. The first metal layer 120 is provided on the lower surface of the second metal layer 130 with a specific thickness to form an oxide layer 125.

[0091] That is, the second metal layer 130 is an alloy layer manufactured by a rolling method. Therefore, due to the characteristics of the alloy layer manufactured by the rolling method, the surface roughness of the second metal layer 130 can have a very low value. The first metal layer 120 can be a plating layer formed on one surface of the second metal layer 130 by a chemical plating method or a deposition layer deposited by a sputtering method.

[0092] The first metal layer 120 includes copper. However, the embodiment is not limited thereto, and the first metal layer 120 may be formed by electroplating or depositing a metal layer other than copper on one surface of the second metal layer 130.

[0093] The arithmetic mean roughness (Ra) of the oxide layer 125 of the first metal layer 120 is in the range of 0.5 μm to 0.9 μm. In addition, the 10-point average roughness (Rz) of the oxide layer 125 of the first metal layer 120 may be in the range of 1.5 μm to 2.5 μm. At this time, the oxide layer 125 is a part of the first metal layer 120, and therefore, the arithmetic mean roughness (Ra) and the 10-point average roughness (Rz) of the oxide layer 125 can be said to be the apparent roughness of the lower surface of the first metal layer 120.

[0094] Therefore, the embodiment may improve the adhesive force between the circuit pattern layer and the insulating layer 110 by making the oxide layer 125 of the first metal layer 120 have the surface roughness within the above range.

[0095] At this time, the first metal layer 120 includes an oxide layer 125 formed on the lower surface in contact with the insulating layer 110. Specifically, the first embodiment includes an oxide layer 125 formed at the interface between the first metal layer 120 and the insulating layer 110. The oxide layer 125 is formed by oxidizing a specific depth area of ​​the lower surface of the first metal layer 120 using an oxidizing material. The oxide layer 125 has a needle-like structure. In addition, the embodiment can improve the bonding force with the insulating layer 110 by having the needle-like structure of the oxide layer 125. Therefore, the embodiment can solve the problem of the circuit pattern layer being peeled off from the insulating layer 110.

[0096] In addition, the oxide layer 125 of the first metal layer 120 has insulating properties. Therefore, the embodiment can further improve the insulating properties between the circuit pattern layer including the first metal layer 120 and the insulating layer 110. Therefore, the embodiment can improve the electrical reliability of the circuit pattern layer.

[0097] The oxide layer 125 includes an opening 125T. For example, the oxide layer 125 is partially formed on the lower surface of the first metal layer 120. For example, the oxide layer 125 includes an opening 125T vertically overlapping the through hole 110T of the insulating layer 110 on the lower surface of the first metal layer 120.

[0098] Therefore, at least a portion of the first metal layer 120 vertically overlaps with the through hole 110T of the insulating layer 110 and the opening 125T of the oxide layer 125. In addition, in the first embodiment, at least a portion of the oxide layer 125 does not vertically overlap with the first metal layer 120 and the second metal layer 130. For example, the first metal layer 120 and the second metal layer 130 include a plurality of electrode patterns (not shown) horizontally spaced apart from each other on the insulating layer 110. And, the oxide layer 125 of the first embodiment is disposed on the upper surface of the insulating layer 110 between the plurality of electrode patterns. Thus, the first embodiment can further improve the insulation characteristics between the plurality of electrode patterns by using the oxide layer 125.

[0099] In the first embodiment, the thickness of the first metal layer 120 satisfies the range of 2 μm to 10 μm. Preferably, the thickness of the first metal layer 120 satisfies the range of 2.5 μm to 9.5 μm. More preferably, the thickness of the first metal layer 120 satisfies the range of 3 μm to 9 μm. At this time, the thickness of the first metal layer 120 represents the total thickness of the first metal layer 120 including the thickness of the oxide layer 125.

[0100] If the thickness of the first metal layer 120 is less than 2 μm, the oxide layer 125 of the first metal layer 120 does not have a target level of surface roughness, and thus the bonding force between the insulating layer 110 may decrease. In addition, if the thickness of the first metal layer 120 is less than 2 μm, the oxide layer 125 may not have a target thickness. In addition, if the oxide layer 125 does not have a target thickness, the bonding force between the first metal layer 120 and the insulating layer 110 may decrease, or the insulating properties of the circuit board may decrease.

[0101] In addition, if the thickness of the first metal layer 120 exceeds 10 μm, the thickness of the circuit pattern layer and the thickness of the circuit board may increase corresponding to the thickness of the first metal layer 120. Therefore, it may be difficult to thin the circuit board and the chip package.

[0102] The thickness of the oxide layer 125 in the first metal layer 120 satisfies the range of 0.2 μm to 5 μm. Preferably, the thickness of the oxide layer 125 satisfies the range of 0.22 μm to 4.8 μm. More preferably, the thickness of the oxide layer 125 satisfies the range of 0.25 μm to 4.5 μm.

[0103] If the thickness of the oxide layer 125 in the first metal layer 120 is less than 0.2 μm, the insulation property between the circuit pattern layer and the insulating layer 110 provided by the oxide layer 125 may be reduced. In addition, if the thickness of the oxide layer 125 exceeds 5 μm, the strength of the oxide layer 125 may be reduced, the strength of the oxide layer 125 is reduced, and a problem of cracking of the oxide layer 125 may occur. In addition, if the strength of the oxide layer 125 is reduced, the bonding force between the insulating layer 110 and the first metal layer 120 is reduced, and thus a problem of peeling of the first metal layer 120 from the insulating layer 110 may occur.

[0104] The second metal layer 130 is disposed on the first metal layer 120. The second metal layer 130 is an alloy layer. For example, the second metal layer 130 is formed of an alloy containing nickel (Ni) or iron (Fe) as a main component. For example, the second metal layer 130 may be an alloy layer formed by a rolling method.

[0105] The thickness of the second metal layer 130 is in the range of 20 μm to 50 μm. For example, the thickness of the second metal layer 130 is in the range of 25 μm to 45 μm. For example, the thickness of the second metal layer 130 is in the range of 30 μm to 40 μm. If the thickness of the second metal layer 130 is less than 20 μm, the resistance value of the second metal layer 130 may increase, and thus the signal loss may increase. For example, if the thickness of the second metal layer 130 is less than 20 μm, the signal transmission characteristics of the circuit board may be reduced. If the thickness of the second metal layer 130 exceeds 50 μm, the total thickness of the circuit board may increase.

[0106] At this time, the embodiment allows the thickness of the second metal layer 130 to be less than or equal to 50 μm while omitting or removing the surface treatment layer formed on the contact portion of the second metal layer 130. This can be achieved by the characteristics of the alloy forming the second metal layer 130 described below.

[0107] The circuit pattern layer including the first metal layer 120 and the second metal layer 130 includes an upper surface and a lower surface. The upper surface of the circuit pattern layer refers to the upper surface of the second metal layer 130. In addition, the lower surface of the circuit pattern layer refers to the lower surface of the first metal layer 120.

[0108] Specifically, the contact portion of the circuit pattern layer refers to the upper surface of the second metal layer 130. In addition, the contact portion of the circuit pattern layer refers to the outermost area arranged on the circuit board and the chip package. For example, the contact portion of the circuit pattern layer refers to the area exposed to the outside of the circuit board and the chip package.

[0109] In addition, the junction of the circuit pattern layer refers to an area connected to the IC chip 170 in the chip package. For example, the junction of the circuit pattern layer refers to an area vertically overlapping with the through hole 110T of the insulating layer 110. At this time, the oxide layer 125 of the first metal layer 120 is partially formed on the lower surface of the first metal layer 120. For example, the oxide layer 125 is formed on the remaining area of ​​the lower surface of the first metal layer 120 except for the area vertically overlapping with the through hole 110T. Therefore, the oxide layer 125 includes an opening 125T vertically overlapping with the through hole 110T of the insulating layer 110. In addition, the area of ​​the lower surface of the first metal layer 120 vertically overlapping with the through hole 110T of the insulating layer 110 and the opening 125T of the oxide layer 125 is used as a junction.

[0110] At this time, the second metal layer 130 is required to have corrosion resistance, oxidation resistance, wear resistance and hardness above a certain level. For example, the contact portion of the circuit pattern layer corresponding to the upper surface of the second metal layer 130 is required to have corrosion resistance, oxidation resistance, wear resistance and hardness above a certain level.

[0111] Therefore, in the comparative example, the second surface treatment layer 40 is formed on the contact portion of the circuit pattern layer.

[0112] In contrast, in the embodiment, one of the first alloy and the second alloy having corrosion resistance, oxidation resistance, wear resistance, hardness, and wire bonding properties above a certain level is used to form the second metal layer 130. Thus, the embodiment allows the surface treatment layer formed on the contact portion of the second metal layer 130 to be omitted or removed.

[0113] That is, the embodiment enables the second metal layer 130 to have corrosion resistance, oxidation resistance, wear resistance, hardness, and wire bonding properties above a predetermined level without a surface treatment layer by changing the content of the metal in the alloy forming the second metal layer 130. This is achieved by the type of metal constituting the second metal layer 130 and its content, which will be described below.

[0114] Hereinafter, the composition ratio of metals in the alloy forming the second metal layer 130 will be described.

[0115] At this time, the second metal layer 130 is formed using one of the first alloy and the second alloy. The first alloy described above has nickel (Ni) as a main component, and the second alloy has iron (Fe) as a main component.

[0116] -First Alloy-

[0117] The second metal layer 130 may be formed of a first alloy having nickel (Ni) as a main component.

[0118] The first alloy has corrosion resistance, oxidation resistance, wear resistance, hardness, and wire bondability above a specific level.

[0119] That is, the first alloy forming the second metal layer 130 has nickel (Ni) as a main component. For example, the content of nickel (Ni) in the first alloy forming the second metal layer 130 satisfies the range of 60wt% to 80wt%. For example, the content of nickel (Ni) in the first alloy is 65wt% to 78wt% or 70wt% to 75wt%.

[0120] If the content of nickel (Ni) in the first alloy is less than 60wt%, the corrosion resistance, oxidation resistance, wear resistance, hardness and wire bonding of the second metal layer 130 are reduced. Therefore, a surface treatment layer must be formed on the contact portion of the second metal layer 130, which leads to problems of complicated manufacturing process, increased thickness of the circuit board and increased manufacturing cost.

[0121] Specifically, if the content of nickel (Ni) in the first alloy is less than 60wt%, the surface roughness variation rate (%) of the second metal layer 130 exceeds 10%. The surface roughness variation rate (%) is related to the corrosion resistance, oxidation resistance and wear resistance of the second metal layer 130.

[0122] Therefore, the content of nickel (Ni) in the first alloy forming the second metal layer 130 is in the range of 60 wt % to 80 wt %, whereby the surface roughness variation rate (%) is 10% or less, preferably 8% or less, and more preferably 5% or less.

[0123] In addition, when the content of nickel (Ni) in the first alloy exceeds 80wt%, the etching rate (μm / min) in the process of forming the second metal layer 130 using the first alloy decreases. That is, if the content of nickel (Ni) in the first alloy exceeds 80wt%, the hardness of the first alloy is too high, so that the etching rate (μm / min) within a specific range cannot be achieved in the process of forming the second metal layer 130. In addition, if the content of nickel (Ni) in the first alloy exceeds 80wt%, the problem of nickel ions dissolving to the surface of the second metal layer 130 formed by the first alloy occurs.

[0124] On the other hand, the first alloy forming the second metal layer 130 includes chromium (Cr). The content of chromium (Cr) in the first alloy satisfies the range of 10wt% to 22wt%. For example, the content of chromium (Cr) in the first alloy satisfies the range of 11wt% to 21wt% or 12wt% to 18wt%.

[0125] If the content of chromium (Cr) in the first alloy is less than 10 wt %, the amount of nickel eluted to the surface of the second metal layer 130 formed of the first alloy increases.

[0126] At this time, if the content of chromium (Cr) in the first alloy is less than 10wt%, the effect of preventing nickel (Ni) from dissolving out by chromium (Cr) is reduced, and thus, product reliability problems occur due to the dissolution of nickel ions to the outside. Therefore, in the embodiment, the first alloy forming the second metal layer 130 includes chromium (Cr) in an amount of 10wt% or more.

[0127] On the other hand, if the content of chromium (Cr) in the first alloy exceeds 22wt%, the hardness of the second metal layer 130 increases, and thus the etching rate (μm / min) of the second metal layer 130 decreases. In addition, if the content of chromium (Cr) in the second metal layer 130 exceeds 22wt%, the wire bonding property of the second metal layer 130 decreases.

[0128] In addition, when the content of chromium (Cr) in the first alloy is less than 10wt% or greater than 22wt%, the content of other metals (e.g., nickel or iron) is reduced or increased by a corresponding amount, and thus there is a problem because the content of other metals does not satisfy the optimal range described in this article.

[0129] On the other hand, the first alloy forming the second metal layer 130 includes iron (Fe). The content of iron (Fe) in the first alloy satisfies the range of 3wt% to 20wt%. The content of iron (Fe) in the first alloy may satisfy the range of 5wt% to 15wt% or 7wt% to 11wt%. The iron (Fe) in the first embodiment is used to improve the rollability (or ductility) of the first alloy.

[0130] At this time, if the content of iron (Fe) in the first alloy is less than 3 wt %, the rollability of the first alloy is reduced, and thus it is difficult to manufacture the thickness of the first alloy and thus the second metal layer 130 to be 50 μm or less.

[0131] In addition, if the content of iron (Fe) in the first alloy exceeds 20 wt %, the content of nickel (Ni) or iron (Fe) decreases accordingly, and thus, the nickel dissolution amount increases or the surface roughness change rate (%) increases.

[0132] On the other hand, the first alloy forming the second metal layer 130 includes one of silver (Ag), silicon (Si) and silver (Ag)-silicon (Si) alloy. Silver (Ag), silicon (Si) and silver (Ag)-silicon (Si) alloy can enable the first alloy to have a certain level of wire bonding or more.

[0133] Therefore, the first alloy can be any one of a nickel (Ni)-chromium (Cr)-iron (Fe)-silver (Ag) alloy, a nickel (Ni)-chromium (Cr)-iron (Fe)-silver (Ag)-silicon (Si) alloy, and a nickel (Ni)-chromium (Cr)-iron (Fe)-silver (Ag)-silicon (Si) alloy.

[0134] In the first alloy, a content of any one of silver (Ag), silicon (Si) and a silver (Ag)-silicon (Si) alloy is in the range of 3 wt % to 10 wt %.

[0135] If the content of any one of silver (Ag), silicon (Si), and silver (Ag)-silicon (Si) alloy in the first alloy is less than 3 wt %, the wire bonding property of the second metal layer 130 is less than 4 gf.

[0136] If the content of any one of silver (Ag), silicon (Si) and silver (Ag)-silicon (Si) alloy in the first alloy forming the second metal layer 130 exceeds 10wt%, the content of nickel (Ni) or chromium (Cr) or iron (Fe) is correspondingly reduced, and thus a problem occurs in at least one of the resistance (Ω), etching rate (μm / min), surface roughness change rate and nickel dissolution amount of the circuit pattern layer.

[0137] On the other hand, the first alloy forming the second metal layer 130 includes at least one additive.

[0138] For example, the first alloy forming the second metal layer 130 includes at least one additive selected from manganese (Mn), tin (Sn), zinc (Zn), and an alloy including at least two of these metals. For example, an additive selected from manganese (Mn), tin (Sn), zinc (Zn), and an alloy including at least two of these metals is added to refine the structure of the alloy constituting the second metal layer 130, thereby achieving solid solution strengthening.

[0139] Specifically, the content of the additive selected from manganese (Mn), tin (Sn), zinc (Zn), and an alloy including at least two of these metals satisfies the range of 1 wt % to 5 wt %.

[0140] That is, if the content of the additive selected from manganese (Mn), tin (Sn), zinc (Zn) and alloys including at least two of these metals is less than 1wt%, the solid solution strengthening effect is not obvious, and therefore, the wear resistance, oxidation resistance and corrosion resistance of the second metal layer 130 are reduced.

[0141] In addition, if the content of the additive selected from manganese (Mn), tin (Sn), zinc (Zn), and an alloy including at least two of these metals exceeds 5 wt %, the resistance characteristic of the second metal layer 130 increases, and thus the signal loss increases.

[0142] In addition, if the content of the additive selected from manganese (Mn), tin (Sn), zinc (Zn), and an alloy including at least two of these metals exceeds 5 wt %, the hardness of the second metal layer 130 increases and thus the etching rate (μm / min) decreases.

[0143] - Second Alloy -

[0144] On the other hand, the second metal layer 130 may be formed of a second alloy having iron (Fe) as a main component.

[0145] At this time, the second alloy includes the metals constituting the first alloy. However, the content of each metal in the second alloy is different from the content of each metal in the first alloy. For example, the first alloy contains nickel as a main component, and the second alloy contains iron as a main component. Therefore, the content of nickel (Ni), iron (Fe) and chromium (Cr) in the second alloy is different from the content of nickel (Ni), iron (Fe) and chromium (Cr) in the first alloy.

[0146] That is, the second alloy forming the second metal layer 130 contains iron (Fe) as a main component. For example, the content of iron (Fe) in the second alloy satisfies the range of 60wt% to 80wt% or 61wt% to 78wt% or 63wt% to 75wt%. The optimal range of the content of iron (Fe) in the second alloy is 63wt% to 75wt%.

[0147] If the content of iron (Fe) in the second alloy is less than 60wt%, the rollability of the second alloy is reduced, and therefore, the thickness of the second alloy is increased, and in addition, the thickness of the second metal layer 130 is increased. If the content of iron (Fe) in the second alloy exceeds 80wt%, the wear resistance, corrosion resistance and oxidation resistance of the second metal layer 130 formed by the second alloy are reduced. In addition, if the content of iron (Fe) in the second alloy exceeds 80wt%, the resistance (Ω) of the second metal layer 130 formed by the second alloy increases, and therefore, the signal transmission loss increases. In addition, if the content of iron (Fe) in the second alloy is less than 60wt% or exceeds 80wt%, the content of other metals (e.g., nickel or chromium) is reduced or increased by the corresponding content, and therefore, the problem that the content of other metals does not meet the optimal range described in this article occurs.

[0148] On the other hand, the content of chromium (Cr) in the second alloy satisfies the range of 10wt% to 22wt% or 13wt% to 21wt% or 15wt% to 20wt%. That is, the optimal range of the content of chromium (Cr) in the second alloy is 15wt% to 20wt%.

[0149] If the content of chromium (Cr) in the second alloy is less than 10wt%, the amount of nickel dissolved into the surface of the second alloy increases. In addition, if the content of chromium (Cr) in the second alloy is less than 10wt%, the hardness of the second metal layer 130 formed of the second alloy decreases. In addition, if the content of chromium (Cr) in the second alloy exceeds 22wt%, the wire bonding property decreases.

[0150] On the other hand, the content of nickel (Ni) in the second alloy satisfies the range of 3wt% to 20wt% or 5wt% to 18wt% or 7wt% to 15wt%. That is, the optimal range of the content of nickel (Ni) in the second alloy is 7wt% to 15wt%.

[0151] If the content of nickel (Ni) in the second alloy is less than 3wt%, the surface roughness change rate (%) of the second metal layer 130 exceeds 10%. In addition, if the content of nickel (Ni) in the second alloy exceeds 20wt%, the etching rate (μm / min) in the etching process of forming the second metal layer 130 using the second alloy decreases.

[0152] Figure 5 It is shown Figure 2 FIG. 1 is a diagram of a first variation of a circuit board.

[0153] Reference Figure 5 The circuit board of the first modification includes an insulating layer 110 and a circuit pattern layer. The circuit pattern layer includes a first metal layer 120 disposed on the insulating layer 110 and including an oxide layer 125. In addition, the circuit pattern layer includes a second metal layer 130 disposed on the first metal layer 120.

[0154] at this time, Figure 2 The lower surface of the first metal layer 120 of the circuit board has the same height in the entire area. For example, Figure 2 The lower surface of the first metal layer 120 of the circuit board has no step.

[0155] In contrast, in the circuit board of the first variant, the lower surface of the first metal layer 120 has a step. For example, the lower surface of the first metal layer 120 includes a first region vertically overlapping with the through hole 110T of the insulating layer 110 and a second region other than the first region. In addition, the height of the first region of the lower surface of the first metal layer 120 is different from the height of the second region of the lower surface of the first metal layer 120. Preferably, the height of the first region of the lower surface of the first metal layer 120 is located higher than the height of the second region of the lower surface of the first metal layer 120.

[0156] For example, the thickness of the first region of the first metal layer 120 is less than the thickness of the second region. Specifically, the lower surface of the first metal layer 120 includes a recess 120S vertically overlapping the through hole 110T of the insulating layer 110 and the opening 125T of the oxide layer 125. In the process of forming the through hole 110T of the insulating layer 110 and the opening 125T of the oxide layer 125, the recess 120S is formed by removing a portion of the lower surface of the first metal layer 120. At this time, when the recess 120S does not exist, the oxide layer 125 can remain in at least a portion of the region of the lower surface of the first metal layer 120 vertically overlapping the through hole 110T. In addition, if the oxide layer 125 remains in the region overlapping the through hole 110T, the electrical reliability between the IC chip 170 and the circuit pattern layer may be reduced. Therefore, in the first modification, in the process of forming the through hole 110T and the opening 125T, the recess 120S is formed on the lower surface of the first metal layer 120. Thus, the embodiment improves the electrical reliability between the bonding portion of the circuit pattern layer and the IC chip 170 .

[0157] At this time, in the first modification example, the recess 120S is described as being formed by removing a portion of the first metal layer 120 , but is not limited thereto.

[0158] For example, the recess 120S in the second modification example has a through-hole type penetrating the upper and lower surfaces of the first metal layer 120. Therefore, the lower surface of the second metal layer 130 is exposed in the area vertically overlapping with the through hole 110T of the insulating layer 110, the opening 125T of the oxide layer 125, and the recess 120S of the first metal layer 120. In addition, the exposed lower surface of the second metal layer 130 serves as a bonding portion.

[0159] At this time, in the first embodiment and the first modification, the lower surface of the first metal layer 120 is used as the bonding portion of the circuit pattern layer. Therefore, in the first embodiment and the first modification, a surface treatment layer must be formed on the lower surface of the bonding portion for wire bonding with the IC chip 170.

[0160] In contrast, as in the second modification, when the recess 120S penetrates the first metal layer 120, the lower surface of the second metal layer 130 is used as a bonding portion of the circuit pattern layer. In addition, the second metal layer 130 is formed of a first alloy or a second alloy having a line bonding property above a certain level. Therefore, the circuit board of the second modification can also remove the surface treatment layer provided on the bonding portion of the circuit pattern layer.

[0161] Figure 6 It is shown Figure 2 FIG. 1 is a diagram of a third variation of a circuit board.

[0162] Reference Figure 6The circuit board of the third modification includes an insulating layer 110, a first metal layer 120, and a second metal layer 130. At this time, the insulating layer 110, the first metal layer 120, and the second metal layer 130 may have substantially the same structure as in the first embodiment. Therefore, a detailed description thereof will be omitted.

[0163] At this time, the oxide layer 125 in the first embodiment includes only the opening 125T formed in a region vertically overlapping with the through hole 110T of the insulating layer 110 .

[0164] In contrast, the oxide layer 125 a of the circuit board of the third modification includes the first opening 125T1 and the second opening 125T2 .

[0165] The first opening 125T1 of the oxide layer 125a is formed in a region vertically overlapping with the through hole 110T. The first opening 125T1 corresponds to the opening 125T of the previous embodiment.

[0166] In addition, the second opening 125T2 of the oxide layer 125a is formed in the oxide layer 125a in the region between the plurality of electrode patterns of the circuit pattern layer. For example, in the third modification, in the process of forming the plurality of electrode patterns of the circuit pattern layer, the oxide layer 125a is removed together with the first metal layer 120 and the second metal layer 130. Therefore, the oxide layer 125a also includes the second opening 125T2 between the plurality of electrode patterns.

[0167] Figure 7 It is shown Figure 2 FIG. 4 is a diagram of a fourth variation of a circuit board.

[0168] Reference Figure 7 , the circuit board includes Figure 2 The insulating layer 110, the first metal layer 120 and the second metal layer 130 corresponding to the circuit board. In addition, an oxide layer 125 is formed on the lower surface of the first metal layer 120.

[0169] At this time, the circuit board of the fourth modification includes a first adhesive layer 140 disposed between the oxide layer 125 of the first metal layer 120 and the insulating layer 110 .

[0170] The first adhesive layer 140 may be a bonding sheet. The first adhesive layer 140 may be an epoxy resin-based bonding sheet, but is not limited thereto.

[0171] The first adhesive layer 140 is disposed between the oxide layer 125 of the first metal layer 120 and the insulating layer 110. Therefore, in the fourth modification, the adhesive force between the circuit pattern layer and the insulating layer 110 can be further improved.

[0172] The first adhesive layer 140 may have the same plane area as the insulating layer 110. For example, the first adhesive layer 140 may include an open area 140T corresponding to the through hole 110T of the insulating layer 110.

[0173] In the fourth modification, the bonding force between the insulating layer 110 and the circuit pattern layer can be further improved by disposing the first adhesive layer 140 between the oxide layer 125 of the first metal layer 120 and the insulating layer 110. Therefore, the embodiment can prevent the circuit pattern layer from being peeled off from the insulating layer 110, thereby further improving the electrical reliability of the circuit pattern layer.

[0174] Figure 8 is a diagram showing a chip package according to a first embodiment. At this time, the chip package of the first embodiment may include Figure 7 However, the embodiment is not limited thereto. For example, the chip package of the first embodiment may include Figure 7 A circuit board of another embodiment other than the circuit board of FIG.

[0175] The chip package of the first embodiment includes a surface finish layer 150. The surface finish layer 150 is formed in a region vertically overlapping the through hole 110T of the insulating layer 110 and the opening 125T of the oxide layer 125, and is formed on a lower surface of the circuit pattern layer.

[0176] The surface treatment layer 150 is formed on the junction of the circuit pattern layer. Preferably, the surface treatment layer 150 is formed on the lower surface of the first metal layer 120 vertically overlapping the through hole 110T and the opening 125T. In this case, when the recess 120S penetrates the first metal layer 120, the lower surface of the second metal layer 130, rather than the lower surface of the first metal layer 120, can be used as the junction of the circuit pattern layer. Therefore, the surface treatment layer 150 can also be omitted or removed.

[0177] On the other hand, when the surface treatment layer 150 is formed on the joint, the surface treatment layer 150 includes a metal having a line bonding property above a certain level. To this end, the surface treatment layer 150 includes a plurality of surface layers. For example, the surface treatment layer 150 includes a first surface layer including nickel. In addition, the surface treatment layer 150 includes a second surface treatment layer disposed below the first surface layer and including gold. The thickness of the first surface layer may be in the range of 2 μm to 3 μm. If the thickness of the first surface layer is less than 2 μm, the bonding reliability between the first metal layer 120 and the second surface layer may be reduced. In addition, if the thickness of the first surface layer exceeds 3 μm, the manufacturing cost may increase. On the other hand, the thickness of the second surface layer may be in the range of 0.2 μm to 0.5 μm. If the thickness of the second surface layer is less than 0.2 μm, the line bonding property may be reduced. If the thickness of the second surface layer exceeds 0.5 μm, the manufacturing cost may increase.

[0178] The chip package includes a second adhesive layer 160 disposed on the lower surface of the insulating layer 110 of the circuit board. The second adhesive layer 160 is used to bond the IC chip 170 to the lower surface of the insulating layer 110. The second adhesive layer 160 can be epoxy resin, thermosetting adhesive, ultraviolet adhesive, but is not limited thereto.

[0179] The IC chip 170 is attached to the second adhesive layer 160. The IC chip 170 includes a terminal 180. In addition, the terminal 180 of the IC chip 170 is electrically connected to the junction of the circuit pattern layer (specifically, the surface treatment layer 150) through a connecting member 190 such as a wire. Specifically, one end of the connecting member 190 is connected to the terminal 180 of the IC chip 170, and the other end of the connecting member 190 is connected to the lower surface of the surface treatment layer 150.

[0180] On the other hand, the chip package includes a molding layer. The molding layer may be EMC (Epoxy Molding Compound), but is not limited thereto. The molding layer is disposed on the lower surface of the insulating layer 110 . The molding layer molds the IC chip 170 and the connection member 190 .

[0181] Fig. 9 is a diagram showing a circuit board according to a second embodiment.

[0182] Hereinafter, a circuit board according to a second embodiment will be described.

[0183] At this time, the circuit board of the first embodiment includes an insulating layer 110. The insulating layer 110 is an insulating layer of an organic material.

[0184] The difference is that the insulating layer 110 included in the circuit board of the first embodiment is removed from the circuit board of the second embodiment.

[0185] Reference Fig. 9 The circuit board includes a first metal layer 220 and a second metal layer 230 disposed on the first metal layer 220 .

[0186] At this time, the first metal layer 220 of the second embodiment corresponds to the first metal layer 120 of the first embodiment, and furthermore, the second metal layer 230 of the second embodiment corresponds to the second metal layer 130 of the first embodiment.

[0187] However, the circuit board of the second embodiment has a structure in which the insulating layer 110 is removed from the circuit board of the first embodiment. Therefore, the first metal layer 220 and the second metal layer 230 of the circuit board of the second embodiment have different thicknesses from those of the first embodiment.

[0188] Specifically, the insulating layer of the circuit board of the second embodiment includes only the oxide layer 225 formed by oxidizing a portion of the first metal layer 220. That is, in the second embodiment, the oxide layer 225 is made to perform the function of the insulating layer 110 of the circuit board of the first embodiment.

[0189] That is, the insulating layer of the circuit board of the second embodiment is an oxide layer 225 formed by oxidizing a portion of the first metal layer 220. In addition, the second embodiment further reduces the thickness of the product compared to the circuit board of the first embodiment by using the oxide layer 225 to perform the function of the insulating layer.

[0190] In addition, when the circuit board of the second embodiment has the same thickness as the circuit board of the first embodiment, the thickness of the second metal layer 230 can be increased compared with the first embodiment. At this time, the second metal layer 230 is a rolled alloy. At this time, when the rolled alloy is manufactured to a thickness of less than 100 μm, an additional rolling process is required, which increases the manufacturing cost. On the contrary, the circuit board of the second embodiment can omit the additional rolling process, thereby simplifying the manufacturing process and reducing the manufacturing cost. In addition, the circuit board of the second embodiment can increase the thickness of the second metal layer while maintaining the same thickness as the first embodiment, thereby improving the overall bending characteristics of the circuit board.

[0191] The thickness of the first metal layer 220 is in the range of 7 μm to 15 μm. If the thickness of the first metal layer 220 is less than 7 μm, it is difficult to form an oxide layer 225 having a certain thickness or more on the lower surface of the first metal layer 220, thereby reducing the insulation characteristics of the circuit board. In addition, if the thickness of the first metal layer 220 exceeds 5 μm, the total thickness of the circuit board increases.

[0192] The oxide layer 225 in the first metal layer 220 satisfies a thickness in the range of 3 μm to 5 μm. If the thickness of the oxide layer 225 in the first metal layer 220 is less than 3 μm, the insulation property is reduced and the electrical reliability of the circuit board is reduced. In addition, if the thickness of the oxide layer 225 exceeds 5 μm, a fracture problem may occur due to a reduction in the strength of the oxide layer 225.

[0193] The oxide layer 225 includes an opening 225T. The opening 225T is formed corresponding to a region serving as a bonding portion on the lower surface of the first metal layer 220. The opening 225T is formed by removing a portion of the oxide layer 225 formed on the lower surface of the first metal layer 220.

[0194] The thickness of the second metal layer 230 is in the range of 100 μm to 200 μm. If the thickness of the second metal layer 230 is less than 100 μm, the warpage characteristics of the circuit board are deteriorated. In addition, if the thickness of the second metal layer 230 is less than 100 μm, an additional process is required in the process of manufacturing the second metal layer 230 by rolling. If the thickness of the second metal layer 230 exceeds 200 μm, the total thickness of the circuit board increases.

[0195] Fig.10 It is shown Fig. 9 FIG. 2 is a diagram of a modified example of the circuit board of the second embodiment.

[0196] Reference Fig.10 , the circuit board of the modified example of the second embodiment includes a recessed portion 220S formed in a region vertically overlapping with the opening 225T of the oxide layer 225 in the lower surface of the first metal layer 220 .

[0197] The concave portion 220S has a shape that is concave from the lower surface toward the upper surface of the first metal layer 220 .

[0198] The recessed portion 220S is formed to correspond to the opening 225T of the oxide layer 225 .

[0199] In addition, the recessed portion 220S has a function of completely removing the oxide layer 225 remaining on the lower surface of the first metal layer 220 serving as a bonding portion.

[0200] At this time, the recess 220S in another modification example may have a structure penetrating the first metal layer 220 .

[0201] Fig.11 is a diagram showing a chip package according to a second embodiment.

[0202] Reference Fig.11 , the chip package of the second embodiment may include Fig. 9 or Fig.10 circuit board.

[0203] The chip package of the second embodiment includes a surface treatment layer 250. The surface treatment layer 250 is formed on the lower surface of the first metal layer 220 vertically overlapping the opening 225T.

[0204] For example, the surface treatment layer 250 is disposed in the concave portion 220S of the first metal layer 220. The surface treatment layer 250 includes a first surface layer including nickel and a second surface layer including gold.

[0205] The chip package includes an adhesive layer 260 disposed on a lower surface of an oxide layer 225 of a circuit board.

[0206] The IC chip 270 is attached to the adhesive layer 260. The IC chip 270 includes a terminal 280. In addition, the terminal 280 of the IC chip 270 is electrically connected to a bonding portion of the circuit pattern layer (specifically, the surface treatment layer 250) through a connection member 290 such as a wire.

[0207] In another aspect, a chip package includes a molding layer.

[0208] In the second embodiment, the insulating function of the circuit board is achieved only by using the oxide layer formed on the lower surface of the first metal layer.

[0209] The circuit board of the embodiment includes an insulating layer and a circuit pattern layer arranged on the insulating layer. The circuit pattern layer includes a first metal layer and a second metal layer. In addition, the second metal layer is a rolled alloy layer, and the first metal layer is a metal layer formed on one surface of the rolled alloy layer. At this time, the oxide layer is formed by oxidizing the surface of the first metal layer, and the oxide layer is formed at the interface between the first metal layer and the insulating layer. At this time, the oxide layer has a needle-like structure, and the bonding force between the first metal layer and the insulating layer can be improved.

[0210] Therefore, the embodiment can solve the reliability problem of the circuit pattern layer including the first metal layer peeled from the insulating layer by improving the adhesive force between the insulating layer and the first metal layer.

[0211] Furthermore, embodiments may further improve the insulation characteristics of the circuit board by using an oxide layer disposed between the first metal layer and the insulation layer.

[0212] On the other hand, the embodiment allows the use of an alloy including nickel (Ni)-chromium (Cr)-iron (Fe) and at least one metal selected from the group consisting of silver (Ag), silicon (Si) and alloys thereof to form the second metal layer of the circuit pattern layer. Therefore, the second metal layer in the embodiment can have a wear resistance, corrosion resistance, oxidation resistance and hardness above a specific level. Thus, the embodiment can omit or remove the surface treatment layer that must be formed on the contact portion of the circuit pattern layer, thereby simplifying the manufacturing process of the circuit board and reducing manufacturing costs.

[0213] On the other hand, the first metal layer of the embodiment includes a recessed portion formed in a region vertically overlapping with the through hole of the insulating layer. In addition, the recessed portion can solve the electrical reliability problem caused by the oxide layer remaining on the joint of the circuit pattern layer. Therefore, the embodiment can improve the electrical reliability of the circuit board and the chip package, and further improve the product reliability.

[0214] In addition, the recessed portion of the first metal layer may have a structure that penetrates the first metal layer. Therefore, the lower surface of the second metal layer vertically overlapping the recessed portion of the first metal layer can be used as a bonding portion of the circuit pattern layer. At this time, the second metal layer of the circuit pattern layer in the embodiment may have a line bonding property above a specific level. Thus, the embodiment can not only omit or remove the surface treatment layer that must be formed on the contact portion of the circuit pattern layer, but also omit or remove the surface treatment layer that must be formed on the bonding portion of the circuit pattern layer. Thus, the embodiment can further simplify the manufacturing process of the circuit board and correspondingly further reduce the manufacturing cost.

[0215] In addition, the embodiment may form the insulating layer using only the oxide layer formed on the lower surface of the first metal layer. That is, the embodiment allows the metal oxide layer to be used as the insulating layer while removing the insulating layer of the organic material.

[0216] That is, the insulating layer of the circuit board of the embodiment can be formed only by the oxide layer formed on the lower surface of the first metal layer. Therefore, the embodiment can further reduce the thickness of the circuit board by using the oxide layer to perform the function of the insulating layer.

[0217] In addition, the embodiment can increase the thickness of the second metal layer of the circuit pattern layer by the thickness of the insulating layer of the organic material by removing the insulating layer of the organic material. At this time, the second metal layer is a rolled alloy layer. At this time, when the rolled alloy layer is manufactured to a thickness of less than 100 μm, an additional rolling process is required, thereby increasing the manufacturing cost. Therefore, the embodiment can omit the additional rolling process for reducing the thickness of the rolled alloy layer without increasing the thickness of the product. Thus, the embodiment can simplify the manufacturing process of the circuit board, thereby reducing the manufacturing cost. Further, the embodiment can improve the overall bending characteristics of the circuit board by increasing the thickness of the second metal layer.

[0218] The features, structures and effects described in the above embodiments are included in at least one embodiment, but are not limited to one embodiment. In addition, a person skilled in the art in the field to which the embodiments belong may even combine or modify the features, structures and effects shown in the various embodiments based on other embodiments. Therefore, it should be understood that the contents related to such combinations and such modifications are included in the scope of the embodiments.

[0219] The above description focuses on the embodiment, but this is only illustrative and does not limit the embodiment. It can be understood by those skilled in the art that various modifications and applications not shown above can be made without departing from the essential features of the present embodiment. For example, the various components specifically indicated in the embodiment can be modified and implemented. In addition, the differences associated with such changes and applications are interpreted as being included within the scope of the embodiments defined in the appended claims.

Claims

1. A circuit board, comprising: A first metal layer; as well as a second metal layer, the second metal layer being disposed on the first metal layer, wherein the first metal layer includes an oxide layer formed by oxidizing a region at a predetermined depth from a lower surface of the first metal layer, wherein the first metal layer and the second metal layer include a plurality of electrode patterns disposed on the oxide layer and spaced apart from each other, and The oxide layer insulates the plurality of electrode patterns.

2. The circuit board according to claim 1, further comprising: an organic layer disposed below the lower surface of the oxide layer, and The organic layer and the oxide layer together serve as an insulating layer for insulating the plurality of electrode patterns.

3. The circuit board according to claim 1 or 2, wherein: The second metal layer is an alloy layer including nickel (Ni) and iron (Fe), and The first metal layer is a metal layer electroplated or deposited below the lower surface of the second metal layer.

4. The circuit board according to claim 3, wherein: The second metal layer comprises: a first metal, wherein the content of the first metal is in the range of 60 wt % to 80 wt %; a second metal, wherein the content of the second metal is in the range of 10 wt % to 22 wt %; A third metal, wherein the content of the third metal is in the range of 3 wt % to 20 wt %; and a fourth metal, wherein the content of the fourth metal is in the range of 3 wt % to 10 wt %, Wherein, the first metal comprises one of nickel (Ni) and iron (Fe), wherein the second metal comprises chromium (Cr), wherein the third metal comprises one of nickel (Ni) and iron (Fe) different from the first metal, Wherein, the fourth metal includes one of silver (Ag), silicon (Si) and silver (Ag)-silicon (Si) alloy.

5. The circuit board according to claim 4, wherein: The first metal layer includes copper (Cu).

6. The circuit board according to claim 1, wherein: The total thickness of the first metal layer including the oxide layer is in the range of 7 μm to 15 μm, Wherein, the thickness of the oxide layer in the first metal layer is in the range of 3 μm to 5 μm, and Wherein, the thickness of the second metal layer is in the range of 100 μm to 200 μm.

7. The circuit board according to claim 2, wherein: The total thickness of the first metal layer including the oxide layer is in the range of 2 μm to 10 μm, Wherein, the thickness of the oxide layer in the first metal layer is in the range of 0.2 μm to 5 μm, and Wherein, the thickness of the second metal layer is in the range of 20 μm to 50 μm.

8. The circuit board according to claim 1 or 2, wherein: The oxide layer comprises at least one opening, The first metal layer includes a first region vertically overlapping the opening and a second region other than the first region. A recess is formed in the first region of the first metal layer, the recess is connected to the opening, and Wherein, a thickness of the first region of the first metal layer is smaller than a thickness of the second region of the first metal layer.

9. The circuit board according to claim 8, wherein: The second metal layer includes a third region vertically overlapping the opening and the recess and a fourth region other than the third region, wherein the recess penetrates the upper surface and the lower surface of the first metal layer, and The lower surface of the third region of the second metal layer is exposed without contacting the first metal layer and the oxide layer.

10. The circuit board according to claim 2, further comprising: a first adhesive layer, the first adhesive layer being disposed between the oxide layer and the organic layer, Wherein, the organic layer comprises at least one through hole, and Wherein, the first adhesive layer includes an opening area vertically overlapping with the through hole.

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