Adapter plate structure and preparation method thereof

Abstract

The invention relates to an adapter plate structure and a preparation method thereof. The adapter plate structure comprises a first adapter plate and a second adapter plate, wherein the first adapter plate comprises a first substrate and a plurality of first silicon through holes penetrating through the first substrate; the interconnection layer is located on the surface of one side of the first adapter plate, the interconnection layer comprises an RDL layer and a passivation layer wrapping the RDL layer, and the RDL layer is connected with the first through silicon via; the second adapter plate is located on the surface of the side, opposite to the second adapter plate, of the first adapter plate, and the second adapter plate comprises a second substrate and a plurality of second silicon through holes penetrating through the second substrate; the DTC chips are embedded into the surface of one side, facing the first adapter plate, of the second adapter plate and are connected with part of the first through silicon vias; and the remaining first through silicon vias are connected with the second through silicon vias. The adapter plate structure provided by the invention can be connected with more external chips, so that the area of a semiconductor structure is reduced, the integration of the semiconductor structure is improved, the current transmission power consumption can be reduced, the capacitance of a silicon capacitor is increased, and the performance and the working stability of the semiconductor structure are improved.

Description

Technical Field

[0001] The present invention relates to the technical field of adapter plate structures, and in particular to an adapter plate structure and a preparation method thereof. Background Art

[0002] Integrated circuits are widely used in the electronics industry to provide electronic devices such as smart phones, computers, etc. Integrated circuits (ICs) include many semiconductor devices, such as transistors, capacitors, etc., which are interconnected by wiring on a semiconductor substrate. There is an increasing need for smaller and faster ICs to support a greater number of complex functions for electronic devices. Traditional organic substrates, ceramic substrates, etc. cannot meet the requirements of small line width, high wiring density, and high I / O density. Adapters (especially silicon-based adapters) have become the best choice for packaging substrates. The adapter board can be set between the components and the circuit board, with metal redistribution (RDL) distributed on the upper and lower surfaces. After packaging, the components are generally interconnected to the adapter board by flip-chip bonding, and the adapter board is interconnected to the circuit board (PCB) below through silicon vias (TSV) or ball grid arrays (BGA) to achieve board-level interconnection. As an intermediary bridge between components and circuit boards, the adapter board can realize the interconnection between multiple chips through RDL, and can also realize the interconnection between chip components and circuit boards.

[0003] In the existing packaging technology, as the number of external chips that need to be connected gradually increases, the solution of directly using an adapter board to connect external chips and semiconductor passive devices (such as embedded deep trench capacitors DTC) will result in a larger area of ​​the semiconductor structure, higher current transmission power consumption, lower capacitance of the silicon capacitor, and poor performance and working stability of the semiconductor structure. At the same time, the number of chips connected by a single-layer adapter board is limited, which will also increase the area of ​​the semiconductor structure, resulting in lower integration of the semiconductor structure.

[0004] Therefore, a solution is needed that can integrate semiconductor passive devices inside the adapter board and connect as many external chips as possible, reduce the area of ​​the semiconductor structure, improve the integration of the semiconductor structure, reduce current transmission power consumption, increase the capacitance of silicon capacitors, and improve the performance and working stability of the semiconductor structure. Summary of the invention

[0005] Therefore, the present invention provides an adapter plate structure and a preparation method thereof to solve the problems that the semiconductor structure packaged using the existing adapter plate structure has a large area, low integration, high current transmission power consumption, low capacitance of the silicon capacitor, and poor performance and working stability of the semiconductor structure.

[0006] The present invention provides a transfer plate structure, comprising:

[0007] A first adapter plate, wherein the first adapter plate includes a first substrate and a plurality of first through silicon vias penetrating the first substrate;

[0008] An interconnection layer, located on one side surface of the first adapter plate, the interconnection layer comprising an RDL layer and a passivation layer covering the RDL layer, the RDL layer being connected to the first through silicon via;

[0009] A second adapter plate, located on a surface of the first adapter plate facing away from the interconnection layer, the second adapter plate comprising a second substrate and a plurality of second through silicon vias penetrating the second substrate;

[0010] A plurality of DTC chips are embedded in a surface of the second adapter board facing the first adapter board and connected to a portion of the first through silicon vias; and the remaining first through silicon vias are connected to the second through silicon vias.

[0011] Optionally, the first adapter plate and the second adapter plate are connected together by hybrid bonding;

[0012] The DTC chip is connected to a portion of the first through silicon vias through hybrid bonding; and the second through silicon vias are connected to the remaining first through silicon vias through hybrid bonding.

[0013] Optionally, the DTC chip is connected to some of the first through silicon vias in a one-to-one correspondence; and the remaining first through silicon vias are connected to the second through silicon vias in a one-to-one correspondence.

[0014] Optionally, a surface of the second adapter plate on one side facing the first adapter plate has a plurality of grooves, and the DTC chips are embedded in the grooves one by one.

[0015] Optionally, the material of the passivation layer is polyimide;

[0016] The filling material of the first through silicon via is a conductive material;

[0017] The filling material of the second through silicon via is a conductive material.

[0018] Optionally, it further includes: a UBM metal layer, located on a surface of the interconnect layer facing away from the first adapter plate, the UBM metal layer being connected to the RDL layer; the RDL layer being suitable for connecting an external chip through the UBM metal layer; the external chip being suitable for connecting to the UBM metal layer through flip-chip bonding;

[0019] A plurality of solder balls are located on a surface of the second adapter board facing away from the first adapter board, the solder balls are connected to the second through silicon vias in a one-to-one correspondence; and the solder balls are suitable for connecting to an external substrate.

[0020] The present invention also provides a method for preparing an adapter plate structure, which is characterized by comprising the following steps:

[0021] Providing a first adapter plate, wherein the first adapter plate includes a first substrate and a plurality of first through silicon vias penetrating the first substrate;

[0022] forming an interconnection layer on a surface of one side of the first adapter plate, the interconnection layer comprising an RDL layer and a passivation layer covering the RDL layer, the RDL layer being connected to the first through silicon via;

[0023] Providing a second adapter plate, wherein the second adapter plate includes a second substrate and a plurality of second through silicon vias penetrating the second substrate;

[0024] Embedding a plurality of DTC chips on one side of the second adapter board;

[0025] The first adapter board is connected to the second adapter board, so that the DTC chip is located on the side of the second adapter board facing the first adapter board and is connected to part of the first through silicon vias; the remaining first through silicon vias are connected to the second through silicon vias.

[0026] Optionally, in the step of connecting the first adapter board to the second adapter board,

[0027] The first adapter plate and the second adapter plate are connected together by hybrid bonding;

[0028] The DTC chip is connected to a part of the first through silicon vias in a one-to-one correspondence through hybrid bonding; and the second through silicon vias are connected to the remaining first through silicon vias in a one-to-one correspondence through hybrid bonding.

[0029] Optionally, in the step of embedding a plurality of DTC chips on one side of the second adapter board,

[0030] A plurality of grooves are formed on a surface of the second adapter plate on one side facing the first adapter plate; and the DTC chips are embedded in the grooves one by one.

[0031] Optionally, after the step of forming an interconnection layer on the surface of one side of the first adapter board, the method further includes:

[0032] Forming a UBM metal layer on a surface of the interconnect layer facing away from the first adapter plate, wherein the UBM metal layer is connected to the RDL layer;

[0033] After the step of connecting the first adapter board to the second adapter board, the method further includes:

[0034] A plurality of solder balls are formed on a surface of the second adapter board on one side facing away from the first adapter board, and the solder balls are connected to the second through silicon vias in a one-to-one correspondence.

[0035] The technical solution of the present invention has the following advantages:

[0036] (1) The adapter board structure provided by the present invention integrates the semiconductor passive device DTC inside the adapter board and sets a double-layer adapter board. On the one hand, it can connect more external chips, thereby reducing the area of ​​the semiconductor structure and improving the integration of the semiconductor structure. On the other hand, it can reduce the current transmission power consumption, increase the capacitance of the silicon capacitor, and improve the performance and working stability of the semiconductor structure.

[0037] (2) The adapter plate structure provided by the present invention connects the first adapter plate and the second adapter plate together through a hybrid bonding technology, combines the silicon via filling materials and DTC chips in different adapter plates, and the silicon via filling materials of different adapter plates together, thereby achieving a firm connection between the first adapter plate and the second adapter plate.

[0038] The method for preparing the adapter plate structure provided by the present invention can prepare the adapter plate structure provided by the present invention. The adapter plate structure provided by the present invention integrates the semiconductor passive device DTC inside the adapter plate and sets a double-layer adapter plate. On the one hand, more external chips can be connected in parallel, thereby reducing the area of ​​the semiconductor structure and improving the integration of the semiconductor structure. On the other hand, the power consumption of current transmission can be reduced, the capacitance of the silicon capacitor can be increased, and the performance and working stability of the semiconductor structure can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] In order to more clearly illustrate the specific implementation methods of the present invention or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0040] Figure 1 It is a structural schematic diagram of an adapter plate structure according to an embodiment of the present invention;

[0041] Figure 2 A schematic flow chart of a method for preparing a transfer plate structure according to an embodiment of the present invention;

[0042] Figure 3 A schematic diagram of a specific method for preparing a transfer plate structure according to an embodiment of the present invention;

[0043] Figure 4-Figure 8 The present invention is a schematic structural diagram of various processes of a specific method for preparing a transfer plate structure according to an embodiment of the present invention.

[0044] Description of reference numerals:

[0045] 1-first transfer board; 2-interconnection layer; 3-second transfer board; 4-multiple DTC chips; 11-first substrate; 12-first through silicon via; 21-RDL layer; 22-passivation layer; 31-second substrate; 32-second through silicon via; 5-UBM metal layer; 6-solder ball. DETAILED DESCRIPTION

[0046] In order to solve the problems that the semiconductor structure packaged by the existing adapter plate structure has a large area, low integration, high current transmission power consumption, low capacitance of silicon capacitors, and poor performance and working stability of the semiconductor structure, the present invention provides an adapter plate structure, including: a first adapter plate, the first adapter plate including a first substrate and a plurality of first silicon through vias penetrating the first substrate; an interconnection layer, located on a side surface of the first adapter plate, the interconnection layer including an RDL layer and a passivation layer covering the RDL layer, the RDL layer being connected to the first silicon through vias; a second adapter plate, located on a side surface of the first adapter plate facing away from the second adapter plate, the second adapter plate including a second substrate and a plurality of second silicon through vias penetrating the second substrate; a plurality of DTC chips, embedded in a side surface of the second adapter plate facing the first adapter plate, and connected to part of the first silicon through vias; the remaining first silicon through vias are connected to the second silicon through vias.

[0047] The present invention also provides a method for preparing an adapter board structure, comprising the following steps: providing a first adapter board, the first adapter board comprising a first substrate and a plurality of first silicon through vias penetrating the first substrate; forming an interconnection layer on a surface of one side of the first adapter board, the interconnection layer comprising an RDL layer and a passivation layer covering the RDL layer, the RDL layer being connected to the first silicon through vias; providing a second adapter board, the second adapter board comprising a second substrate and a plurality of second silicon through vias penetrating the second substrate; embedding a plurality of DTC chips on one side of the second adapter board; connecting the first adapter board to the second adapter board so that the DTC chip is located on a side of the second adapter board facing the first adapter board and is connected to a portion of the first silicon through vias; the remaining first silicon through vias are connected to the second silicon through vias.

[0048] The technical solution of the present invention will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments in the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention. In the description of the present invention, it should be noted that the terms "first", "second" and "third" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance.

[0049] Example 1

[0050] refer to Figure 1 , this embodiment provides a transfer plate structure, including:

[0051] A first adapter board 1, wherein the first adapter board 1 comprises a first substrate 11 and a plurality of first through silicon vias 12 penetrating the first substrate 11;

[0052] An interconnection layer 2, located on one side surface of the first adapter board 1, the interconnection layer 2 comprises an RDL layer 21 and a passivation layer 22 covering the RDL layer 21, the RDL layer 21 is connected to the first through silicon via 12;

[0053] A second adapter plate 3, located on a surface of the first adapter plate 1 facing away from the interconnection layer 2, the second adapter plate 3 comprising a second substrate 31 and a plurality of second through silicon vias 32 penetrating the second substrate 31;

[0054] A plurality of DTC chips 4 are embedded in a surface of the second adapter board 3 facing the first adapter board 1 , and are connected to a portion of the first TSVs 12 ; the remaining first TSVs 12 are connected to the second TSVs 32 .

[0055] The adapter board structure provided in this embodiment integrates the semiconductor passive device DTC inside the adapter board and sets up a double-layer adapter board. On the one hand, it can connect more external chips, thereby reducing the area of ​​the semiconductor structure and improving the integration of the semiconductor structure. On the other hand, it can reduce the current transmission power consumption, increase the capacitance of the silicon capacitor, and improve the performance and working stability of the semiconductor structure.

[0056] Further, in this embodiment, the first adapter plate 1 and the second adapter plate 3 are connected together by hybrid bonding;

[0057] The DTC chip 4 is connected to a portion of the first through silicon vias 12 through hybrid bonding; and the second through silicon vias 32 are connected to the remaining first through silicon vias 12 through hybrid bonding.

[0058] In a specific implementation, SiO is provided on the inner wall of the first adapter plate 1 and the inner wall of the first silicon through hole 12, the surface of the second adapter plate 3 and the inner wall of the second silicon through hole 32. 2 Therefore, the metal layer (such as Cu) exposed on the surface of the DTC chip 4, the metal (such as Cu) filled in the first silicon through hole 12, and the SiO 2 And the SiO on the surface of the two adapter plates 2Hybrid bonding is performed to achieve the connection between the DTC chip 4 and part of the first through silicon via 12; and the metal (such as Cu) filled in the first through silicon via 12, the metal (such as Cu) filled in the second through silicon via 32, and the remaining SiO2 on the inner wall of the first through silicon via 12 are used to connect the DTC chip 4 to the first through silicon via 12. 2 , the SiO 2 And the SiO on the surface of the two adapter plates 2 Hybrid bonding is performed to connect the second TSV 32 with the remaining first TSVs 12 .

[0059] In this embodiment, the first adapter board and the second adapter board are connected together by hybrid bonding technology, and the silicon via filling materials and DTC chips in different adapter boards and the silicon via filling materials of different adapter boards are combined together up and down to achieve a firm connection between the first adapter board and the second adapter board.

[0060] Furthermore, in this embodiment, the DTC chips 4 are connected to some of the first TSVs 12 in a one-to-one correspondence; and the remaining first TSVs 12 are connected to the second TSVs 32 in a one-to-one correspondence.

[0061] Furthermore, in this embodiment, a surface of the second adapter board 3 facing the first adapter board 1 has a plurality of grooves, and the DTC chips 4 are embedded in the grooves one by one.

[0062] Furthermore, in this embodiment, the material of the passivation layer 22 is polyimide;

[0063] The filling material of the first through silicon via 12 is a conductive material, such as copper, tungsten, etc.;

[0064] The filling material of the second TSV 32 is a conductive material, such as copper, tungsten, etc.

[0065] Furthermore, in this embodiment, it also includes: a UBM metal layer 5, located on a surface of the interconnect layer 2 facing away from the first adapter board 1, the UBM metal layer 5 is connected to the RDL layer 21; the RDL layer 21 is suitable for connecting an external chip through the UBM metal layer 5; the external chip is suitable for connecting to the UBM metal layer 5 through flip-chip bonding;

[0066] A plurality of solder balls 6 are located on a surface of the second adapter board 3 on one side facing away from the first adapter board 1 , and the solder balls 6 are connected to the second through silicon vias 32 in a one-to-one correspondence; the solder balls 6 are suitable for connecting to an external substrate.

[0067] Example 2

[0068] refer to Figure 2 The present invention also provides a method for preparing a transfer plate structure, which is used to prepare the transfer plate structure of the above embodiment 1. The method comprises the following steps:

[0069] S201, providing a first adapter plate, wherein the first adapter plate includes a first substrate and a plurality of first through silicon vias penetrating the first substrate;

[0070] S202, forming an interconnection layer on a surface of one side of the first adapter board, the interconnection layer comprising an RDL layer and a passivation layer covering the RDL layer, the RDL layer being connected to the first through silicon via;

[0071] S203, providing a second adapter plate, wherein the second adapter plate includes a second substrate and a plurality of second through silicon vias penetrating the second substrate;

[0072] S204, embedding a plurality of DTC chips on one side of the second adapter board;

[0073] S205, connecting the first adapter board to the second adapter board, so that the DTC chip is located on the side of the second adapter board facing the first adapter board, and is connected to part of the first through silicon vias; the remaining first through silicon vias are connected to the second through silicon vias.

[0074] The adapter board structure provided in this embodiment integrates the semiconductor passive device DTC inside the adapter board and sets up a double-layer adapter board. On the one hand, it can connect more external chips, thereby reducing the area of ​​the semiconductor structure and improving the integration of the semiconductor structure. On the other hand, it can reduce the current transmission power consumption, increase the capacitance of the silicon capacitor, and improve the performance and working stability of the semiconductor structure.

[0075] Further, in some embodiments, in the step of connecting the first adapter board to the second adapter board,

[0076] The first adapter plate and the second adapter plate are connected together by hybrid bonding;

[0077] The DTC chip is connected to a part of the first through silicon vias in a one-to-one correspondence through hybrid bonding, and the second through silicon vias are connected to the remaining first through silicon vias in a one-to-one correspondence through hybrid bonding.

[0078] In a specific implementation, in the process of preparing the first adapter plate and the second adapter plate, before filling the first through silicon via and the second through silicon via, SiO is deposited on the inner wall of the first adapter plate and the inner wall of the first through silicon via, the surface of the second adapter plate and the inner wall of the second through silicon via. 2 Therefore, in this embodiment, the metal layer (such as Cu) exposed on the surface of the DTC chip, the metal (such as Cu) filled in the first silicon through hole, and the SiO2 on the inner wall of the first silicon through hole are used. 2 And the SiO on the surface of the adapter 2Hybrid bonding is performed to achieve the connection between the DTC chip and part of the first through silicon via; and the metal (such as Cu) filled in the first through silicon via, the metal (such as Cu) filled in the second through silicon via, and the SiO 2 , SiO on the inner wall of the second TSV 2 And the SiO on the surface of the adapter 2 Hybrid bonding is performed to connect the second through silicon via with the remaining first through silicon vias.

[0079] Furthermore, in some embodiments, in the step of embedding a plurality of DTC chips on one side of the second adapter board,

[0080] A plurality of grooves are formed on a surface of the second adapter plate on one side facing the first adapter plate; and the DTC chips are embedded in the grooves one by one.

[0081] In a specific implementation, a second adapter plate with a second through silicon via can be formed, and then a groove can be formed on the second adapter plate; or a groove can be first formed on the second substrate and the DTC chip can be embedded therein, and then the second through silicon via can be formed.

[0082] In one example, a plurality of second through silicon vias penetrating the second substrate are first formed on the second substrate, and then a plurality of grooves are formed between two adjacent second through silicon vias on one side of the second substrate, and finally the DTC chips are embedded in the grooves one by one.

[0083] In another example, a plurality of grooves are first formed on the second substrate, and then the DTC chips are embedded in the grooves one by one. Finally, a plurality of second through silicon vias penetrating the second substrate are formed between two adjacent grooves of the second substrate.

[0084] Furthermore, in some embodiments, after the step of forming an interconnection layer on the surface of one side of the first adapter board, the method further includes:

[0085] Forming a UBM metal layer on a surface of the interconnect layer facing away from the first adapter plate, wherein the UBM metal layer is connected to the RDL layer;

[0086] After the step of connecting the first adapter board to the second adapter board, the method further includes:

[0087] A plurality of solder balls are formed on a surface of the second adapter board on one side facing away from the first adapter board, and the solder balls are connected to the second through silicon vias in a one-to-one correspondence.

[0088] In a specific implementation, this embodiment also provides a specific method for preparing the adapter plate structure, referring to Figure 3 , including steps S301-S307:

[0089] S301, forming a plurality of first through silicon vias penetrating the first substrate on a surface of the first substrate to form a first transfer plate.

[0090] S302 , forming an interconnection layer on a surface of one side of the first adapter board, wherein the interconnection layer includes an RDL layer and a passivation layer covering the RDL layer, and the RDL layer is connected to the first through silicon via.

[0091] S303, forming a UBM metal layer on a surface of the interconnect layer facing away from the first adapter plate, wherein the UBM metal layer is connected to the RDL layer, such as Figure 4 shown.

[0092] S304, forming a plurality of grooves on the second substrate, and embedding a plurality of DTC chips into the grooves one by one. Figure 5 shown.

[0093] S305, forming a plurality of second through silicon vias penetrating the second substrate between two adjacent grooves of the second substrate to form a second adapter plate, such as Figure 6 shown.

[0094] S306, connecting the first adapter plate and the second adapter plate together through hybrid bonding; wherein the DTC chip and part of the first through silicon vias are connected in a one-to-one correspondence through hybrid bonding, and the second through silicon vias and the remaining first through silicon vias are connected in a one-to-one correspondence through hybrid bonding, such as Figure 7 shown.

[0095] S307, forming a plurality of solder balls on a surface of the second adapter board facing away from the first adapter board, wherein the solder balls are connected to the second through silicon vias in a one-to-one correspondence, such as Figure 8 shown.

[0096] Obviously, the above embodiments are merely examples for the purpose of clear explanation, and are not intended to limit the implementation methods. For those skilled in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the implementation methods here. The obvious changes or modifications derived therefrom are still within the scope of protection of the invention.

Claims

1. A transfer plate structure, characterized in that: include: A first adapter plate, wherein the first adapter plate includes a first substrate and a plurality of first through silicon vias penetrating the first substrate; An interconnection layer, located on one side surface of the first adapter plate, the interconnection layer comprising an RDL layer and a passivation layer covering the RDL layer, the RDL layer being connected to the first through silicon via; A second adapter plate, located on a surface of the first adapter plate facing away from the interconnection layer, the second adapter plate comprising a second substrate and a plurality of second through silicon vias penetrating the second substrate; A plurality of DTC chips are embedded in a surface of the second adapter board facing the first adapter board and connected to a portion of the first through silicon vias; and the remaining first through silicon vias are connected to the second through silicon vias.

2. The adapter plate structure according to claim 1, characterized in that: The first adapter plate and the second adapter plate are connected together by hybrid bonding; The DTC chip is connected to a portion of the first through silicon vias through hybrid bonding; and the second through silicon vias are connected to the remaining first through silicon vias through hybrid bonding.

3. The adapter plate structure according to claim 2, characterized in that: The DTC chips are connected to some of the first through silicon vias in a one-to-one correspondence; and the remaining first through silicon vias are connected to the second through silicon vias in a one-to-one correspondence.

4. The adapter plate structure according to claim 1, characterized in that: A surface of the second adapter plate on one side facing the first adapter plate has a plurality of grooves, and the DTC chips are embedded in the grooves one by one.

5. The adapter plate structure according to claim 1, characterized in that: The material of the passivation layer is polyimide; The filling material of the first through silicon via is a conductive material; The filling material of the second through silicon via is a conductive material.

6. The adapter plate structure according to claim 1, characterized in that: Also includes: A UBM metal layer is located on a surface of the interconnect layer facing away from the first adapter plate, and the UBM metal layer is connected to the RDL layer; The RDL layer is suitable for connecting to an external chip through the UBM metal layer; The external chip is suitable for connecting to the UBM metal layer through flip chip bonding; A plurality of solder balls are located on a surface of the second adapter board facing away from the first adapter board, the solder balls are connected to the second through silicon vias in a one-to-one correspondence; and the solder balls are suitable for connecting to an external substrate.

7. A method for preparing an adapter plate structure, characterized in that: The following steps are involved: Providing a first adapter plate, wherein the first adapter plate includes a first substrate and a plurality of first through silicon vias penetrating the first substrate; forming an interconnection layer on a surface of one side of the first adapter plate, the interconnection layer comprising an RDL layer and a passivation layer covering the RDL layer, the RDL layer being connected to the first through silicon via; Providing a second adapter plate, wherein the second adapter plate includes a second substrate and a plurality of second through silicon vias penetrating the second substrate; Embedding a plurality of DTC chips on one side of the second adapter board; The first adapter board is connected to the second adapter board, so that the DTC chip is located on the side of the second adapter board facing the first adapter board and is connected to part of the first through silicon vias; the remaining first through silicon vias are connected to the second through silicon vias.

8. The method for preparing the adapter plate structure according to claim 7, characterized in that: In the step of connecting the first adapter board to the second adapter board, The first adapter plate and the second adapter plate are connected together by hybrid bonding; The DTC chip is connected to a part of the first through silicon vias in a one-to-one correspondence through hybrid bonding; and the second through silicon vias are connected to the remaining first through silicon vias in a one-to-one correspondence through hybrid bonding.

9. The method for preparing the adapter plate structure according to claim 7, characterized in that: In the step of embedding a plurality of DTC chips on one side of the second adapter board, A plurality of grooves are formed on a surface of the second adapter plate on one side facing the first adapter plate; and the DTC chips are embedded in the grooves one by one.

10. The method for preparing the adapter plate structure according to claim 7, characterized in that: After the step of forming an interconnection layer on the surface of one side of the first adapter board, the method further includes: Forming a UBM metal layer on a surface of the interconnect layer facing away from the first adapter plate, wherein the UBM metal layer is connected to the RDL layer; After the step of connecting the first adapter board to the second adapter board, the method further includes: A plurality of solder balls are formed on a surface of the second adapter board on one side facing away from the first adapter board, and the solder balls are connected to the second through silicon vias in a one-to-one correspondence.

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