Semiconductor structure and detection method of semiconductor structure

Abstract

The embodiment of the invention relates to the field of semiconductors, and provides a semiconductor structure and a detection method of the semiconductor structure, the semiconductor structure comprises a substrate, the substrate comprises a plurality of exposure areas arranged in a splicing mode, and a splicing boundary is arranged between every two adjacent exposure areas; the adjacent exposure areas are obtained by sequentially exposing by using the same photomask in the exposure treatment process; the test element stretches across the splicing boundary, and the test element at least comprises sub-elements located on the adjacent exposure areas respectively; and under the condition that the adjacent exposure areas are aligned, the sub-elements in the test element are spliced into a continuous conductive structure. The embodiment of the invention at least can improve the yield of the semiconductor structure.

Description

Technical Field

[0001] The present disclosure belongs to the field of semiconductors, and in particular relates to a semiconductor structure and a method for detecting the semiconductor structure. Background Art

[0002] The exposure process is a very important process in the semiconductor manufacturing field. Its purpose is to transfer the geometric patterns on the photolithography mask to the substrate, and then form corresponding devices on the substrate through processes such as etching.

[0003] In order to meet the requirements of larger sizes, splicing exposure has been applied in the semiconductor field. The substrate is divided into multiple splicing exposure areas, and different exposure areas are exposed successively. Multiple exposure processes can form a complete pattern of the device.

[0004] However, during the splicing exposure, the positioning of different exposure areas may be offset, that is, adjacent exposure areas may be misaligned. However, there is currently a lack of effective means to quickly monitor the alignment of adjacent exposure areas, so it is difficult to adjust the process parameters of the exposure process in a timely manner, thereby affecting the yield of a large number of semiconductor structures. Summary of the invention

[0005] The embodiments of the present disclosure provide a semiconductor structure and a method for detecting the semiconductor structure, which are at least beneficial to improving the yield of the semiconductor structure.

[0006] According to some embodiments of the present disclosure, on the one hand, an embodiment of the present disclosure provides a semiconductor structure, wherein the semiconductor structure includes: a substrate, the substrate includes a plurality of exposure areas that are spliced ​​together, and adjacent exposure areas have a splicing boundary between them; adjacent exposure areas are exposed successively using the same mask during an exposure process; a test element spanning the splicing boundary, the test element at least including respective sub-elements located on adjacent exposure areas respectively; when adjacent exposure areas are aligned, the sub-elements in the test element are spliced ​​into a continuous conductive structure.

[0007] According to some embodiments of the present disclosure, on the other hand, the embodiments of the present disclosure further provide a detection method for a semiconductor structure, the detection method comprising: providing the aforementioned semiconductor structure as a semiconductor structure to be tested; detecting an experimental resistance, wherein the experimental resistance is the resistance of the test element in the semiconductor structure to be tested; providing a reference resistance, wherein the reference resistance is the ideal resistance of the test element when the stitching boundaries between the adjacent exposure areas it spans are fully aligned; comparing the experimental resistance with the reference resistance, and obtaining a resistance difference between the two; and determining the offset of multiple exposure areas of the semiconductor structure to be tested based on the resistance difference.

[0008] The technical solution provided by the embodiments of the present disclosure has at least the following advantages:

[0009] When adjacent exposure areas are aligned, the test element is in a continuous state. When adjacent exposure areas are not aligned, the test element is in a disconnected state or adjacent sub-elements have a large degree of misalignment. Since the test element is a conductive structure, the resistance of the test element can be tested to determine the offset of the exposure area, so as to facilitate the timely adjustment of subsequent process parameters to avoid affecting the subsequent product yield. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The accompanying drawings herein are incorporated into the specification and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification are used to explain the principles of the present disclosure. Obviously, the accompanying drawings described below are only some embodiments of the present disclosure, and for ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without creative work.

[0011] Figure 1 Top views of exposure regions of a semiconductor structure provided by an embodiment of the present disclosure are respectively shown.

[0012] Figure 2 Top views of exposure regions of another semiconductor structure provided by embodiments of the present disclosure are respectively shown.

[0013] Figure 3-Figure 8 as well as Figure 12-14 They are Figure 1 Different magnifications of the test area are shown.

[0014] Figure 9-11 for Figure 2 An enlarged view of the test area is shown.

[0015] Fig.15 for Figure 3 The test area shown is a cross-sectional view along the A-A1 direction.

[0016] Fig.16 A flow chart of a semiconductor structure testing method provided by an embodiment of the present disclosure is shown.

[0017] Fig.17 A top view of a semiconductor structure provided by an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0018] The following will describe the various embodiments of the present disclosure in detail with reference to the accompanying drawings. However, it will be appreciated by those skilled in the art that in the various embodiments of the present disclosure, many technical details are provided in order to enable the reader to better understand the embodiments of the present disclosure. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solutions claimed in the embodiments of the present disclosure can be implemented.

[0019] like Figure 1-Figure 15 As shown, an embodiment of the present disclosure provides a semiconductor structure, which includes a substrate 10 and a test element 3 on the substrate 10. The substrate 10 includes a plurality of spliced ​​exposure areas M, and there is a splicing boundary 20 between adjacent exposure areas M; the adjacent exposure areas M are exposed successively using the same mask during the exposure process. The test element 3 spans the splicing boundary 20, and the test element 3 includes at least sub-elements 31 respectively located on adjacent exposure areas M, that is, there is a sequence of exposure processes for different sub-elements 31. When adjacent exposure areas M are aligned, the sub-elements 31 in the test element 3 are spliced ​​into a continuous conductive structure.

[0020] It should be noted that the aforementioned "when adjacent exposure areas M are aligned" can be understood as the offset of adjacent exposure areas M being less than the preset range. That is to say, the initial design pattern of each test element 3 is a continuous pattern. In the actual production process, if the adjacent exposure areas M are offset to a large extent, the test element 3 actually manufactured may be in a disconnected state; if the adjacent exposure areas M are not offset, the test element 3 is in a continuous state, and the adjacent sub-elements 31 are completely aligned; if the offset of the adjacent exposure areas M is small, the test element 3 can be kept continuous as a whole, but the adjacent sub-elements 31 are slightly misaligned. Therefore, the higher the offset, the greater the resistance of the test element 3; the smaller the offset, the smaller the resistance of the test element 3. Based on this, the alignment of multiple exposure areas M can be determined by detecting the actual resistance of the test element 3. The method of testing the actual resistance is simple and rapid, and can obtain the alignment of the exposure area M in a timely manner, so as to facilitate engineers to adjust the process parameters of the subsequent manufacturing of semiconductor structures to avoid the occurrence of large quantities of unqualified products.

[0021] The semiconductor structure will be described in detail below with reference to the accompanying drawings.

[0022] Figure 1-Figure 2 Different top views of the exposure regions of the two semiconductor structures are shown respectively. Figure 1-Figure 2 Each exposure area M may include at least one test sub-area M0, the area of ​​the test sub-area M0 is smaller than the area of ​​the exposure area M, and each test sub-area M0 has a sub-element 31 (refer to Figure 3 In other words, the test sub-areas M0 on the multiple exposure areas M are spliced ​​together to form a test area M', and the sub-elements 31 on the multiple test sub-areas M0 are spliced ​​together to form a test element 3 (refer to Figure 3 In some embodiments, the test area M' may be located at a corner of the exposure area M.

[0023] Specifically, refer to Figure 1 , the four exposure areas M (four test sub-areas M0) are spliced ​​in pairs, and there are four splicing boundaries 20 in total. Figure 2 , two exposure areas M (two test sub-areas M0) are spliced ​​together, and there is a splicing boundary 20. It is worth noting that the splicing boundary 20 can be understood as the entire boundary shared by adjacent exposure areas M, rather than just the partial boundary spanned by the test element 3.

[0024] refer to Figure 3-Figure 9 , Fig.11 , the positive projection of the test element 3 on the substrate 10 is arranged in a serpentine manner (snake-shaped arrangement), so that the longer test element 3 can be arranged as much as possible in a limited area, thereby increasing its resistance, making it easier to capture the resistance change, and confirming the quality of the stitching effect based on the resistance change. The resistance change can also be understood as the difference between the measured resistance and the ideal resistance. The measured resistance varies according to different stitching effects, and the ideal resistance is the standard resistance used for reference. The ideal resistance can be understood as the resistance of the test element 3 when the stitching boundaries 20 between the adjacent exposure areas M it spans are fully aligned, that is, the resistance of the test element 3 when there is no offset in the multiple exposure areas M to which it corresponds. In other embodiments, reference Fig.10 , Figure 12-14 , the orthographic projection of the test element 3 on the substrate 10 may also be in the shape of a straight strip.

[0025] Continue to refer Figure 2-Figure 9 , Fig.11 In some embodiments, the test element 3 crosses the stitching boundary 20 multiple times, that is, there are multiple stitching sites between adjacent sub-elements 31. Compared with the test element 3 crossing the stitching boundary 20 once, crossing the stitching boundary 20 multiple times can make it easier to capture the resistance change of the test element 3. In other words, the resistance of the test resistor when crossing the stitching boundary 20 multiple times is more different from the ideal resistance, so the offset of the exposure area M corresponding to the test element 3 can be obtained more obviously and accurately.

[0026] For example, each test element 3 crosses the stitching boundary 20 at least three times to ensure a more accurate offset condition. In other embodiments, each test element 3 may also cross the stitching boundary 20 twice. In addition, to avoid the test element 3 occupying too much space on the substrate 10, the number of times the test element 3 crosses the stitching boundary 20 should not be too many. For example, each stitching boundary 20 is crossed by the test element 3 at most seven times to avoid affecting the settings of other elements.

[0027] In other embodiments, reference Fig.10 , Figure 12-14 , each test element 3 may also cross the splicing boundary 20 only once.

[0028] refer to Fig.15 , Fig.15 for Figure 3The cross-sectional view of the test area M' in the direction of A-A1 is shown. In some embodiments, the semiconductor structure further includes at least two test pads, such as a first test pad 51 and a second test pad 52, which are electrically connected to the head and tail ends of the test element 3 respectively. The probe of the resistance tester is pressed on the first test pad 51 and the second test pad 52 to obtain the resistance of the entire test element 3. In other embodiments, there may be more than two test pads, and the test pads may be connected to other positions other than the head and tail ends of the test element 3, which will be described in detail later in combination with the type of the test element 3.

[0029] Continue to refer Fig.15 , the semiconductor structure may further include a wiring layer 53, which is connected between the test pad and the test element 3, so that the position of the test pad can be flexibly adjusted to facilitate the resistance test process. It should be noted that the resistance directly measured by the resistance test instrument actually includes the resistance of the test element 3, the wiring layer 53 and the test pad. Therefore, the resistance of the wiring layer 53 and the test pad can be appropriately reduced to avoid the resistance of the two affecting the test results. For example, the head and tail ends of the test element 3 can be located in the same exposure area M, which can facilitate the setting of the position of the test pad and shorten the routing length of the wiring layer 53 to avoid the resistance of the wiring layer 53 itself affecting the test results.

[0030] In some embodiments, the materials of the test element 3, the wiring layer 53 and the test pad can be conductive materials such as copper, aluminum, titanium or tungsten. The substrate 10 may include an insulating layer, and the test element 3, the wiring layer 53 and the test pad can be arranged in the insulating layer, so as to isolate the three from other components, thereby improving the accuracy of the resistance test. The insulating layer also exposes the upper surface of the test pad so that the probe of the resistance test instrument can contact the test pad.

[0031] The quantitative relationship between the test elements 3 and the splicing boundaries 20 they span will be described in detail below.

[0032] Example 1, reference 3- Figure 6 , a test element 3 spans across multiple stitching boundaries 20 and is located on all exposure areas M that share the stitching boundaries 20. That is, when the number of stitching boundaries 20 is greater than or equal to 2, the relationship between the number of the test element 3 and the stitching boundaries 20 it spans is a one-to-many relationship.

[0033] For example, four exposure areas M are spliced ​​in pairs, and there are four splicing boundaries 20 in total. A test element 3 can span the four splicing boundaries 20 and be located on the four exposure areas M. The four exposure areas M are respectively a first exposure area M1, a second exposure area M2, a third exposure area M3, and a fourth exposure area M4.

[0034] In some embodiments, the number of crossings of the test element 3 on the multiple stitching boundaries 20 is the same, so that the overall offset of the multiple exposure areas M corresponding to the test element 3 can be more accurately obtained. In other embodiments, the number of crossings of the test element 3 on the multiple stitching boundaries 20 may also be different. For example, the difference between the number of crossings of the test element 3 on different stitching boundaries 20 does not exceed two.

[0035] Continue to refer Figure 3-Figure 5 The shape of the positive projection of the test element 3 on the substrate 10 is a spiral. The spiral test element 3 can cross the splicing boundary 20 multiple times, and the space it occupies on the substrate 10 is small, thereby providing more sufficient space for other elements.

[0036] In some embodiments, the shape of the test element 3 may be a square spiral, and the length of a square spiral is easier to calculate than that of a circular spiral, and thus it is easier to calculate the theoretical resistance of the test element 3. For example, the test element 3 includes a plurality of straight strips 32 connected in sequence, and for example, the straight strips 32 may all have a uniform width to ensure that the cross-sectional areas of the straight strips 32 at different positions are the same, thereby simplifying the calculation process of the theoretical resistance. In some embodiments, the plurality of straight strips 32 on the same exposure area M may also be arranged in parallel, which is more convenient for process manufacturing.

[0037] For example, refer to Figure 3 and Figure 5 Each straight strip portion 32 spans across a splicing boundary 20 and is located on two adjacent exposure areas M, and the two connected straight strip portions 32 can be perpendicular to each other, and the straight strip portion 32 is arranged perpendicular to the splicing boundary 20 it spans.

[0038] In other embodiments, reference Figure 4 Each straight strip portion 32 is located on an exposure area M, and the angle between the straight strip portion 32 and the splicing boundary 20 is an acute angle or an obtuse angle, for example, at least part of the angle is 45 degrees. Figure 3-Figure 5 It can be seen that when the straight strip portions 32 have the same width and the same spacing, Figure 4 The cross-sectional area of ​​the illustrated test element 3 at the splicing boundary 20 is larger, that is, the area of ​​the splicing interface between two adjacent sub-elements 31 is larger, for example, Figure 4 The cross-sectional area of ​​the test element 3 on the splicing boundary 20 is Figure 3 or Figure 5 The ratio of the cross-sectional area of ​​the test element 3 on the splicing boundary 20 is about 1.41, that is, Figure 4 The test element 3 shown has a larger process margin, which is beneficial to ensure the accuracy of obtaining the offset situation.

[0039] In some embodiments, reference Figure 3 and Figure 4 , one of the ends of the test element 3 may be located inside the pattern, and the other of the ends may be located outside the pattern. Figure 5 , both ends of the test element 3 can be located outside the pattern, so that the positions of the two ends are closer, and it is convenient to set a test pad electrically connected to the two.

[0040] In other embodiments, the shape of the test element 3 may also be an S-shape or a plurality of S-shapes connected in sequence. The shape of the test element 3 may also be other irregular shapes, as long as it can be ensured to span across all the splicing boundaries 20 .

[0041] In some embodiments, the orthographic projections of at least two sub-elements 31 on the substrate 10 are symmetrical or identical in shape and have the same size. Figure 3 and Figure 5 The shapes and areas of the sub-elements 31 in the first exposure area M1 and the third exposure area M3 are the same, which is helpful to simplify the calculation process of the theoretical resistance of the test element 3.

[0042] Continue to refer Figure 3-Figure 5 , the actual resistance at both ends of the test element 3 can be detected, and the overall offset of the four exposure areas M can be obtained. Since only one resistance test can be performed, the number of resistance tests is small, thereby improving the speed of the test. However, the above-mentioned detection method can only determine whether there is an exposure area M with offset among the four exposure areas M, but cannot determine which exposure areas M have offset. In order to facilitate the subsequent adjustment of the corresponding process parameters, a fragment of the test element 3 can be intercepted for resistance testing to determine which specific exposure areas M have offset.

[0043] For example, refer to Figure 3 , the resistance of the test element 3 between the first point C and the second point D is detected, thereby determining whether the first exposure area M1 is aligned with the third exposure area M3. However, the test element 3 between the first point C and the second point D only crosses the splicing boundary 20 once, and the length of the test element 3 between the two points is short, and the resistance is small, so the accuracy of the test result needs to be improved. Figure 6 The test element 3 shown can improve the accuracy of obtaining the offset condition of the local exposure area M, which will be described in detail below.

[0044] refer to Figure 6 ,refer to Figure 6The test element 3 includes a plurality of first elements 33 and a plurality of second elements 34. The number of the first elements 33 is equal to the number of the splicing boundaries 20, and each first element 33 spans a splicing boundary 20, that is, each first element 33 is simultaneously located on two adjacent exposure areas M. When the adjacent exposure areas M are aligned, the first elements 33 are in a continuous state, and the first elements 33 can span the splicing boundaries 20 multiple times. For example, the first element 33 can be S-shaped or multiple S-shaped elements connected in sequence. The second element 34 is connected to the ends of the two first elements 33 respectively, so that the entire test element 3 is in a continuous state.

[0045] The purpose of such a design is to first test the resistance at both ends of the entire test element 3 to determine the overall offset of the multiple exposure areas M corresponding to the test element 3. If there is no exposure area M with offset among the multiple exposure areas M, there is no need to perform a local resistance test. If there is an exposure area M with offset among the multiple exposure areas M, the resistance at both ends of each first element 33 can be measured separately, so that it can be determined which specific exposure areas M have offset. In addition, since each first element 33 crosses the splicing boundary 20 multiple times and is a zigzag pattern, that is, the first element 33 has a large length, the local offset of adjacent exposure areas M can be obtained more accurately.

[0046] Continue to refer Figure 6 In some embodiments, eight test pads may be provided, that is, each first element 33 is electrically connected to a test pad at both ends. For example, two test pads are located in the first exposure area M1 and are respectively connected to the ends of two different first elements 33. In other words, the two test pads are also electrically connected to the ends of the entire test element 3, so the two test pads can be applied not only to the test process of local resistance, but also to the test process of the total resistance of the test element 3.

[0047] Continue to refer Figure 6 , when all exposure areas M corresponding to the splicing boundaries 20 spanned by the plurality of first elements 33 are aligned, the shapes and areas of the orthographic projections of the plurality of first elements 33 on the substrate 10 are the same, so that the theoretical resistances of the plurality of first elements 33 are the same, thereby simplifying the comparison process between the measured resistance and the theoretical resistance of the first elements 33; in addition, it is also helpful to simplify the calculation process of the theoretical resistance of the test element 3. In some embodiments, the shapes and areas of the orthographic projections of at least two second elements 34 on the substrate 10 are the same, so as to simplify the calculation process of the theoretical resistance of the test element 3. For example, the shape of the orthographic projection of the second element 34 on the substrate 10 can be an "L" shape, so that its length is easier to calculate.

[0048] Continue to refer Figure 6The head and tail ends of the test element 3 can be located in the same exposure area M, for example, both located in the first exposure area M1. This makes it easy to set the position of the test pad and shorten the routing length of the wiring layer 53, avoiding the influence of the resistance of the wiring layer 53 itself on the test result.

[0049] Example 2, reference Figure 7 There are multiple test elements 3, and each test element 3 spans multiple stitching boundaries 20 and is located on all exposure areas M that share the stitching boundary 20. For example, there are four test elements 3, each test element 3 spans three stitching boundaries 20 and is located on four exposure areas M.

[0050] refer to Figure 7 , taking one of the four test elements 3 as an example, the test element 3 spans the splicing boundary 20 between the first exposure area M1 and the third exposure area M3, also spans the splicing boundary 20 between the third exposure area M3 and the fourth exposure area M4, and also spans the splicing boundary 20 between the fourth exposure area M4 and the second exposure area M2. After detecting the resistance of the test element 3, the overall offset of the exposure areas M corresponding to the three splicing boundaries 20 can be obtained, but the offset of the first exposure area M1 and the second exposure area M2 cannot be obtained. However, since there are multiple test elements 3, the resistance of each test element 3 can be tested, and the overall offset of the four exposure areas M can be determined by combining the results of multiple resistance tests.

[0051] Example 3, reference Figure 8 , there are multiple test elements 3, and each test element 3 spans the splicing boundary 20 between two adjacent exposure areas M. That is, there is a one-to-one correspondence between the test element 3 and the splicing boundary 20. By performing a resistance test on each test element 3 separately, the offset degree of the two exposure areas M corresponding to the test element 3 can be obtained. Thereafter, the resistance test conditions of the multiple test elements 3 are summarized to determine the overall offset condition of the multiple exposure areas M.

[0052] Continue to refer Figure 8 , the number of exposure areas M is more than two, the number of stitching boundaries 20 and the number of test elements 3 are both multiple, and the multiple stitching boundaries 20 correspond to the multiple test elements 3 one by one. In some embodiments, the shape of the positive projection of the test element 3 on the substrate 10 is an S shape or a plurality of S shapes connected in sequence. In this way, while crossing the stitching boundaries 20 multiple times, the space occupied on the substrate 10 can be reduced, thereby providing more sufficient space for other elements. In some embodiments, the shape of the test element 3 can be a spiral or other irregular shape, as long as it can ensure that it crosses a stitching boundary 20.

[0053] Continue to refer Figure 8When all exposure areas M corresponding to the splicing boundaries 20 spanned by the multiple test elements 3 are aligned, the orthographic projections of the multiple test elements 3 on the substrate 10 are symmetrical or identical in shape and size. This is conducive to simplifying the calculation process of the theoretical resistance, thereby improving the efficiency of obtaining the offset conditions of the multiple exposure areas M.

[0054] contrast Figure 6 and Figure 8 It can be seen that for Figure 6 The test element shown can directly obtain the overall offset of all exposure areas M, and can also directly obtain the local offset of every two adjacent exposure areas M. Figure 8 The test element shown can only directly obtain the local offset conditions of every two adjacent exposure areas M. To obtain the overall offset conditions of all exposure areas M, it is necessary to summarize the local offset conditions.

[0055] Example 4, reference Fig. 9 , there are two exposure areas M, one splicing boundary 20, and one test element 3 straddles the splicing boundary 20 between adjacent exposure areas M. That is, the test element 3 straddles one splicing boundary 20 and is located on two exposure areas M. Whether the two exposure areas M are offset can be determined by detecting the resistance of the test element 3.

[0056] Continue to refer Fig. 9 , the shape of the orthographic projection of the test element 3 on the substrate 10 is an S shape or a plurality of S shapes connected in sequence. For example, the test element 3 includes a plurality of straight strips 32 connected in sequence to form an S shape or a plurality of connected S shapes, and the adjacent straight strips 32 can be arranged vertically, and the straight strips 32 can be perpendicular to the splicing boundary 20 they cross. Alternatively, the angle between adjacent straight strips 32 can be an acute angle, and each straight strip 32 crosses the splicing boundary 20; in this way, the angle between the straight strips 32 and the splicing boundary 20 is an acute angle or an obtuse angle, thereby the cross-sectional area of ​​the test element 3 on the splicing boundary 20 is larger and the process margin is larger. In addition, the length of the straight strip 32 is easier to calculate, which is conducive to simplifying the process of obtaining the theoretical resistance of the test element 3.

[0057] Example 5, reference Fig.10 and Fig.11 There are two exposure areas M, one splicing boundary 20 , a plurality of test elements 3 , and each test element 3 spans across the splicing boundary 20 between adjacent exposure areas M.

[0058] By performing a resistance test on the test element 3, the alignment status between the two exposure areas M can be obtained. Since there are multiple test elements 3, multiple resistance tests can be performed and the results of the multiple resistance tests can be compared, which is conducive to improving the accuracy of obtaining the alignment status.

[0059] Specifically, refer to Fig.10 Each test element 3 spans across a splicing boundary 20, and the test element 3 may be in the form of a straight strip. Fig.11 , each test element 3 spans multiple splicing boundaries 20. Example 6, reference Figure 12-14 , the number of exposure areas M is more than two, and the number of stitching boundaries 20 is more than two. There are multiple test elements 3, and each test element 3 spans a stitching boundary 20, and each stitching boundary 20 is spanned by multiple test elements 3. Therefore, the alignment of the two corresponding exposure areas M can be obtained by detecting the resistance of each test element 3. In addition, comparing the resistances of multiple test elements 3 spanning the same stitching boundary 20 is conducive to improving the accuracy of obtaining the alignment.

[0060] Specifically, refer to Fig.12 , the lengths of the multiple test elements 3 across the same splicing boundary 20 are the same, which is helpful to simplify the calculation process of the theoretical resistance of the test element 3. Figure 13-14 The lengths of the multiple test elements 3 across the same splicing boundary 20 may also be different, and the multiple test elements 3 are arranged in sequence according to their lengths. This is conducive to improving the space utilization of the exposure area M. Fig.13 , the sub-elements 31 on two adjacent exposure areas M can be arranged axially symmetrically. Fig.14 The sub-elements 31 on two adjacent exposure areas M may not be arranged in an axisymmetric manner, and the sub-elements 31 on two exposure areas M on the same diagonal line may be arranged in a center-symmetrical manner.

[0061] In some embodiments, the splicing exposure and the aforementioned test element 3 can be applied to the semiconductor packaging field. For example, the substrate 10 can be an interposer in the packaging field. In 2.5D and 3D packaging, the interposer is one of the key technologies, and its process is becoming more and more complicated. The splicing exposure and the aforementioned test element 3 are conducive to meeting the requirements of larger size and higher precision of the interposer. In other embodiments, the splicing exposure and the aforementioned test element 3 can be applied to the front-end manufacturing process of the chip.

[0062] In summary, according to the different alignment conditions of adjacent exposure areas M, the continuous state of the test element 3 changes, thereby affecting the resistance of the test element 3. The test element 3 may be tested for overall resistance first, and then for local resistance; or, only the test element 3 may be tested for overall resistance; or, only the test element 3 may be tested for local resistance. Based on the resistance test results, the offset of adjacent exposure areas M may be discovered, thereby facilitating timely adjustment of process parameters to ensure the yield of the semiconductor structure.

[0063] Combined with reference Figure 1-Figure 17Another embodiment of the present disclosure provides a method for testing a semiconductor structure, which can be used to test the aforementioned semiconductor structure.

[0064] refer to Fig.16 , Step S1: Provide a semiconductor structure as a semiconductor structure to be tested. The semiconductor structure is the semiconductor structure in the aforementioned embodiment. The detailed description of the semiconductor structure can refer to the aforementioned embodiment and will not be repeated here.

[0065] refer to Fig.16 Step S2: Provide a reference resistance, which is the ideal resistance of the test element 3 when the splicing boundaries 20 between the adjacent exposure areas M it spans are fully aligned, that is, the ideal resistance of the test element 3 when there is no offset in the adjacent exposure areas M. In some embodiments, the reference resistance can be obtained by theoretical calculation, for example, the length and cross-sectional area of ​​the test element 3 and the resistivity of the material of the test element 3 are obtained, and the reference resistance is calculated based on the above three data. In other embodiments, the reference resistance can also come from a measured resistance value in a reference standard semiconductor structure.

[0066] refer to Fig.16 Step S3: Detecting the experimental resistance, which is the resistance of the test element 3 in the semiconductor structure to be tested. It should be noted that in some embodiments, the probe of the resistance tester is connected to the first test pad 51 and the second test pad 52 (reference Fig.15 ) instead of directly contacting the ends of the test element 3. Therefore, the resistance actually tested also includes the test pad and the wiring layer 53 (reference Fig.15 Therefore, in the process of providing the reference resistance, if a theoretical calculation method is adopted, the theoretical resistance of the test pad and the wiring layer 53 can also be calculated, and added to the theoretical resistance of the test element 3, and the total resistance of the three can be compared with the actual test resistance.

[0067] In other embodiments, the direct detection result may not be resistance, but current or voltage, and the resistance change can be evaluated through the current or voltage.

[0068] refer to Fig.16 Step S4: Compare the experimental resistance with the reference resistance and obtain the resistance difference between the two. For example, a reference resistance is d1, and an experimental resistance is d2, and the resistance difference between the two is d2-d1.

[0069] Step S5: Determine the offset of multiple exposure areas M of the semiconductor structure to be tested based on the resistance difference. Specifically, set a threshold range according to the reference resistance, and determine the relationship between the resistance difference and the threshold range; if the resistance difference exceeds the threshold range, mark the semiconductor structure to be tested as unqualified for exposure alignment; if the resistance difference does not exceed the threshold range, mark the semiconductor structure to be tested as qualified for exposure alignment.

[0070] For example, a reference resistor is d1, and the threshold range is set to 0.1*d1, that is, the threshold range is one tenth of the reference resistor. A test resistor is d2, and if the resistance difference d2-d1 is less than or equal to 0.1*d1, the semiconductor structure to be tested is marked as qualified for exposure alignment; if the resistance difference d2-d1 is greater than 0.1*d1, the semiconductor structure to be tested is marked as unqualified for exposure alignment. The above threshold range is only for schematic illustration and can be adjusted according to the specific situation of the test element 3.

[0071] This will be illustrated with an example below.

[0072] Example 1, reference Figure 3-Figure 6 , a test element 3 spans across multiple stitching boundaries 20 and is located on all exposure areas M that share the stitching boundaries 20; based on the resistance difference, the offset of multiple exposure areas M of the semiconductor structure to be tested is determined, including: determining the overall offset of multiple exposure areas M corresponding to all stitching boundaries 20 spanned by the test element 3 of the semiconductor structure to be tested.

[0073] It should be noted that, in some embodiments, Figure 1-Figure 14 As shown, the entire semiconductor structure includes a test area M', and "determining the overall offset of multiple exposure areas M corresponding to multiple stitching boundaries 20 spanned by the test element 3 of the semiconductor structure to be tested" can be understood as: determining the overall offset of the exposure area M corresponding to the test area M'.

[0074] In other embodiments, reference Fig.16, the entire semiconductor structure includes a plurality of test areas M' arranged in an array. In this case, "a test element 3 spans across a plurality of stitching boundaries 20 and is located on all exposure areas M that share the stitching boundaries 20" can be understood as: a test element 3 in a certain test area M' spans across a plurality of stitching boundaries 20 corresponding to the test area M' and is located on all exposure areas M corresponding to the test area M'. That is, not one test element 3 is located on all exposure areas M of the semiconductor structure. Accordingly, "determining the overall offset of all exposure areas M corresponding to the plurality of stitching boundaries 20 spanned by the test element 3 of the semiconductor structure to be tested" can be understood as: determining the overall offset of a plurality of exposure areas M corresponding to a certain test area M', rather than the offset of all exposure areas M of the semiconductor structure. The offset of all exposure areas M of the semiconductor structure needs to be determined jointly based on the test conditions of all test areas M'.

[0075] In some embodiments, reference Figure 3-Figure 6 There are four exposure areas M, and four test sub-areas M0 form a test area M'. There is a test element 3 in the test area M'. The test element 3 spans across four splicing boundaries 20. In the process of detecting the experimental resistance, the resistance between the head and tail ends of the test element 3 can be detected to determine the overall offset of the four exposure areas M. In addition, if the four exposure areas M are offset as a whole, the resistance test of the local test element 3 can also be performed. For example, refer to Figure 6 , resistance test is performed on the multiple first elements 33 in the test element 3, so that it can be determined which exposure areas M among the four exposure areas M are offset.

[0076] Example 2, reference Figure 8 There are multiple test elements 3, and each test element 3 spans across the stitching boundary 20 between two adjacent exposure areas M; based on the resistance difference, the offset of multiple exposure areas M of the semiconductor structure to be tested is determined, including: determining the local offset of two exposure areas M corresponding to each stitching boundary 20 of the semiconductor structure to be tested.

[0077] Continue to refer Figure 8 For example, there are four exposure areas M, and four test sub-areas M0 form a test area M'. There are four test elements 3 in the test area M', and each test element 3 spans a splicing boundary 20. By performing a resistance test on each test element 3, it can be determined whether the two exposure areas M corresponding to the test element 3 are offset. Thereafter, combining the test results of the four test elements 3, it can be determined whether the entirety of the four exposure areas M is offset.

[0078] The above-mentioned test method is only an example description, and the test method can also be adjusted according to the different quantity relationships and position relationships between the test elements 3 and the splicing boundary 20.

[0079] In summary, the experimental resistance is compared with the control resistance, and the resistance difference between the two is obtained. Based on the resistance difference, the offset of multiple exposure areas M of the semiconductor structure to be tested can be determined, thereby determining whether the offset meets the specification requirements. In addition, different offset conditions can be obtained for different test elements 3. When the test element 3 only crosses one stitching boundary 20, the offset of the adjacent exposure areas M sharing this stitching boundary 20 can be obtained; when the test element 3 crosses multiple stitching boundaries 20, the overall offset of the multiple exposure areas M corresponding to the test element 3 can be obtained.

[0080] In the description of this specification, the description with reference to the terms "some embodiments", "exemplarily", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present disclosure. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples, without contradiction.

[0081] Although the embodiments of the present disclosure have been shown and described above, it is to be understood that the above embodiments are exemplary and cannot be construed as limitations on the present disclosure. A person skilled in the art may change, modify, replace and modify the above embodiments within the scope of the present disclosure. Therefore, any changes or modifications made in accordance with the claims and specification of the present disclosure shall fall within the scope covered by the patent of the present disclosure.

Claims

1. A semiconductor structure, characterized in that: include: A substrate, the substrate comprising a plurality of spliced ​​exposure areas, with a splicing boundary between adjacent exposure areas; The adjacent exposure areas are exposed successively using the same photomask during the exposure process; A test element straddling the stitching boundary, the test element comprising at least sub-elements respectively located on adjacent exposure areas; When adjacent exposure areas are aligned, the sub-elements in the test element are spliced ​​into a continuous conductive structure.

2. The semiconductor structure according to claim 1, characterized in that The test element crosses the stitching boundary multiple times.

3. The semiconductor structure according to claim 1 or 2, characterized in that: One test element spans across a plurality of stitching boundaries and is located on all of the exposure regions that share the stitching boundaries.

4. The semiconductor structure according to claim 3, characterized in that: The orthographic projection of the test element on the substrate is in a spiral shape.

5. The semiconductor structure according to claim 4, characterized in that: The test element comprises a plurality of straight strips connected in sequence; Wherein, each of the straight strip portions spans across one of the splicing boundaries and is located on two adjacent exposure areas; or, each of the straight strip portions is located on one of the exposure areas.

6. The semiconductor structure according to claim 3, characterized in that: Orthographic projections of at least two of the sub-elements on the substrate are symmetrical or identical in shape and size.

7. The semiconductor structure according to claim 3, characterized in that: The test element crosses the same number of times on the plurality of stitching boundaries.

8. The semiconductor structure according to claim 1 or 2, characterized in that: There are a plurality of test elements, and each of the test elements spans the splicing boundary between two adjacent exposure areas.

9. The semiconductor structure according to claim 8, characterized in that: The shape of the orthographic projection of the test element on the substrate is an S shape or a plurality of S shapes connected in sequence.

10. The semiconductor structure according to claim 8, characterized in that When all the exposure areas corresponding to the stitching boundaries spanned by the multiple test elements are aligned, the orthographic projections of the multiple test elements on the substrate are symmetrical or identical in shape and have the same size.

11. The semiconductor structure according to claim 1, characterized in that: Also includes: The first test pad and the second test pad are electrically connected to both ends of the test element respectively.

12. A method for detecting a semiconductor structure, characterized in that: include: Providing a semiconductor structure as claimed in any one of claims 1 to 11 as a semiconductor structure to be tested; Detecting an experimental resistance, wherein the experimental resistance is the resistance of the test element in the semiconductor structure to be tested; Providing a reference resistance, the reference resistance being an ideal resistance of the test element when the stitching boundaries between adjacent exposure regions spanned by the test element are fully aligned; Comparing the experimental resistor with the reference resistor and obtaining a resistance difference between the two; The offset conditions of the plurality of exposure regions of the semiconductor structure to be tested are determined based on the resistance difference.

13. The method for detecting a semiconductor structure according to claim 12, characterized in that: One of the test elements spans across a plurality of the stitching boundaries and is located on all of the exposure areas that share the stitching boundaries; Determining the offset of the plurality of exposure regions of the semiconductor structure to be tested based on the resistance difference includes: determining the overall offset of all exposure regions corresponding to the stitching boundary spanned by the test element of the semiconductor structure to be tested.

14. The method for detecting a semiconductor structure according to claim 12, characterized in that: There are a plurality of test elements, and each of the test elements spans the splicing boundary between two adjacent exposure areas; Determining the offset conditions of the plurality of exposure regions of the semiconductor structure to be tested based on the resistance difference includes: determining the local offset conditions of two exposure regions corresponding to each splicing boundary of the semiconductor structure to be tested.

15. The method for detecting a semiconductor structure according to claim 12, characterized in that: Determining the offset of the plurality of exposure regions of the semiconductor structure to be tested based on the resistance difference comprises: Setting a threshold range according to the reference resistance; determining a relationship between the resistance difference and the threshold range; When the resistance difference exceeds the threshold range, marking the semiconductor structure to be tested as unqualified for exposure alignment; When the resistance difference does not exceed the threshold range, the semiconductor structure to be tested is marked as qualified for exposure alignment.

Images