Wafer structure and preparation method thereof

Abstract

The invention belongs to the technical field of semiconductor manufacturing, and provides a wafer structure, which comprises a chip area and a positioning area, the positioning area comprises a fine alignment area, the fine alignment area comprises M semiconductor layers stacked along a first direction, the M semiconductor layers are respectively marked as first to Mth semiconductor layers, and the wafer structure is overlooked along the first direction, the fine alignment area is divided into N mark areas in the second direction, the N mark areas are marked as the first mark area to the Nth mark area respectively, a fine alignment graph is arranged in at least one semiconductor layer of each mark area, the first semiconductor layer is an alignment layer, and the fine alignment graph is an alignment mark. When exposure positioning is carried out, the mark area with the best positioning effect can be judged according to the intensity of the positioning signal of each mark area, and effective alignment positioning of the wafer is realized. The invention further provides a preparation method of the wafer structure, and the preparation method is used for manufacturing the wafer structure.

Description

Technical Field

[0001] The present application relates to the field of semiconductor manufacturing technology, and in particular to a wafer structure and a preparation method thereof. Background Art

[0002] Surface passivation technology is an important part of the semiconductor device manufacturing process. It can form a passivation layer on the device surface to prevent the external environment from corroding the internal structure of the device, while reducing the generation of surface states and improving the electrical performance and reliability of the device. In existing semiconductor devices, a PI (polyimide) passivation layer is often provided. In order to further improve the withstand voltage capability, a CB passivation layer is introduced in the semiconductor manufacturing process before the PI passivation layer is formed, and together with the PI passivation layer, a composite passivation layer is formed.

[0003] In the semiconductor manufacturing process, the upper layer of the CB passivation layer is a thick aluminum layer. Since the solubility of aluminum in silicon is very low, while the solubility of silicon in aluminum is very high, when aluminum is deposited on the silicon wafer, silicon dissolves in aluminum and forms cracks. Aluminum atoms enter the cracks to form sharp wedges, which in turn cause PN junction failure. In order to solve the sharp wedge problem, silicon-aluminum alloy is often used as the material of the thick aluminum layer.

[0004] Since the alignment marks of semiconductor devices are covered with a thick aluminum layer, the outline of the alignment marks will become blurred, making photolithography alignment very difficult. Therefore, in the semiconductor design stage, the thick aluminum layer on the alignment marks needs to be removed. However, after the thick aluminum layer is exposed and etched, the silicon in the thick aluminum layer will precipitate and aggregate on the surface to form silicon chips, and the CB layer has a very prominent amplification effect on the silicon chips, making the reflected light of the alignment marks more messy, resulting in serious interference with the positioning signal during exposure positioning, causing distortion of the reflected signal, and then causing signal recognition errors or frequent exposure terminations and inability to expose. Therefore, how to enhance the recognition of the alignment marks of semiconductor devices by the lithography machine, reduce the probability of failure to expose and the risk of positioning deviation, and ensure product quality, is a problem that needs to be solved urgently. Summary of the invention

[0005] In view of the shortcomings of the prior art mentioned above, the purpose of the present application is to provide a wafer structure and a preparation method thereof, so as to solve the problems existing in the prior art such as poor wafer alignment mark recognition and positioning effect, improve the strength of the alignment signal during exposure positioning of the lithography machine, and improve the alignment and positioning effect.

[0006] To achieve the above-mentioned purpose and other related purposes, the present application provides a wafer structure, including a chip area and a positioning area located at the periphery of the chip area, the positioning area includes a fine alignment area, the fine alignment area includes M semiconductor layers sequentially stacked along a first direction, and are respectively recorded as the first to Mth semiconductor layers along the first direction; wherein the first direction is the thickness direction of the wafer structure, and M is a positive integer greater than 5;

[0007] Looking down at the wafer structure along the first direction, the fine alignment area is in a strip structure, and the extension direction of the strip structure of the fine alignment area is the second direction. The fine alignment area is divided into N marking areas along the second direction, and are respectively recorded as the first to Nth marking areas along the second direction, wherein N is a positive integer greater than 3, and a fine alignment pattern is provided in at least one semiconductor layer of each of the marking areas, and the first semiconductor layer is an alignment layer, and the fine alignment pattern in the first semiconductor layer is an alignment mark.

[0008] Optionally, M takes a value of 8, and the fine alignment area includes the 1st to 8th semiconductor layers stacked sequentially along the first direction, wherein the 2nd to 4th semiconductor layers are material injection layers, the 5th semiconductor layer is a polycrystalline silicon layer, the 6th semiconductor layer is a thick aluminum layer, and the 7th and 8th semiconductor layers are passivation layers.

[0009] Optionally, the precise alignment pattern is in a cross-shaped structure, including a first type of pattern and a second type of pattern, the first type of pattern is an upward convex cross structure, and the second type of pattern is a grooved cross structure.

[0010] Optionally, the cross-shaped structure of the precise alignment pattern has four rectangular protrusions, and the width of the rectangular protrusions is recorded as a mark width, and the value of the mark width is 1.5 μm to 6 μm.

[0011] Optionally, M takes a value of 8, and there is a K-1th marking area among the N marking areas; the K-1th marking area includes the 1st to 8th semiconductor layers, and the second type of graphics are arranged in the 3rd semiconductor layer and the 5th to 8th semiconductor layers of the K-1th marking area; wherein K is a positive integer less than N.

[0012] Optionally, the second type of patterns in the third semiconductor layer and the second type of patterns in the fifth to eighth semiconductor layers are aligned along the first direction.

[0013] Optionally, the N marking areas further include a Kth marking area and a K+1th marking area; and,

[0014] The Kth marking region includes the first to fourth semiconductor layers and the sixth and eighth semiconductor layers, and the first semiconductor layer of the Kth marking region is provided with the first type of pattern or the second type of pattern;

[0015] The K+1th marking region includes the first to second semiconductor layers, the fourth semiconductor layer and the eighth semiconductor layer, and the first type of pattern or the second type of pattern is arranged in the first semiconductor layer of the K+1th region.

[0016] Optionally, in the first semiconductor layer of the Kth mark region, the mark width of the precise alignment pattern is a first width;

[0017] In the third semiconductor layer and the fifth to eighth semiconductor layers of the K-1th region, the mark width of the second type of graphics is the second width.

[0018] Optionally, the first width is 2.5 μm or 5 μm, and the second width is 3 μm.

[0019] The present application also provides a method for preparing a wafer structure, which is used to manufacture any of the wafer structures described in the aforementioned embodiments, comprising the following steps:

[0020] Providing a wafer sample having a first semiconductor layer, wherein a precision alignment pattern is provided in the first semiconductor layer;

[0021] forming a second semiconductor layer on the first semiconductor layer;

[0022] Applying photoresist on the second semiconductor layer and performing development and exposure;

[0023] Etching and cleaning the exposed second semiconductor layer to form a second semiconductor layer having a precise alignment pattern;

[0024] The third to Mth semiconductor layers having precise alignment patterns are sequentially formed on the second semiconductor layer.

[0025] The wafer structure and preparation method thereof provided in the present application have at least the following beneficial effects:

[0026] First, in the wafer structure of the present embodiment, the precision alignment area is divided into N marking areas, the marking area has multiple semiconductor layers, and a precision alignment pattern is arranged in at least one semiconductor layer in each marking area, and the marking area with the best positioning effect can be judged according to the scanning intensity of the positioning signal of each marking area, thereby realizing effective alignment and positioning of the wafer; the K-1th marking area to the Kth marking area with specific structures in the N marking areas, and the thick aluminum layer of the Kth marking area is retained during the exposure and etching process, which effectively reduces the precipitation of silicon chips and thus reduces the interference with the positioning signal, and the precision alignment pattern aligned along the first direction is arranged in the 3rd semiconductor layer and the 5th semiconductor layer to the 8th semiconductor layer of the K-1th marking area, and the K+1th marking area removes the 3rd semiconductor layer and the 5th semiconductor layer to the 7th semiconductor layer, reduces the intensity of the clutter signal and improves the intensity of the positioning signal, thereby significantly reducing the risk of position deviation during wafer alignment, ensuring the accuracy and reliability of wafer alignment, effectively reducing the rework rate and raw material consumption during exposure, saving production costs, and ensuring product quality, and having extremely high practical and promotion value.

[0027] On the second aspect, the method for preparing the wafer structure provided in the present application is used to manufacture the above-mentioned wafer structure, and therefore also has the above-mentioned beneficial effects. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0029] Figure 1 Shown is a structural schematic diagram of the wafer structure provided in Example 1 of the present application.

[0030] Figure 2 Shown is a schematic diagram of a partial cross-sectional structure of a precision alignment pattern along the second direction provided in an optional embodiment of the first embodiment of the present application.

[0031] Figure 3 Shown is a schematic structural diagram of silicon chips precipitated on the surface of the wafer structure provided in Example 1 of the present application.

[0032] Figure 4 Shown is a schematic diagram of the surface structure with silicon chips in the prior art provided in Example 1 of the present application.

[0033] Figure 5 Shown is a schematic diagram of scanning of positioning signals during exposure positioning in the prior art provided in Example 1 of the present application.

[0034] Figure 6 Shown is a schematic diagram of the structure of spot etching of silicon chips in the prior art provided in Example 1 of the present application.

[0035] Figure 7 Shown is a schematic diagram of a partial cross-sectional structure of a precision alignment pattern along the second direction provided by another optional embodiment in the first embodiment of the present application.

[0036] Figure 8 Shown is a schematic diagram of the position of the precise alignment pattern provided in the optional embodiment of the first embodiment of the present application.

[0037] Fig. 9 Shown is a schematic diagram of a top view of a portion of a precision alignment area along a first direction provided in an optional embodiment of the first embodiment of the present application.

[0038] Fig.10 Display as Fig. 9 A partial enlarged view of the precision alignment pattern within the elliptical coil in the precision alignment area shown.

[0039] Fig.11 Shown is a schematic diagram of scanning the positioning signal during exposure positioning provided by an optional embodiment in the first embodiment of the present application.

[0040] Fig.12 Shown is a schematic flow chart of a method for preparing a wafer structure provided in the second embodiment of the present application.

[0041] Reference numerals:

[0042] 1. Wafer structure; 11. Chip area; 12. Positioning area; 121. Precision alignment area; 1211. 1st semiconductor layer; 1212. 2nd semiconductor layer; 1213. 3rd semiconductor layer; 1214. 4th semiconductor layer; 1215. 5th semiconductor layer; 1216. 6th semiconductor layer; 1217. 7th semiconductor layer; 1218. 8th semiconductor layer; 1201. K-2th marking area; 1202. K-1th marking area; 1203. Kth marking area Domain; 1204, K+1th marking area; 1205, K+2th marking area; 1206, K+3th marking area; 1207, K+4th marking area; 1208, K+5th marking area; 1209, K+6th marking area; 122, first positioning pattern; 1221, fine alignment pattern; 1222, coarse alignment pattern; 123, coarse alignment area; 2, mask; 21, second positioning pattern; 31, lens group; 32, mask; 321, third positioning pattern. DETAILED DESCRIPTION

[0043] In order to make the technical purpose, technical solution and technical effect of the present application clearer, the technical solution in the present application will be clearly and completely described in conjunction with the embodiments below. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. The components of the embodiments of the present application described and shown in the drawings here can be arranged and designed in various different configurations.

[0044] Therefore, the following detailed description of the embodiments of the present application is not intended to limit the scope of the present application for protection, but merely represents the selected embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work are within the scope of protection of the present application. In addition, the terms "first" and "second" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance.

[0045] In the description of the present application, it should be noted that the description with reference to the terms "one embodiment", "some embodiments", "illustrative embodiments", "example", "specific example" or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the implementation or example are included in at least one implementation or example of the present application. In this specification, the schematic representation of the above terms does not necessarily refer to the same implementation or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more implementations or examples in a suitable manner.

[0046] Embodiment 1

[0047] The present embodiment provides a wafer structure 1 for solving the problem in the prior art that, when a lithography machine is positioning a wafer, a positioning signal is seriously interfered with, resulting in poor positioning effect or frequent exposure interruptions.

[0048] In this embodiment, refer to Figure 1 and Figure 2 The wafer structure 1 includes a chip area 11 and a positioning area 12. The chip area 11 is a chip setting area. The positioning area 12 is located at the periphery of the chip area. A first positioning pattern 122 is provided in the positioning area 12 for aligning and positioning the wafer. The positioning area 12 includes a precision alignment area 121. The first positioning pattern 122 includes a precision alignment pattern 1221. The precision alignment pattern is provided in the precision alignment area 121 for precision alignment of the wafer. It should be noted that Figure 2 The fine alignment pattern 1221 shown in the figure does not represent the actual size, but is drawn for ease of understanding. The fine alignment region 121 includes M semiconductor layers stacked in sequence along a first direction, and the M semiconductor layers are sequentially recorded as the first to Mth semiconductor layers along the first direction, wherein the first direction is the thickness direction of the wafer structure 1, and M is a positive integer greater than 5.

[0049] In an optional embodiment, the positioning area further includes a coarse alignment area 123 , and the first positioning pattern 122 further includes a coarse alignment pattern 1222 . The coarse alignment pattern 1222 is disposed in the coarse alignment area 123 , and the coarse alignment pattern 1222 is used for coarse alignment of the wafer.

[0050] In an optional embodiment, the M value can be, for example, 8, and the fine alignment region 121 includes a first semiconductor layer 1211 to an eighth semiconductor layer 1218 stacked in sequence along the first direction. Optionally, among the eight semiconductor layers, the first semiconductor layer 1211 is an alignment layer, and the fine alignment pattern 1221 in the first semiconductor layer 1211 is an alignment mark, which can reflect incident light to form reflected light. The second semiconductor layer 1212 to the fourth semiconductor layer 1214 are material injection layers, for example, the second semiconductor layer 1211 is a semiconductor layer 1218. The body layer 1212 and the fourth semiconductor layer 1214 can be P-type material injection layers, the third semiconductor layer 1213 can be, for example, an N-type material injection layer, the fifth semiconductor layer 1215 is a polysilicon layer, the sixth semiconductor layer 1216 is a metal layer, for example, the sixth semiconductor layer 1216 can be a thick aluminum layer, the seventh semiconductor layer 1217 and the eighth semiconductor layer 1218 are passivation layers, for example, the seventh semiconductor layer 1217 can be a CB passivation layer, and the eighth semiconductor layer 1218 can be, for example, a PI passivation layer.

[0051] In an optional embodiment, the M value can be 5, for example, and the fine alignment region 121 includes the first semiconductor layer 1211 to the fifth semiconductor layer 1215 stacked in sequence along the first direction, wherein the first semiconductor layer 1211 is an alignment layer, the fine alignment pattern 1221 in the first semiconductor layer 1211 is an alignment mark, the second semiconductor layer 1212 is a material injection layer, the third semiconductor layer 1213 is a polycrystalline silicon layer, the fourth semiconductor layer 1214 is a metal layer such as a thick aluminum layer, and the fifth semiconductor layer 1215 is a passivation layer.

[0052] In the prior art, reference Figure 3 and Figure 4 Since the thick aluminum layer covers the alignment mark, the outline of the alignment mark will be blurred. Therefore, the thick aluminum layer above the alignment mark is removed. After the thick aluminum layer is exposed and etched, the silicon in it precipitates and aggregates on the surface to form silicon chips. At this time, refer to Figure 5 When the wafer is exposed and positioned, the silicon scraps are magnified by the passivation layer, making the reflected light of the alignment mark more chaotic, disrupting the positioning signal, causing serious signal scanning noise interference, and increasing the risk of positioning deviation and exposure termination. To solve the above problems caused by silicon scraps, refer to Figure 6 At present, the freckle etching process is often used to make silicon chips fall off. However, the pits produced after the silicon chips fall off will undergo electrochemical reactions, resulting in pad contamination problems on the chip surface, which in turn affects chip performance.

[0053] Based on the above technical issues, refer to Figure 2 In this embodiment, when looking down at the wafer structure 1 along the first direction, the precision alignment region 121 is in a strip structure, and the extension direction of the strip structure of the precision alignment region 121 is the second direction. The precision alignment region 121 is divided into N marking regions along the second direction, and the N marking regions are sequentially recorded as the first to the Nth marking regions along the second direction, wherein N is a positive integer greater than 3, and a precision alignment pattern 1221 is provided in at least one semiconductor layer of each marking region. By providing multiple marking regions and providing precision alignment patterns in the marking regions, when in use, the marking region with the best positioning effect can be determined according to the scanning intensity of the positioning signals of each marking region, thereby achieving effective alignment and positioning of the wafer.

[0054] In an optional embodiment, the precision alignment pattern 1221 in the first semiconductor layer 1211 is an alignment mark, and the precision alignment pattern 1221 in the second semiconductor layer 1212 to the Nth semiconductor layer penetrates the semiconductor layer in which it is located, thereby enabling a window to be formed in the semiconductor layer in which it is located, so as to improve the transmission effect of reflected light, enhance the strength of the positioning signal, and improve the accuracy and reliability of wafer positioning. Optionally, the precision alignment pattern is a cross-shaped structure.

[0055] Reference Figure 1 The wafer structure 1 is placed on the machine platform, and the light generated by the photolithography machine is irradiated to the surface of the wafer structure 1 through the lens group 31 and the mask 2. The photolithography machine is provided with a mask 32, and the mask 32 has a third positioning pattern 321. The mask 2 is provided with a second positioning pattern 21. The incident light irradiates the surface of the wafer and forms reflected light through the first semiconductor layer 1211. The reflected light passes through the second positioning pattern 21 and the third positioning pattern 321 to reach the optical fiber detector. When the first positioning pattern 122, the second positioning pattern 21 and the third positioning pattern 321 are located in the same straight line, the reflected light is detected by the optical fiber detector, and the current position of the wafer structure 1 is recorded by the machine platform, thereby realizing the positioning of the wafer structure 1. When in use, the rough alignment pattern 1222, the second positioning pattern 21 and the third positioning pattern 321 are used to perform rough alignment on the wafer structure 1. After the rough alignment is completed, the fine alignment pattern, the second positioning pattern 21 and the third positioning pattern 321 are used to perform fine alignment on the wafer structure 1, thereby achieving alignment and positioning of the wafer structure 1.

[0056] In an optional embodiment, the number of precision alignment areas 121 in the wafer structure 1 can be one or more. For example, two precision alignment areas 121 are provided in the wafer structure 1, and the two precision alignment areas 121 are spaced apart from each other to achieve precise alignment and positioning of the wafer. Other appropriate numbers of precision alignment areas 121 may also be provided and distributed in an appropriate manner. This embodiment is not limited to the order.

[0057] In an optional embodiment, the precise alignment pattern 1221 is a cross-shaped structure, and the precise alignment pattern 1221 includes a first type of pattern and a second type of pattern, wherein the first type of pattern is an upper convex cross structure, and the second type of pattern is a grooved cross structure. The cross-shaped structure of the precise alignment pattern has four rectangular protrusions, and optionally, the width of the rectangular protrusion is recorded as the mark width, and the value of the mark width is 1.5μm to 6μm.

[0058] In this embodiment, refer to Figure 2 When M takes a value of 8, there is a K-1th marking area 1202 in each of the N marking areas, and the K-1th marking area 1202 includes the 1st semiconductor layer 1211 to the 8th semiconductor layer 1218, and the second type of graphics are arranged in the 3rd semiconductor layer 1213, the 5th semiconductor layer 1215, the 6th semiconductor layer 1216, the 7th semiconductor layer 1217 and the 8th semiconductor layer 1218 of the K-1th marking area 1202, wherein K is a positive integer less than N.

[0059] In an optional embodiment, the second type of graphics in the third semiconductor layer 1213 and the fifth semiconductor layer 1215 to the eighth semiconductor layer 1218 are aligned along the first direction, and the second type of graphics penetrates the semiconductor layer where it is located, so that the third semiconductor layer 1213 and the fifth semiconductor layer 1215 to the eighth semiconductor layer 1218 form windows at corresponding positions along the first direction, thereby improving the transmission effect of reflected light and enhancing the strength of the positioning signal. Optionally, in the third semiconductor layer 1213 and the fifth semiconductor layer 1215 to the eighth semiconductor layer 1218 of the K-1th marking area 1202, the mark width of the second type of graphics is the second width, and further, the second width is 3μm.

[0060] In this embodiment, among the N marking regions, there are also a Kth marking region 1203 and a K+1th marking region 1204. The Kth marking region 1203 includes the first semiconductor layer 1211 to the fourth semiconductor layer 1214, the sixth semiconductor layer 1216, and the eighth semiconductor layer 1218, and the first semiconductor layer 1211 of the Kth marking region 1203 is provided with a first type of pattern or a second type of pattern. The K+1th marking region 1204 includes the first semiconductor layer 1211, the second semiconductor layer 1212, the fourth semiconductor layer 1214, and the eighth semiconductor layer 1218, and the first semiconductor layer 1211 of the K+1th marking region 1204 is provided with a first type of pattern or a second type of pattern. Optionally, in the first semiconductor layer 1211 of the Kth marking region 1203, the marking width of the precision alignment pattern 1221 is the first width, and further, the first width is 2.5 μm or 5 μm.

[0061] In an alternative embodiment, reference Figure 2, K is a positive integer greater than 3, N is a positive integer greater than 10, and the N marking areas include K-2 marking area 1201 to K+6 marking area 1209. Specifically, the K-2 marking area 1201 includes the first and second semiconductor layers 1212, the fourth semiconductor layer 1214 and the eighth semiconductor layer 1218, the first semiconductor layer 1211 is provided with a first type of pattern, the K+1 marking area 1204 and the K+4 marking area 1207 have the same structure as the K-2 marking area 1201, and optionally, the marking widths of the first type of pattern in the K-2 marking area 1201, the K+1 marking area 1204 and the K+4 marking area 1207 are 3.5μm, 4.5μm and 5.5μm, respectively. The K-1th marking region 1202 includes the 1st semiconductor layer 1211 to the 8th semiconductor layer 1218, and the second type of graphics are arranged in the 3rd semiconductor layer 1213 and the 5th semiconductor layer 1215 to the 8th semiconductor layer 1218 of the K-1th marking region 1202. The K+2th marking region 1205 and the K+5th marking region 1208 have the same structure as that of the K-1th marking region 1202. Optionally, the marking width of the second type of graphics in the above semiconductor layers is 3μm. The Kth marking region 1203 includes the 1st semiconductor layer 1211 to the 4th semiconductor layer 1214, the 6th semiconductor layer 1216, and the 8th semiconductor layer 1218. The 1st semiconductor layer 1211 of the Kth marking region 1203 is provided with a first type of graphic. The K+3rd marking region 1206 has the same structure as the Kth marking region 1203. Optionally, the marking widths of the first type of graphic of the Kth marking region 1203 and the K+3rd marking region 1206 are 2.5μm and 5μm, respectively. The K+1st marking region 1204 includes the first semiconductor layer 1211, the second semiconductor layer 1212, the fourth semiconductor layer 1214 and the eighth semiconductor layer 1218, the first semiconductor layer 1211 of the K+1st marking region 1204 is provided with a first type of pattern, the K+4th marking region 1207 has the same structure as the K+1st marking region 1204, and optionally, the marking widths of the first type of pattern of the K+1st marking region 1204 and the K+4th marking region 1207 are 4.5 μm and 5.5 μm, respectively. The K+6th marking region 1209 includes the first semiconductor layer 1211 to the fourth semiconductor layer 1214 and the eighth semiconductor layer 1218, the first semiconductor layer 1211 of which is provided with a first type of pattern, and optionally, the marking width of the first type of pattern of the K+6th marking region 1209 is 6 μm.

[0062] In an alternative embodiment, reference Figure 7 , K is a positive integer greater than 3, N is a positive integer greater than 10, and among the N marking areas, there are K-2 marking areas 1201 to K+6 marking areas 1209, and the K-2 marking areas 1201 to K+6 marking areas 1209 and Figure 2The structure shown is similar, except that a precision alignment pattern 1221 of the second type of pattern is arranged in the first semiconductor layer 1211 of the K-2 marking area 1201, the K marking area 1203, the K+1 marking area 1204, the K+3 marking area 1206, the K+4 marking area 1207 and the K+6 marking area 1209.

[0063] In this embodiment, when etching the 6th semiconductor layer 1216, the photoresist on the 6th semiconductor layer 1216 of the Kth marking area 1203 is retained to retain the thick aluminum layer, thereby reducing the precipitation of silicon chips to reduce interference with the positioning signal, and the mark width of the alignment mark of the Kth marking area 1203 is set to a specific value. At the same time, a precise alignment pattern aligned along the first direction is provided in the 3rd semiconductor layer 1213 and the 5th semiconductor layer 1215 to the 8th semiconductor layer 1218 of the K-1th marking area 1202, and the 3rd semiconductor layer 1213 and the 5th semiconductor layer 1215 to the 7th semiconductor layer 1217 are removed from the K+1th marking area 1204, thereby effectively improving the signal strength of the Kth marking area 1203 detected during exposure alignment, so that the signal strength of the positioning signal is increased and the noise is not obvious, thereby significantly reducing the risk of position deviation during wafer alignment, thereby ensuring the accuracy and reliability of wafer alignment.

[0064] In an optional embodiment, a UT1500 lithography machine is used in the manufacturing process of a 1700V FRD chip. In the wafer structure 1, N is 33, and the fine alignment area 121 includes 33 marking areas, wherein the K value is 9. Specifically, the semiconductor layer structure of the 7th marking area to the 30th marking area is as follows: Figure 8 As shown. In the figure, the numbers in the table on the lower right indicate the mark width of the current layer precision alignment pattern 1221; the gray area with numbers indicates that the layer is a dark field area during exposure and has a groove-shaped cross structure; the white area with numbers indicates that the layer is a bright field area during exposure and has an upward convex cross structure; the gray area without numbers indicates that the current layer is a dark field area during exposure and the layer is retained; the white area without numbers indicates that the current layer is a bright field area during exposure and the layer is etched. Figures 9 to 11 After testing the above wafer structure, it was found that compared with the existing technology, the amount of silicon chips was effectively curbed, the positioning signal strength of the alignment mark detection was significantly increased, and the noise signal strength was effectively reduced, so that the full inspection rate of the wafer structure was reduced from 39.58% in the existing technology to 5.23%, and the offset rework rate during exposure positioning was reduced from 3.44% to 0.43%.

[0065] In the wafer structure 1 provided in this embodiment, the precision alignment area 121 is divided into N marking areas, the marking area has multiple semiconductor layers, and a precision alignment pattern is arranged in at least one semiconductor layer in each marking area. The precision alignment pattern in the first semiconductor layer 1211 forms an alignment mark. When in use, the marking area with the best positioning effect can be judged according to the scanning intensity of the positioning signal of each marking area, thereby realizing effective alignment and positioning of the wafer. The K-1 marking area 1202 to the K marking area 1203 have specific structures among the N marking areas, and the thick aluminum layer of the K marking area 1203 is retained during the exposure and etching process, which effectively reduces the precipitation of silicon chips and thus reduces the interference to the positioning signal. The 3rd semiconductor layer 1213 and the 5th semiconductor layer 1215 to the 8th semiconductor layer 1218 of the K-1 marking area 1202 are provided with precise alignment patterns aligned along the first direction. The 3rd semiconductor layer 1213 and the 5th semiconductor layer 1215 to the 7th semiconductor layer 1217 are removed from the K+1 marking area 1204, which reduces the intensity of the clutter signal and improves the intensity of the positioning signal, thereby significantly reducing the risk of position deviation during wafer alignment, ensuring the accuracy and reliability of wafer alignment, effectively reducing the rework rate and raw material consumption during the exposure process, saving production costs, and ensuring product quality. It has extremely high practical and promotion value.

[0066] Embodiment 2

[0067] This embodiment provides a method for preparing a wafer structure 1, which is used to manufacture any wafer structure 1 in the first embodiment, referring to Fig.12 The method for preparing the wafer structure 1 of this embodiment includes steps S1 to S5.

[0068] Step S1: providing a wafer sample having a first semiconductor layer. Specifically, a precision alignment pattern is provided in the first semiconductor layer 1211 of the wafer sample, and the first semiconductor layer 1211 is an alignment layer, wherein the precision alignment pattern is an alignment mark, and optionally, the wafer sample also has N mark areas divided along the second direction.

[0069] Step S2: forming a second semiconductor layer on the first semiconductor layer.

[0070] Step S3: coating photoresist on the second semiconductor layer, and performing development and exposure. Specifically, a suitable mask can be provided according to the specific structure of the wafer structure 1 in the first embodiment for development and exposure, so as to form a corresponding precise alignment pattern in the current semiconductor layer.

[0071] Step S4: etching and cleaning the exposed second semiconductor layer to form a second semiconductor layer with a precise alignment pattern.

[0072] Step S5: The third to Mth semiconductor layers having a precise alignment pattern are sequentially formed on the second semiconductor layer 1212. Specifically, referring to steps S2 to S4, the third semiconductor layer 1213 is formed on the second semiconductor layer 1212, and after developing, exposing and etching, the third semiconductor layer 1213 having a precise alignment pattern is formed. Similarly, referring to the above steps, the fourth semiconductor layer 1214 to the Mth semiconductor layer are formed. Optionally, M is 8, and the third to eighth semiconductor layers 1218 having a precise alignment pattern are sequentially formed on the second semiconductor layer 1212.

[0073] In an optional embodiment, the value of M is 8, and the N marking areas formed also include the K-1th marking area 1202 to the K+1th marking area 1204 in the first embodiment. Among them, the K-1th marking area 1202 includes the 1st semiconductor layer 1211 to the 8th semiconductor layer 1218, and the second type of graphics are arranged in the 3rd semiconductor layer 1213 and the 5th semiconductor layer 1215 to the 8th semiconductor layer 1218 of the K-1th marking area 1202; the Kth marking area 1203 includes the 1st semiconductor layer 1211 to the 4th semiconductor layer 1214, the 6th semiconductor layer 1216, and the 8th semiconductor layer 1218, and the first type of graphics or the second type of graphics are arranged in the first semiconductor layer 1211 of the Kth marking area 1203; the K+1th marking area 1204 includes the 1st semiconductor layer 1211 to the 2nd semiconductor layer 1212, the 4th semiconductor layer 1214 and the 8th semiconductor layer 1218, and the first type of graphics or the second type of graphics are arranged in the first semiconductor layer 1211 of the K+1th area.

[0074] In an optional embodiment, the sixth semiconductor layer 1216 is a thick aluminum layer, which can be deposited on the surface of the wafer specimen by a magnetron sputtering process. Optionally, the material of the thick aluminum layer is a silicon-aluminum alloy containing 1% or about 1% silicon, and the thickness of the thick aluminum layer is 4μm or other suitable thickness.

[0075] The method for preparing the wafer structure 1 provided in this embodiment is used to manufacture the wafer structure 1 in the first embodiment, and therefore also has the beneficial effects of the first embodiment.

[0076] The above embodiments are merely illustrative of the principles and effects of the present application and are not intended to limit the present application. Anyone familiar with the technology may modify, change or combine the above embodiments without violating the spirit and scope of the present application. Therefore, all equivalent modifications or changes made by a person of ordinary skill in the art without departing from the spirit and technical ideas disclosed in the present application shall still be covered by the claims of the present application.

Claims

1. A wafer structure, characterized in that: The wafer structure includes a chip region and a positioning region located at the periphery of the chip region, wherein the positioning region includes a fine alignment region, and the fine alignment region includes M semiconductor layers sequentially stacked along a first direction, and are respectively recorded as the first to the Mth semiconductor layers along the first direction; wherein the first direction is the thickness direction of the wafer structure, and M is a positive integer greater than 5; Looking down at the wafer structure along the first direction, the fine alignment area is in a strip structure, and the extension direction of the strip structure of the fine alignment area is the second direction. The fine alignment area is divided into N marking areas along the second direction, and are respectively recorded as the first to Nth marking areas along the second direction, wherein N is a positive integer greater than 3, and a fine alignment pattern is provided in at least one semiconductor layer of each of the marking areas, and the first semiconductor layer is an alignment layer, and the fine alignment pattern in the first semiconductor layer is an alignment mark.

2. The wafer structure according to claim 1, characterized in that: The value of M is 8, and the fine alignment area includes the 1st to 8th semiconductor layers stacked in sequence along the first direction, wherein the 2nd to 4th semiconductor layers are material injection layers, the 5th semiconductor layer is a polysilicon layer, the 6th semiconductor layer is a thick aluminum layer, and the 7th semiconductor layer and the 8th semiconductor layer are passivation layers.

3. The wafer structure according to claim 1, characterized in that: The precise alignment pattern is in a cross-shaped structure, including a first type of pattern and a second type of pattern, wherein the first type of pattern is an upward convex cross structure, and the second type of pattern is a grooved cross structure.

4. The wafer structure according to claim 3, characterized in that: The cross-shaped structure of the precise alignment pattern has four rectangular protrusions, and the width of the rectangular protrusions is recorded as the mark width, and the value of the mark width is 1.5 μm to 6 μm.

5. The wafer structure according to claim 4, characterized in that: M takes a value of 8, and there is a K-1th marking area among the N marking areas; the K-1th marking area includes the 1st to 8th semiconductor layers, and the second type of graphics are arranged in the 3rd semiconductor layer and the 5th to 8th semiconductor layers of the K-1th marking area; wherein K is a positive integer less than N.

6. The wafer structure according to claim 5, characterized in that: In the K-1th marking region, the second type patterns of the third semiconductor layer and the second type patterns of the fifth to eighth semiconductor layers are aligned along the first direction.

7. The wafer structure according to claim 5, characterized in that: The N marking areas also include a Kth marking area and a K+1th marking area; and, The Kth marking region includes the first to fourth semiconductor layers and the sixth and eighth semiconductor layers, and the first semiconductor layer of the Kth marking region is provided with the first type of pattern or the second type of pattern; The K+1th marking region includes the first to second semiconductor layers, the fourth semiconductor layer and the eighth semiconductor layer, and the first type of pattern or the second type of pattern is arranged in the first semiconductor layer of the K+1th region.

8. The wafer structure according to claim 7, characterized in that: In the first semiconductor layer of the Kth mark region, the mark width of the precise alignment pattern is a first width; In the third semiconductor layer and the fifth to eighth semiconductor layers of the K-1th region, the mark width of the second type of graphics is the second width.

9. The wafer structure according to claim 8, characterized in that: The first width is 2.5 μm or 5 μm, and the second width is 3 μm.

10. A method for preparing a wafer structure, used to manufacture the wafer structure according to any one of claims 1 to 9, characterized in that: The following steps are involved: Providing a wafer sample having a first semiconductor layer, wherein a precision alignment pattern is provided in the first semiconductor layer; forming a second semiconductor layer on the first semiconductor layer; Applying photoresist on the second semiconductor layer and performing development and exposure; Etching and cleaning the exposed second semiconductor layer to form a second semiconductor layer having a precise alignment pattern; The third to Mth semiconductor layers having precise alignment patterns are sequentially formed on the second semiconductor layer.

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