Substrate processing method for improving imaging quality of infrared focal plane hybrid chip

Abstract

The invention discloses a substrate processing method for improving the imaging quality of an infrared focal plane hybrid chip, and belongs to the technical field of substrate processing. The infrared focal plane hybrid chip is prepared from an array chip and a silicon readout circuit through inverted interconnection of indium columns, an epitaxial layer, a substrate epitaxial interface and a substrate are sequentially arranged above the indium columns in the first direction, and the method comprises the following steps that S1, the substrate is thinned, and degumming and dewaxing treatment is carried out; s2, forming a protective layer on the electrode of the silicon readout circuit; s3, adhering the treated chip and the accompanying chip to a glass substrate, and removing the thinned substrate through chemical mechanical polishing treatment; and S4, removing the epitaxial layer with a set thickness close to the epitaxial interface of the substrate by adopting chemical polishing treatment, and cleaning. The technical scheme has the beneficial effects that the tellurium-zinc-cadmium substrate is removed through chemical mechanical polishing, the loss rate is reduced, the problem of uneven corrosion is solved, the epitaxial material close to the epitaxial interface of the substrate is removed through chemical polishing, and the imaging quality is improved.

Description

Technical Field

[0001] The invention relates to the technical field of substrate processing, and in particular to a substrate processing method for improving the imaging quality of an infrared focal plane hybrid chip. Background Art

[0002] Reference Figure 1 , Figure 2 The infrared focal plane detector hybrid chip is made of an infrared focal plane array chip and a silicon readout circuit 7 through an indium column 6 flip-chip interconnection. In order to improve the reliability of the indium column 6, a filler 4 is usually filled between the chip and the electrode 5 of the silicon readout circuit 7, and the temperature is increased to cure. The infrared focal plane array chip is prepared by epitaxial technology of cadmium zinc telluride substrate, and the thickness of the substrate 1 is hundreds of microns. After the sample chip is thinned by the substrate back side process, a certain thickness of cadmium zinc telluride substrate 1 is reserved, and then the substrate selective etching liquid is used for etching and cleaning to achieve the purpose of completely removing the substrate 1.

[0003] In the prior art, reference Figure 5 , Figure 6 The selective etching process of the substrate will cause uneven corrosion. When the detector component is imaged, corrosion lines are likely to appear on the level map, affecting the imaging quality. If the over-corrosion is serious, the detector component will fail. The HgCdTe (mercury cadmium telluride) wafer of the infrared focal plane manufacturing technology has its inherent growth defects on the surface. The HgCdTe surface produces wavy ripples due to convection, and the substrate etching cannot remove the ripple morphology at the interface. Interdiffusion of components occurs between the substrate 1 and the epitaxial layer 2, and the epitaxial material near the substrate epitaxial interface 3 has a higher impurity concentration and misfit dislocations. Summary of the invention

[0004] The purpose of the present invention is to provide a substrate processing method for improving the imaging quality of an infrared focal plane hybrid chip to solve the above technical problems;

[0005] A substrate processing method for improving the imaging quality of an infrared focal plane hybrid chip, comprising:

[0006] The infrared focal plane hybrid chip is prepared by interconnecting an array chip and a silicon readout circuit through an indium column flip chip, and an epitaxial layer, a substrate epitaxial interface and a substrate are sequentially arranged above the indium column along a first direction, comprising the following steps:

[0007] Step S1, thinning the substrate and performing a de-resin and de-waxing process to obtain a thinned substrate;

[0008] Step S2, forming a protective layer on the electrode of the silicon readout circuit to obtain a processed chip;

[0009] Step S3, bonding the processed chip and companion wafer to a glass substrate, and removing the thinned substrate by chemical mechanical polishing;

[0010] Step S4, removing the epitaxial layer of a set thickness close to the epitaxial interface of the substrate by chemical polishing and cleaning.

[0011] Preferably, the thinned substrate in step S1 is a cadmium zinc telluride substrate, and the thickness of the thinned substrate is 10 μm to 15 μm.

[0012] Preferably, step S2 comprises coating photoresist on the electrode and baking for 15 minutes to form the protective layer.

[0013] Preferably, in step S3, the processed chip and the companion sheet are adhered to the glass substrate by paraffin wax, the companion sheet has the same thickness as the processed chip, and the companion sheet is made of cadmium zinc telluride material.

[0014] Preferably, the chemical mechanical polishing process in step S3 includes:

[0015] A first polishing is performed using aluminum oxide of a first particle size and a sodium hypochlorite solution in a first time period, and then a second polishing is performed using silica sol of a second particle size and a hydrogen peroxide solution in a second time period.

[0016] Preferably, the first time period is 3 minutes, the first particle size is 0.3 μm, the second time period is 30 minutes, and the second particle size is 50 μm.

[0017] Preferably, the chemical polishing treatment in step S4 is to use a bromine-based alcohol solution of a first concentration to remove the epitaxial layer.

[0018] Preferably, the first concentration is 0.1% to 0.5%, and the epitaxial layer is made of mercury cadmium telluride material.

[0019] Preferably, the set thickness in step S4 is 2 μm to 3 μm.

[0020] Preferably, the surface roughness of the array chip is less than 1 nm.

[0021] The beneficial effects of the present invention are: removing the cadmium zinc telluride substrate by chemical mechanical polishing instead of the substrate etching process, reducing the loss rate, solving the problem of uneven corrosion, and removing the epitaxial material close to the epitaxial interface of the substrate by chemical polishing, thereby improving the imaging quality. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 It is the process of removing the substrate in the prior art;

[0023] Figure 2It is a structural diagram of a hybrid chip of an infrared focal plane detector in the prior art;

[0024] Figure 3 It is a step diagram of a substrate processing method for improving the imaging quality of an infrared focal plane hybrid chip according to the present invention;

[0025] Figure 4 is a substrate processing flow chart of an embodiment of the present invention;

[0026] Figure 5 It is a microscopic examination image of the chip surface after processing using the existing technology;

[0027] Figure 6 It is a microscopic picture of the chip surface after processing using existing technology;

[0028] Figure 7 It is a microscopic examination picture of the chip surface after being processed by the present invention;

[0029] Figure 8 It is a microscopic picture of the chip surface after being processed by the present invention.

[0030] In the attached figure: 1, substrate; 2, epitaxial layer; 3, substrate-epitaxial interface; 4, filling glue; 5, electrode; 6, indium column; 7, silicon readout circuit. DETAILED DESCRIPTION

[0031] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0032] It should be noted that, in the absence of conflict, the embodiments of the present invention and the features in the embodiments may be combined with each other.

[0033] The present invention will be further described below in conjunction with the accompanying drawings and specific embodiments, but they are not intended to limit the present invention.

[0034] A substrate processing method for improving the imaging quality of infrared focal plane hybrid chips, such as Figure 1 , Figure 3 As shown, including,

[0035] The infrared focal plane hybrid chip is prepared by flip-chip interconnecting an array chip and a silicon readout circuit 7 through an indium column 6. An epitaxial layer 2, a substrate epitaxial interface 3 and a substrate 1 are sequentially arranged above the indium column 6 along a first direction (arrow A), and the steps include:

[0036] Step S1, thinning the substrate 1 and performing a de-resin and de-waxing process to obtain a thinned substrate;

[0037] Step S2, forming a protective layer on the electrode 5 of the silicon readout circuit 7 to obtain a processed chip;

[0038] Step S3, bonding the processed chip and companion wafer to a glass substrate, and removing the thinned substrate by chemical mechanical polishing;

[0039] Step S4, using chemical polishing to remove the epitaxial layer 2 of a set thickness near the substrate epitaxial interface 3 and clean it.

[0040] Specifically, the present invention provides a substrate processing method for improving the imaging quality of an infrared focal plane hybrid chip, wherein a cadmium zinc telluride substrate is removed by chemical mechanical polishing instead of a substrate etching process, thereby reducing the loss rate and solving the problem of uneven etching caused by a traditional substrate etching process, and epitaxial materials close to an epitaxial interface of the substrate are removed by chemical polishing, thereby improving the imaging quality.

[0041] The purpose of thinning the substrate 1 is to reduce its thickness to improve the sensitivity and imaging quality of the infrared sensor. When the thickness of the substrate 1 is reduced to a certain extent, it can better transmit infrared light and reduce the attenuation of infrared signals. The degumming and dewaxing treatment is to remove the residue on the surface of the substrate 1 and play a cleaning role.

[0042] Forming a protection layer on the electrode 5 of the silicon readout circuit 7 can prevent damage to the electrode 5 during subsequent processing, protect the electrode 5 from being affected by chemical treatment or mechanical operation, and help improve the stability and reliability of the final chip.

[0043] Chemical mechanical polishing is used to remove the substrate 1, replacing the substrate etching process, reducing the loss rate of the chip substrate etching removal process and solving the problem of uneven etching. Chemical polishing is used to remove the epitaxial layer 2 of a set thickness to improve the imaging quality, obtain a flat, low-roughness surface, reduce the surface reflectivity, and improve the back transmittance of the back-illuminated infrared detector.

[0044] In a preferred embodiment, the thinned substrate in step S1 is a cadmium zinc telluride substrate, and the thickness of the thinned substrate is 10 μm to 15 μm.

[0045] Specifically, a backside thinning process is used to thin the CdZnTe substrate to a target thickness of 10 μm to 15 μm, ensuring that the detector's performance reaches its optimal state and improving imaging clarity and the detector's overall efficiency.

[0046] Thinning the CdZnTe substrate can reduce the substrate's absorption and scattering of infrared light and improve the light transmittance of the infrared focal plane hybrid chip. The thinned substrate can effectively reduce the loss in the optical path and improve the overall efficiency of the optical system.

[0047] The thinner substrate 1 can better match the thermal management system of the readout circuit and reduce the impact of heat accumulation on the detector performance.

[0048] The thinned substrate 1 can reduce the propagation time of the signal in the substrate 1 and improve the response speed and real-time imaging capability of the detector.

[0049] In subsequent processing steps, such as chemical mechanical polishing and chemical polishing, less material is removed, which makes processing easier and helps to achieve a flatter and smoother surface.

[0050] In a preferred embodiment, step S2 includes coating photoresist on the electrode 5 and baking it for 15 minutes to form a protective layer.

[0051] Specifically, the photoresist layer plays a role in protecting the electrode 5 from chemical corrosion, physical wear and high temperature environment in the subsequent processing steps. A good photoresist protection layer can reduce defects generated in the subsequent deposition or etching process, such as contamination, missing or irregular shape of the electrode 5 surface, improve the processing accuracy of the infrared focal plane hybrid chip, and thus improve the quality of the final imaging.

[0052] The protective layer helps to maintain the structure and shape of the electrode 5, avoiding damage to the electrode 5 when removing the substrate 1 and the epitaxial layer 2, thereby improving the accuracy and consistency of the processing process.

[0053] The protective layer can improve the adhesion between the electrode and other materials (such as glass substrate), ensuring the reliability and stability of the final chip.

[0054] After the protective layer is formed, the process of removing the substrate 1 and the epitaxial layer 2 can be simplified because the electrode area will be effectively isolated, reducing unnecessary interference and damage.

[0055] In a preferred embodiment, in step S3, the processed chip and the companion sheet are adhered to the glass substrate by paraffin wax, the companion sheet has the same thickness as the processed chip, and the companion sheet is made of cadmium zinc telluride material.

[0056] Specifically, paraffin wax is used as a temporary adhesive to fix the positions of the companion wafer and the chip on the substrate.

[0057] The companion wafer provides the necessary mechanical support during chip processing to prevent the chip from being deformed or damaged during subsequent processing steps. The same thickness ensures the consistency of mechanical support, thus avoiding stress concentration problems caused by thickness differences.

[0058] The companion film is made of a substrate material with the same thermal expansion coefficient as the chip material to reduce stress and deformation caused by temperature changes, thereby improving imaging quality.

[0059] In a preferred embodiment, the chemical mechanical polishing process in step S3 includes:

[0060] A first polishing is performed using aluminum oxide of a first particle size and a sodium hypochlorite solution in a first time period, and then a second polishing is performed using silica sol of a second particle size and a hydrogen peroxide solution in a second time period;

[0061] The first time period is 3 minutes, the first particle size is 0.3 μm, the second time period is 30 minutes, and the second particle size is 50 μm.

[0062] Specifically, the first step of rough polishing was performed using aluminum oxide with a particle size of 0.3 μm and sodium hypochlorite solution for 3 minutes, and then the second step of fine polishing was performed using silica sol with a particle size of 50 μm and hydrogen peroxide solution for 30 minutes until the mirror surface was smooth and scratch-free.

[0063] Alumina particles with a particle size of 0.3μm are relatively large and can effectively remove larger surface defects and irregular surface roughness to reduce macroscopic unevenness and obvious scratches on the material surface.

[0064] Silica sol with a particle size of 50μm is very fine and can effectively remove tiny surface defects and fine scratches left in the rough polishing stage. Fine-grained polishing materials can achieve a higher finish and make the surface reach mirror level. The surface quality is gradually improved from macro to micro. Rough polishing removes large-scale irregularities, and fine polishing ensures the removal of tiny defects, ultimately achieving a high-smooth mirror effect.

[0065] In a preferred embodiment, the chemical polishing treatment in step S4 is to remove the epitaxial layer 2 using a bromine-based alcohol solution of a first concentration;

[0066] The first concentration is 0.1% to 0.5%, and the epitaxial layer 2 is made of mercury cadmium telluride material;

[0067] In step S4 , the thickness is set to 2 μm to 3 μm.

[0068] Specifically, by precisely controlling the concentration of bromohydrin, the removal rate and effect can be finely adjusted to control the thickness of the epitaxial layer 2 and preserve the performance and morphology of the substrate. The selective corrosion characteristics of bromohydrin make it suitable for processing cadmium zinc telluride materials without affecting other materials.

[0069] Chemical polishing can effectively remove surface defects and unevenness, ensure the smoothness of the epitaxial layer 2, and thus improve the imaging quality of the infrared focal plane hybrid chip. Improving the surface smoothness helps to reduce image distortion and enhance the accuracy of imaging.

[0070] Through precise chemical polishing control, 2μm to 3μm of unnecessary epitaxial material can be evenly removed to ensure the consistency of the required thickness.

[0071] The selective dissolving ability of the bromoalcohol helps to remove the epitaxial layer 2 without damaging the substrate, thus preserving the original characteristics and performance of the substrate. This selective removal helps to maintain the overall performance of the final device.

[0072] In a preferred embodiment, the surface roughness of the array chip is less than 1 nm.

[0073] Specifically, surface roughness directly affects the optical uniformity of the chip. Higher surface roughness can cause light scattering and interference effects, thus affecting the imaging clarity and sensitivity of the infrared detector. In infrared focal plane hybrid chips, surface roughness affects the quality of electrical contact. Surface unevenness may lead to poor contact, affecting signal transmission and the electrical performance of the detector.

[0074] Surface roughness less than 1nm helps reduce light scattering and interference, thereby improving imaging quality. A smoother surface ensures that light passes through the chip in a more consistent manner, improving detection accuracy and image clarity.

[0075] A smooth surface can improve the detector's response speed and signal stability, because low surface roughness can reduce signal noise and improve signal quality.

[0076] Chemical mechanical polishing is used to treat the substrate surface to achieve the desired ultra-low surface roughness. Surface irregularities are removed through a combination of chemical and mechanical action to achieve an extremely smooth surface. The chemical reaction helps dissolve and remove surface material, while mechanical polishing physically flattens the surface.

[0077] After chemical mechanical polishing and chemical polishing, a flat surface with a low roughness of less than 1 nm is obtained, which reduces the surface reflectivity and improves the back transmittance of the back-illuminated infrared detector.

[0078] Reference Figure 4 , using the array chip as a sample chip for substrate processing, the specific steps are as follows:

[0079] First, a cadmium zinc telluride substrate with a thickness of 10 μm to 15 μm is reserved by back thinning;

[0080] Then, glue is applied on the electrodes 5 around the array chip to protect it;

[0081] Secondly, the cadmium zinc telluride substrate is completely removed by CMP (chemical mechanical polishing);

[0082] Then, the epitaxial layer 2 with a thickness of 2 μm to 3 μm is removed by CP (chemical polishing);

[0083] Finally, clean it.

[0084] Specifically, coating the electrodes 5 around the array chip with glue can prevent the electrodes 5 from being damaged during the subsequent polishing process. Protecting the electrodes 5 is the key to ensuring the reliability of electrical connection, and preventing the electrodes 5 from being damaged and affecting the working performance of the final chip.

[0085] CMP can evenly remove substrate material, reduce surface roughness, and eliminate surface defects that may affect imaging quality. Through precise chemical mechanical polishing, the substrate surface is ensured to be smooth, which helps to improve the clarity of infrared images.

[0086] When removing the epitaxial layer of 2μm to 3μm, chemical polishing can remove surface unevenness and stress release layer, thereby improving the flatness and consistency of the chip. This flatness directly affects the imaging performance of the focal plane array and reduces image distortion and aberration.

[0087] The final cleaning process removes chemical residues and tiny particles generated during the processing, ensuring that the chip surface is free of contamination.

[0088] More specifically, during the processing, the coating of the electrode 5 with glue can effectively protect the array chip and avoid damage when the substrate 1 is removed.

[0089] By removing the substrate 1 by CMP and the epitaxial layer 2 by CP, the flatness and quality of the chip surface can be improved, and the loss rate of the chip substrate etching and removal process can be reduced.

[0090] By precisely controlling the concentration of bromohydrin, the removal rate and effect can be finely adjusted to control the thickness of the removed epitaxial layer 2. The selective corrosion characteristics of bromohydrin make it suitable for processing cadmium zinc telluride materials without affecting other materials. Removing excess substrate 1 and epitaxial layer 2 helps optimize the optoelectronic performance of the chip, especially in optoelectronic devices.

[0091] Reducing material thickness and unnecessary layers helps improve chip stability and long-term reliability, improves imaging quality, and increases backside transmittance of back-illuminated infrared detectors.

[0092] The uneven etching phenomenon caused by the substrate selective etching process is avoided, the imaging quality is not affected, the epitaxial material close to the substrate epitaxial interface 3 is removed, and a high impurity concentration and misfit dislocation are avoided.

[0093] Figure 6 a shows the residual hole defects of corrosion under high magnification. Figure 6 b shows the macroscopic corrugated steps of the HgCdTe epitaxial layer under high magnification. Figure 6 c. Figure 6 d corresponds to Figure 6 a. Figure 6 b: Hole defects and ripple step morphology patterns captured by a white light profilometer.

[0094] Figure 7 This is a microscopic examination image of the chip surface obtained by the present invention. Figure 8 a', Figure 8 b' shows the mirror-smooth chip surface under a high-power microscope. Figure 8 c', Figure 8 d' shows the topography pattern with a roughness of less than 1 nm under white light profilometer.

[0095] In summary, the present application provides a substrate processing method for improving the imaging quality of an infrared focal plane hybrid chip, by replacing the substrate etching process with a chemical mechanical polishing process to remove cadmium zinc telluride, thereby reducing the loss rate of the chip substrate etching removal process and solving the problem of uneven corrosion; by removing the epitaxial layer of 2μm to 3μm near the interface through chemical polishing, the imaging quality is improved, and the back transmittance of the back-illuminated infrared detector is improved.

[0096] The above description is only a preferred embodiment of the present invention, and does not limit the implementation mode and protection scope of the present invention. For those skilled in the art, it should be aware that all solutions obtained by equivalent substitutions and obvious changes made using the description and illustrations of the present invention should be included in the protection scope of the present invention.

Claims

1. A substrate processing method for improving the imaging quality of an infrared focal plane hybrid chip, characterized in that: An infrared focal plane hybrid chip is prepared by flip-chip interconnecting an array chip and a silicon readout circuit (7) through an indium column (6), wherein an epitaxial layer (2), a substrate epitaxial interface (3) and a substrate (1) are sequentially arranged above the indium column (6) along a first direction, and the process comprises the following steps: Step S1, thinning the substrate (1) and performing a de-bonding and de-waxing process to obtain a thinned substrate; Step S2, forming a protective layer on the electrode (5) of the silicon readout circuit (7) to obtain a processed chip; Step S3, bonding the processed chip and companion wafer to a glass substrate, and removing the thinned substrate by chemical mechanical polishing; Step S4, using chemical polishing to remove the epitaxial layer (2) of a set thickness close to the substrate epitaxial interface (3) and clean it.

2. The substrate processing method for improving the imaging quality of infrared focal plane hybrid chip according to claim 1, characterized in that: The thinned substrate in step S1 is a cadmium zinc telluride substrate, and the thickness of the thinned substrate is 10 μm to 15 μm.

3. The substrate processing method for improving the imaging quality of infrared focal plane hybrid chip according to claim 1, characterized in that: Step S2 includes coating photoresist on the electrode (5) and baking for 15 minutes to form the protective layer.

4. The substrate processing method for improving the imaging quality of an infrared focal plane hybrid chip according to claim 1, characterized in that: In step S3, the processed chip and the companion sheet are adhered to the glass substrate by paraffin wax, the companion sheet has the same thickness as the processed chip, and the companion sheet is made of cadmium zinc telluride material.

5. The substrate processing method for improving the imaging quality of infrared focal plane hybrid chip according to claim 1, characterized in that: The chemical mechanical polishing process in step S3 includes: A first polishing is performed using aluminum oxide of a first particle size and a sodium hypochlorite solution in a first time period, and then a second polishing is performed using silica sol of a second particle size and a hydrogen peroxide solution in a second time period.

6. The substrate processing method for improving the imaging quality of an infrared focal plane hybrid chip according to claim 5, characterized in that: The first time period is 3 minutes, the first particle size is 0.3 μm, the second time period is 30 minutes, and the second particle size is 50 μm.

7. The substrate processing method for improving the imaging quality of an infrared focal plane hybrid chip according to claim 1, characterized in that: The chemical polishing treatment in step S4 is to remove the epitaxial layer (2) using a bromine-based alcohol solution of a first concentration.

8. The substrate processing method for improving the imaging quality of an infrared focal plane hybrid chip according to claim 7, characterized in that: The first concentration is 0.1% to 0.5%, and the epitaxial layer (2) is made of mercury cadmium telluride material.

9. The substrate processing method for improving the imaging quality of an infrared focal plane hybrid chip according to claim 1, characterized in that: The thickness in step S4 is set to be 2 μm to 3 μm.

10. The substrate processing method for improving the imaging quality of an infrared focal plane hybrid chip according to claim 1, characterized in that: The surface roughness of the array chip is less than 1 nm.

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