Semiconductor device and preparation method thereof

Abstract

The invention relates to a semiconductor device and a preparation method thereof. The semiconductor device comprises a substrate, a first step semiconductor layer, a second step semiconductor layer and a gate structure, the first step semiconductor layer comprises a first type high semiconductor column, a second type step semiconductor column and a first type low semiconductor column, and the second step semiconductor layer comprises a first type semiconductor layer and a first type step semiconductor layer. When the device is turned off, the first type high semiconductor column and the second type stepped semiconductor column as well as the second type stepped semiconductor column and the first type low semiconductor column form two reversely biased PN junctions, so that the width of a depletion layer is increased, and the breakdown voltage of the semiconductor device is enhanced; meanwhile, the first type step semiconductor layer in the first step semiconductor layer and the second step semiconductor layer is arranged to be of a step structure, and the gate structure is arranged on the partial top surface of the first step and the top surface of the third step, so that a plane channel in a traditional device can be converted into a vertical channel, and the resistance of a JFET region is reduced.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor device and a method for preparing the same. Background Art

[0002] Super Junction Metal-Oxide-Semiconductor Field-Effect Transistor (SJ MOSFET) can modulate the electric field inside the device by setting P-type and N-type columns, thereby breaking through the "silicon limit" relationship between the specific on-resistance and withstand voltage of traditional power devices. In addition, the parasitic capacitance of the super junction metal-oxide semiconductor field effect transistor is small, so the specific on-resistance is low, making the super junction metal-oxide semiconductor field effect transistor widely used in power semiconductors.

[0003] However, since the channel of the JFET region in the super junction metal-oxide semiconductor field effect transistor is a planar channel, the resistance value of the JFET region is too large, resulting in a decrease in the power of the semiconductor device and a reduction in the electrical properties of the semiconductor device. Summary of the invention

[0004] The purpose of this application is to provide a semiconductor device and a method for preparing the same, which solves the problem that the resistance value of the JFET region is too large, resulting in a decrease in the power of the semiconductor device, and improves the electrical properties of the semiconductor device. To achieve the purpose of this application, this application provides the following technical solutions:

[0005] In a first aspect, the present application provides a semiconductor device, comprising:

[0006] substrate;

[0007] A first stepped semiconductor layer, located on the substrate, comprises a first-type high semiconductor column, a second-type stepped semiconductor column and a first-type low semiconductor column distributed along a first direction parallel to the substrate, wherein the top surface of the first-type high semiconductor column is higher than the top surface of the first-type low semiconductor column, and the second-type stepped semiconductor column comprises two groups of first steps and second steps consisting of interconnected horizontal planes and vertical planes;

[0008] The second stepped semiconductor layer includes a first-type semiconductor layer and a first-type stepped semiconductor layer, wherein the first-type semiconductor layer covers the top surface of the first-type high semiconductor column and part of the top surface of the second-type stepped semiconductor column, the first-type stepped semiconductor layer covers the horizontal plane of the second step and the top surface of the first-type low semiconductor column, and the first-type stepped semiconductor layer includes a third step and a fourth step formed by interconnected horizontal planes and vertical planes;

[0009] The gate structure is located on a portion of the top surface of the first step and the top surface of the third step, and includes a gate dielectric layer and a gate conductive layer covered by the gate dielectric layer.

[0010] The semiconductor device of the present application includes a substrate, a first-step semiconductor layer, a second-step semiconductor layer and a gate structure, the first-step semiconductor layer includes a first-type high semiconductor column, a second-type stepped semiconductor column and a first-type low semiconductor column distributed along a first direction parallel to the substrate, the second-step semiconductor layer includes a first-type semiconductor layer and a first-type stepped semiconductor layer, and the gate structure is located on a partial top surface of the first step and a top surface of the third step, and includes a gate dielectric layer and a gate conductive layer covered by the gate dielectric layer. By setting a first-type high semiconductor column, a second-type stepped semiconductor column and a first-type low semiconductor column, when the device is turned off, the first-type high semiconductor column and the second-type stepped semiconductor column, as well as the second-type stepped semiconductor column and the first-type low semiconductor column can form two reverse-biased PN junctions to increase the width of the depletion layer, thereby enhancing the breakdown voltage of the semiconductor device. At the same time, the first-type stepped semiconductor layer in the first-step semiconductor layer and the second-step semiconductor layer are set to a stepped structure, and the gate structure is set on a partial top surface of the first step and the top surface of the third step. The planar channel in the traditional device can be converted into a vertical channel, thereby reducing the resistance of the JFET region, increasing the electrical properties of the semiconductor device, reducing the size of the gate structure, and improving the space utilization of the semiconductor device.

[0011] In one embodiment, the top surface of the third step is flush with the top surface of the first step.

[0012] In one embodiment, it also includes:

[0013] A first doping region, located on a top surface of the second stepped semiconductor layer, wherein a top surface of the first doping region is flush with a top surface of the gate structure, and comprises a first type doping region and a second type doping region distributed along a first direction;

[0014] The second doping region is located on the top surface of the fourth step, and the top surface of the second doping region is flush with the top surface of the third step, and includes a second type injection region and a first type injection region distributed along the first direction.

[0015] In one embodiment, a top surface of the second doped region is flush with a bottom surface of the gate structure.

[0016] In one embodiment, the first type is P type, and the second type is N type; or

[0017] The first type is N type, and the second type is P type.

[0018] In a second aspect, the present application further provides an electronic device, including:

[0019] The semiconductor device according to any one of the above embodiments.

[0020] The electronic device of the present application comprises: a semiconductor device of any one of the above embodiments. By setting a first-type high semiconductor column, a second-type stepped semiconductor column and a first-type low semiconductor column, when the device is turned off, the first-type high semiconductor column and the second-type stepped semiconductor column, and the second-type stepped semiconductor column and the first-type low semiconductor column can form two reverse-biased PN junctions to increase the width of the depletion layer, thereby enhancing the breakdown voltage of the semiconductor device, and at the same time, the first-type stepped semiconductor layer in the first-step semiconductor layer and the second-step semiconductor layer is set to a stepped structure, and the gate structure is set on the top surface of part of the first step and the top surface of the third step, so that the planar channel in the traditional device can be converted into a vertical channel, thereby reducing the resistance of the JFET region, increasing the electrical properties of the semiconductor device, and reducing the size of the gate structure, thereby improving the space utilization of the semiconductor device.

[0021] In a third aspect, the present application further provides a method for preparing a semiconductor device, comprising:

[0022] providing a substrate;

[0023] A first stepped semiconductor layer is formed on the substrate, wherein the first stepped semiconductor layer includes a first-type high semiconductor column, a second-type stepped semiconductor column and a first-type low semiconductor column distributed along a first direction parallel to the substrate, wherein the top surface of the first-type high semiconductor column is higher than the top surface of the first-type low semiconductor column, and the second-type stepped semiconductor column includes two groups of first steps and second steps consisting of interconnected horizontal planes and vertical planes;

[0024] A second stepped semiconductor layer and a gate structure are formed, wherein the second stepped semiconductor layer includes a first-type semiconductor layer and a first-type stepped semiconductor layer, wherein the first-type semiconductor layer covers the top surface of the first-type high semiconductor column and part of the top surface of the second-type stepped semiconductor column, wherein the first-type stepped semiconductor layer covers the horizontal plane of the second step and the top surface of the first-type low semiconductor column, and the first-type stepped semiconductor layer includes a third step and a fourth step formed by interconnected horizontal planes and vertical planes, wherein the gate structure is located on part of the top surface of the first step and the top surface of the third step, and wherein the gate structure includes a gate dielectric layer and a gate conductive layer covered by the gate dielectric layer.

[0025] The preparation method of the semiconductor device of the present application includes providing a substrate, and then forming a first stepped semiconductor layer on the substrate, wherein the first stepped semiconductor layer includes a first-type high semiconductor column, a second-type stepped semiconductor column and a first-type low semiconductor column distributed along a first direction parallel to the substrate, wherein the top surface of the first-type high semiconductor column is higher than the top surface of the first-type low semiconductor column, and the second-type stepped semiconductor column includes two groups of first steps and second steps composed of interconnected horizontal planes and vertical planes, and finally forming a second stepped semiconductor layer and a gate structure, wherein the second stepped semiconductor layer includes a first-type semiconductor layer and a first-type stepped semiconductor layer, the first-type semiconductor layer covers the top surface of the first-type high semiconductor column and part of the top surface of the second-type stepped semiconductor column, the first-type stepped semiconductor layer covers the horizontal plane of the second step and the top surface of the first-type low semiconductor column, and the first-type stepped semiconductor layer includes a third step and a fourth step composed of interconnected horizontal planes and vertical planes, the gate structure is located on part of the top surface of the first step and the top surface of the third step, and the gate structure includes a gate dielectric layer and a gate conductive layer covered by the gate dielectric layer. By setting a first-type high semiconductor column, a second-type stepped semiconductor column and a first-type low semiconductor column, when the device is turned off, the first-type high semiconductor column and the second-type stepped semiconductor column, as well as the second-type stepped semiconductor column and the first-type low semiconductor column can form two reverse-biased PN junctions to increase the width of the depletion layer, thereby enhancing the breakdown voltage of the semiconductor device. At the same time, the first-type stepped semiconductor layer in the first-step semiconductor layer and the second-step semiconductor layer are set to a stepped structure, and the gate structure is set on a partial top surface of the first step and the top surface of the third step. The planar channel in the traditional device can be converted into a vertical channel, thereby reducing the resistance of the JFET region, increasing the electrical properties of the semiconductor device, reducing the size of the gate structure, and improving the space utilization of the semiconductor device.

[0026] In one embodiment, forming a first stepped semiconductor layer on the substrate includes:

[0027] forming a lightly doped epitaxial layer on the substrate;

[0028] Forming the first-type high semiconductor pillars and initial first-type low semiconductor pillars in the lightly doped epitaxial layer, wherein the first-type high semiconductor pillars and initial first-type low semiconductor pillars circumferentially surround the lightly doped epitaxial layer;

[0029] forming a covering lightly doped epitaxial layer on top surfaces of the lightly doped epitaxial layer, the first-type tall semiconductor pillars and the initial first-type low semiconductor pillars;

[0030] Etching the covering lightly doped epitaxial layer to form a groove, wherein the bottom surface of the groove is flush with the top surface of the initial first-type low semiconductor column;

[0031] A second-type stepped semiconductor column having the first step and the second step is formed in the lightly doped epitaxial layer, and a first-type lower semiconductor column is formed in the initial first-type lower semiconductor column to form the first stepped semiconductor layer.

[0032] In one embodiment, the forming of the second stepped semiconductor layer comprises:

[0033] forming a first-type semiconductor layer and an initial first-type stepped semiconductor layer in the covering lightly doped epitaxial layer having the groove;

[0034] A first-type stepped semiconductor layer having the third step and the fourth step is formed in the initial first-type stepped semiconductor layer to form the second stepped semiconductor layer, wherein a top surface of the third step is flush with a top surface of the first step.

[0035] In one embodiment, after forming the second stepped semiconductor layer and the gate structure, the method further comprises:

[0036] forming a first doping region on the top surface of the second stepped semiconductor layer, wherein the top surface of the first doping region is flush with the top surface of the gate structure, and the first doping region includes a first-type doping region and a second-type doping region distributed along a first direction;

[0037] A second doped region is formed on the top surface of the horizontal plane of the fourth step, the top surface of the second doped region is flush with the top surface of the third step and the bottom surface of the gate structure, and the second doped region includes a second type injection region and a first type injection region distributed along the first direction. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure or the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure, and for ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0039] Figure 1 is a schematic cross-sectional structure diagram of a semiconductor device provided in an embodiment;

[0040] Figure 2 is a schematic cross-sectional structural diagram of a semiconductor device provided in another embodiment;

[0041] Figure 3 is a schematic cross-sectional structural diagram of a semiconductor device provided in another embodiment;

[0042] Figure 4is a schematic cross-sectional structural diagram of a semiconductor device provided in another embodiment;

[0043] Figure 5 is a flow chart of a method for preparing a semiconductor device provided in another embodiment;

[0044] Figure 6 is a schematic cross-sectional structural diagram of a structure obtained in step S11 in a method for preparing a semiconductor device provided in another embodiment;

[0045] Figure 7 is a schematic cross-sectional structural diagram of a structure obtained in step S12 in a method for preparing a semiconductor device provided in another embodiment;

[0046] Figure 8 is a flow chart of steps S121 to S125 in a method for preparing a semiconductor device provided in another embodiment;

[0047] Fig. 9 is a schematic cross-sectional view of a structure obtained in step S121 in a method for preparing a semiconductor device provided in another embodiment;

[0048] Fig.10 is a schematic cross-sectional structural diagram of a structure obtained in step S1221 in a method for preparing a semiconductor device provided in another embodiment;

[0049] Fig.11 is a schematic cross-sectional structural diagram of a structure obtained in step S1222 of a method for preparing a semiconductor device provided in another embodiment;

[0050] Fig.12 is a schematic cross-sectional structural diagram of a structure obtained in step S1223 in a method for preparing a semiconductor device provided in another embodiment;

[0051] Fig.13 is a schematic cross-sectional view of a structure obtained in step S123 in a method for preparing a semiconductor device provided in another embodiment;

[0052] Fig.14 is a schematic cross-sectional structural diagram of a structure obtained in step S124 in a method for preparing a semiconductor device provided in another embodiment;

[0053] Fig.15 is a schematic cross-sectional structural diagram of a structure obtained in step S125 in a method for preparing a semiconductor device provided in another embodiment;

[0054] Fig.16 is a flow chart of steps S131 to S132 in a method for preparing a semiconductor device provided in another embodiment;

[0055] Fig.17 is a schematic cross-sectional structural diagram of a structure obtained in step S131 in a method for preparing a semiconductor device provided in another embodiment;

[0056] Fig.18 is a schematic cross-sectional structural diagram of a structure obtained in step S133 in a method for preparing a semiconductor device provided in another embodiment;

[0057] Fig.19 is a schematic cross-sectional structural diagram of a structure obtained in step S134 in a method for preparing a semiconductor device provided in another embodiment;

[0058] Fig. 20 is a schematic cross-sectional view of a structure obtained in step S135 in a method for preparing a semiconductor device provided in another embodiment;

[0059] Fig.21 is a schematic cross-sectional view of a structure obtained in step S136 in a method for preparing a semiconductor device provided in another embodiment;

[0060] Fig. 22 It is a flowchart of steps S141 to S142 in a method for preparing a semiconductor device provided in another embodiment.

[0061] Description of Reference Numerals

[0062] 10. substrate; 101. heavily doped epitaxial layer; 102. lightly doped epitaxial layer; 103. covering lightly doped epitaxial layer; 1031. initial covering lightly doped epitaxial layer; 104. epitaxial layer; 20. first stepped semiconductor layer; 201. first type high semiconductor column; 2011. initial first type semiconductor column; 201A. first type semiconductor column; 202. second type stepped semiconductor column; 2021. first step; 2022. second step; 203. first type low semiconductor column; 202A. second type semiconductor column; 2031. initial first type low semiconductor column; 20A. low concentration first stepped semiconductor layer ; 20B, high-concentration first-step semiconductor layer; 30, second-step semiconductor layer; 301, first-type semiconductor layer; 302, first-type stepped semiconductor layer; 3021, third step; 3022, fourth step; 3023, initial first-type stepped semiconductor layer; 40, gate structure; 401, gate dielectric layer; 4011, first gate dielectric layer; 402, gate conductive layer; 4021, initial gate conductive layer; 50, first doped region; 501, first-type doped region; 502, second-type doped region; 60, second doped region; 601, second-type injection region; 602, first-type injection region; 70, groove. DETAILED DESCRIPTION

[0063] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present application are given in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0064] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0065] It should be understood that when an element or layer is referred to as being "on, adjacent to, connected to or coupled to other elements or layers, it may be directly on, adjacent to, connected to or coupled to other elements or layers, or there may be intervening elements or layers. On the contrary, when an element is referred to as being "directly on, directly adjacent to, directly connected to or directly coupled to other elements or layers, there may be no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types and / or parts, these elements, components, regions, layers, doping types and / or parts should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, doping type or part from another element, component, region, layer, doping type or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer, doping type or portion discussed below may be represented as a second element, component, region, layer or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

[0066] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as "under other elements" or "under it" or "under it" will be oriented as being "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0067] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that when the terms "consisting of" and / or "comprising" are used in this specification, the presence of the features, integers, steps, operations, elements and / or parts can be determined, but the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups is not excluded. At the same time, when used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0068] Embodiments of the invention are described herein with reference to cross-sectional views which are schematic diagrams of ideal embodiments (and intermediate structures) of the invention, such that variations in the shapes shown due to, for example, manufacturing techniques and / or tolerances are anticipated. Thus, embodiments of the invention should not be limited to the specific shapes of the regions shown herein, but rather include deviations in shapes due to, for example, manufacturing techniques. For example, an implanted region shown as a rectangle typically has rounded or curved features and / or an implant concentration gradient at its edges rather than a binary change from an implanted region to a non-implanted region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is performed. Thus, the regions shown in the figures are schematic in nature, their shapes do not represent the actual shape of the region of the device, and do not limit the scope of the invention.

[0069] Super Junction Metal-Oxide-Semiconductor Field-Effect Transistor (SJ MOSFET) can modulate the electric field inside the device by setting P-type and N-type columns, thereby breaking through the "silicon limit" relationship between the specific on-resistance and withstand voltage of traditional power devices. In addition, the parasitic capacitance of the super junction metal-oxide semiconductor field effect transistor is small, so the specific on-resistance is low, making the super junction metal-oxide semiconductor field effect transistor widely used in power semiconductors.

[0070] However, since the channel of the JFET region in the super junction metal-oxide semiconductor field effect transistor is a planar channel, the resistance value of the JFET region is too large, resulting in a decrease in the power of the semiconductor device and a reduction in the electrical properties of the semiconductor device.

[0071] The present application embodiment provides a semiconductor device. Figure 1 The semiconductor device may include: a substrate 10 , a first stepped semiconductor layer 20 , a second stepped semiconductor layer 30 and a gate structure 40 .

[0072] The first stepped semiconductor layer 20 is located on the substrate 10, and includes a first-type high semiconductor column 201, a second-type stepped semiconductor column 202, and a first-type low semiconductor column 203 distributed along a first direction parallel to the substrate 10, wherein the top surface of the first-type high semiconductor column 201 is higher than the top surface of the first-type low semiconductor column 203, and the second-type stepped semiconductor column 202 includes two groups of first steps 2021 and second steps 2022 composed of interconnected horizontal planes and vertical planes.

[0073] The second stepped semiconductor layer 30 includes a first-type semiconductor layer 301 and a first-type stepped semiconductor layer 302. The first-type semiconductor layer 301 covers the top surface of the first-type high semiconductor column 201 and part of the top surface of the second-type stepped semiconductor column 202. The first-type stepped semiconductor layer 302 covers the horizontal plane of the second step and the top surface of the first-type low semiconductor column 203. The first-type stepped semiconductor layer 302 includes a third step 3021 and a fourth step 3022 composed of interconnected horizontal planes and vertical planes.

[0074] The gate structure 40 is located on a portion of the top surface of the first step 2021 and the top surface of the third step 3021 , and includes a gate dielectric layer 401 and a gate conductive layer 402 covered by the gate dielectric layer 401 .

[0075] Exemplarily, the substrate 10 may include but is not limited to at least one of a silicon substrate, a gallium nitride (GaN) substrate, and a silicon carbide (SiC) substrate, and the substrate 10 includes a heavily doped epitaxial layer 101 of the second conductivity type located on the substrate 10. Specifically, in the present embodiment, the substrate 10 is a silicon substrate, and the heavily doped epitaxial layer 101 of the second conductivity type is an N-type heavily doped epitaxial layer.

[0076] Exemplarily, the first direction is defined as the direction of the x-axis.

[0077] Exemplarily, the first-type tall semiconductor pillar 201 is a P-type semiconductor pillar, the second-type stepped semiconductor pillar 202 is an N-type semiconductor pillar, and the first-type low semiconductor pillar 203 is a P-type semiconductor pillar.

[0078] Exemplarily, both the first-type semiconductor layer 301 and the first-type stepped semiconductor layer 302 are P-type semiconductor layers. Specifically, in this embodiment, the doping concentration of the second stepped semiconductor layer 30 is greater than the doping concentration of the first-type tall semiconductor pillar 201 .

[0079] For example, the gate dielectric layer 401 may include but is not limited to an oxide layer, and the gate conductive layer 402 may include but is not limited to a polysilicon layer.

[0080] In the embodiment of the present application, a substrate 10, a first stepped semiconductor layer 20, a second stepped semiconductor layer 30 and a gate structure 40 are included. The first stepped semiconductor layer 20 includes a first-type high semiconductor column 201, a second-type stepped semiconductor column 202 and a first-type low semiconductor column 203 distributed along a first direction ox parallel to the substrate. The second stepped semiconductor layer 30 includes a first-type semiconductor layer 301 and a first-type stepped semiconductor layer 302. The gate structure 40 is located on a partial top surface of the first step 2021 and a top surface of the third step 3021, and includes a gate dielectric layer 401 and a gate conductive layer 402 covered by the gate dielectric layer 401. When the device is turned off, the first-type high semiconductor column 201 and the second-type stepped semiconductor column 202, as well as the second-type stepped semiconductor column 202 and the first-type low semiconductor column 203 can form two reverse-biased PN junctions to increase the width of the depletion layer, thereby enhancing the breakdown voltage of the semiconductor device. At the same time, the first-step semiconductor layer 20 and the second-step semiconductor layer 30 are arranged into a stepped structure, and the gate structure is arranged on a partial top surface of the first step 2021 and a top surface of the third step 3021. The planar channel in the traditional device can be converted into a vertical channel, thereby reducing the resistance of the JFET region, increasing the electrical properties of the semiconductor device, and reducing the size of the gate structure 40, thereby improving the space utilization of the semiconductor device.

[0081] In some embodiments, please refer to Figure 1, the top surface of the third step 3021 is flush with the top surface of the first step 2021 .

[0082] As an example, the top surface of the third step 3021 is flush with the top surface of the first step 2021, so that the gate structure 40 can cover the top surfaces of the third step 3021 and the first step 2021 at the same time, thereby converting the planar channel in the traditional device into a vertical channel, thereby reducing the resistance of the JFET region.

[0083] In the embodiment of the present application, the top surface of the third step 3021 is flush with the top surface of the first step 2021 so that the gate structure 40 can cover the top surface of the third step 3021 and the top surface of the first step 2021 at the same time, thereby converting the planar channel in the traditional device into a vertical channel, thereby reducing the resistance of the JFET region.

[0084] In some embodiments, please refer to Figure 1 The semiconductor device also includes: a first doped region 50, located on the top surface of the second stepped semiconductor layer 30, and the top surface of the first doped region 50 is flush with the top surface of the gate structure 40, including a first type doped region 501 and a second type doped region 502 distributed along the first direction ox; a second doped region 60, located on the top surface of the fourth step 3022, and the top surface of the second doped region 60 is flush with the top surface of the third step 3021, including a second type injection region 601 and a first type injection region 602 distributed along the first direction ox.

[0085] As an example, the first-type doping region 501 is a P-type doping region, and the second-type doping region 502 is an N-type doping region. Specifically, in this embodiment, the doping concentrations of the first-type doping region 501 and the second-type doping region 502 are both greater than the doping concentration of the second stepped semiconductor layer 30. The second-type injection region 601 is an N-type doping region, and the first-type injection region 602 is a P-type doping region. Specifically, in this embodiment, the doping concentrations of the second-type injection region 601 and the first-type injection region 602 are both greater than the doping concentration of the second stepped semiconductor layer 30.

[0086] In the embodiment of the present application, the first doping region 50 and the second doping region 60 are set so that when the device is in the on state, carriers flow between the second type doping region 502 in the first doping region 50 and the second type injection region in the second doping region 60, thereby forming an on-current.

[0087] In some embodiments, please refer to Figure 1 , the top surface of the second doping region 60 is flush with the bottom surface of the gate structure 40 .

[0088] As an example, the top surface of the second doping region 60 is flush with the bottom surface of the gate structure 40 so as to convert a conventional device channel into a vertical channel.

[0089] In this embodiment, the top surface of the second doped region 60 and the bottom surface of the gate structure 40 are flush with each other, so that the conventional device channel can be converted into a vertical channel, thereby reducing the resistance of the JFET region and improving the electrical properties of the semiconductor device.

[0090] In some embodiments, please refer to Figure 1 , the first type is P-type and the second type is N-type; or the first type is N-type and the second type is P-type.

[0091] It should be noted that, in another embodiment, Figure 2 As shown in , the semiconductor device may further include an epitaxial layer 104, which is located on the top surface of the heavily doped epitaxial layer 101. The epitaxial layer 104 may include a layer of ions of the same conductivity type as the heavily doped epitaxial layer 101 injected into the top surface of the heavily doped epitaxial layer 101 to reduce the extraction speed of minority carriers and improve the recovery capability of the device, wherein the doping concentration of the epitaxial layer 104 is less than the doping concentration of the heavily doped epitaxial layer 101, and greater than the doping concentration of the second-type stepped semiconductor column 202.

[0092] It should be noted that, in another embodiment, Figure 3 As shown in the figure, the semiconductor device can also set the first step semiconductor layer to a low-concentration first step semiconductor layer 20A and a high-concentration first step semiconductor layer 20B. The low-concentration first step semiconductor layer 20A and the high-concentration first step semiconductor layer 20B can improve the unclamped inductive load switching process (Unclamped Inductive Switching, UIS) characteristics. By setting the low-concentration first step semiconductor layer 20A and the high-concentration first step semiconductor layer 20B in the second direction to form a concentration gradient, the triggering of the parasitic bipolar transistor effect is delayed.

[0093] It should be noted that, in another embodiment, the semiconductor device may further include: Figure 4 The structure shown in the figure includes an epitaxial layer 104, and the first stepped semiconductor layer 20 is set to a first-type semiconductor column 201A and a second-type semiconductor column 202A, and the exposed top surface of the second-type semiconductor column 202A is set to a second-type Schottky contact, and the exposed surface of the first-type doped region 501 is set to a first-type Schottky contact. This structure can greatly reduce the hole injection in the reverse conduction process, thereby improving the reverse recovery capability of the device.

[0094] An embodiment of the present application provides an electronic device, comprising the semiconductor device in any one of the above embodiments.

[0095] The electronic device of the present application includes the semiconductor device in any of the above embodiments. When the device is turned off, the first-type high semiconductor column 201 and the second-type stepped semiconductor column 202, as well as the second-type stepped semiconductor column 202 and the first-type low semiconductor column 203 can form two reverse-biased PN junctions to increase the width of the depletion layer, thereby enhancing the breakdown voltage of the semiconductor device. At the same time, the first-step semiconductor layer 20 and the second-step semiconductor layer 30 are arranged into a stepped structure, and the gate structure is arranged on a partial top surface of the first step 2021 and a top surface of the third step 3021. The planar channel in the traditional device can be converted into a vertical channel, thereby reducing the resistance of the JFET region, increasing the electrical properties of the semiconductor device, and reducing the size of the gate structure 40, thereby improving the space utilization of the semiconductor device.

[0096] The present invention provides a method for preparing a semiconductor device. Figure 5 , the method for preparing the semiconductor device may include:

[0097] S11: providing a substrate.

[0098] As an example, see Figure 6 The substrate 10 may include but is not limited to at least one of a silicon substrate, a gallium nitride (GaN) substrate, and a silicon carbide (SiC) substrate, and the substrate 10 includes a heavily doped epitaxial layer 101 of a second conductivity type located on the substrate 10. Specifically, in this embodiment, the substrate 10 is a silicon substrate, and the heavily doped epitaxial layer 101 of the second conductivity type is an N-type heavily doped epitaxial layer.

[0099] S12: A first stepped semiconductor layer is formed on the substrate, wherein the first stepped semiconductor layer includes a first-type high semiconductor column, a second-type stepped semiconductor column and a first-type low semiconductor column distributed along a first direction parallel to the substrate, wherein a top surface of the first-type high semiconductor column is higher than a top surface of the first-type low semiconductor column, and the second-type stepped semiconductor column includes two groups of first steps and second steps consisting of interconnected horizontal planes and vertical planes.

[0100] As an example, see Figure 7 , the first direction is defined as the direction of the x-axis. The first-type high semiconductor pillar 201 is a P-type semiconductor pillar, the second-type step semiconductor pillar 202 is an N-type semiconductor pillar, and the first-type low semiconductor pillar 203 is a P-type semiconductor pillar.

[0101] S13: forming a second stepped semiconductor layer and a gate structure, the second stepped semiconductor layer comprising a first-type semiconductor layer and a first-type stepped semiconductor layer, the first-type semiconductor layer covering the top surface of the first-type high semiconductor column and part of the top surface of the second-type stepped semiconductor column, the first-type stepped semiconductor layer covering the horizontal plane of the second step and the top surface of the first-type low semiconductor column, and the first-type stepped semiconductor layer comprising a third step and a fourth step consisting of interconnected horizontal planes and vertical planes, the gate structure being located on part of the top surface of the first step and the top surface of the third step, the gate structure comprising a gate dielectric layer and a gate conductive layer covered by the gate dielectric layer.

[0102] As an example, see Figure 1 , the first-type semiconductor layer 301 and the first-type stepped semiconductor layer 302 are both P-type semiconductor layers. Specifically, in this embodiment, the doping concentration of the second stepped semiconductor layer 30 is greater than the doping concentration of the first-type high semiconductor pillar 201. The gate dielectric layer 401 may include but is not limited to an oxide layer, and the gate conductive layer 402 may include but is not limited to a polysilicon layer.

[0103] The preparation method of the semiconductor device of the present application first provides a substrate, and then forms a first stepped semiconductor layer on the substrate, wherein the first stepped semiconductor layer includes a first-type high semiconductor column, a second-type stepped semiconductor column and a first-type low semiconductor column distributed along a first direction parallel to the substrate, wherein the top surface of the first-type high semiconductor column is higher than the top surface of the first-type low semiconductor column, and the second-type stepped semiconductor column includes two groups of first steps and second steps composed of interconnected horizontal planes and vertical planes, and finally forms a second stepped semiconductor layer and a gate structure, wherein the second stepped semiconductor layer includes a first-type semiconductor layer and a first-type stepped semiconductor layer, the first-type semiconductor layer covers the top surface of the first-type high semiconductor column and part of the top surface of the second-type stepped semiconductor column, the first-type stepped semiconductor layer covers the horizontal plane of the second step and the top surface of the first-type low semiconductor column, and the first-type stepped semiconductor layer includes a third step and a fourth step composed of interconnected horizontal planes and vertical planes, the gate structure is located on part of the top surface of the first step and the top surface of the third step, and the gate structure includes a gate dielectric layer and a gate conductive layer covered by the gate dielectric layer. When the device is turned off, the first-type high semiconductor column 201 and the second-type stepped semiconductor column 202, as well as the second-type stepped semiconductor column 202 and the first-type low semiconductor column 203 can form two reverse-biased PN junctions to increase the width of the depletion layer, thereby enhancing the breakdown voltage of the semiconductor device. At the same time, the first-step semiconductor layer 20 and the second-step semiconductor layer 30 are arranged into a stepped structure, and the gate structure is arranged on a partial top surface of the first step 2021 and a top surface of the third step 3021. The planar channel in the traditional device can be converted into a vertical channel, thereby reducing the resistance of the JFET region, increasing the electrical properties of the semiconductor device, and reducing the size of the gate structure 40, thereby improving the space utilization of the semiconductor device.

[0104] In some embodiments, see Figure 8 , forming a first stepped semiconductor layer on a substrate may include the following steps: step S121 to step S125.

[0105] S121: forming a lightly doped epitaxial layer on a substrate.

[0106] As an example, see Fig. 9 , a lightly doped epitaxial layer 102 may be formed on the heavily doped epitaxial layer 101 in the substrate 10 by using but not limited to an epitaxial process.

[0107] S122: forming a first-type high semiconductor column and an initial first-type low semiconductor column in the lightly doped epitaxial layer, wherein the first-type high semiconductor column and the initial first-type low semiconductor column circumferentially surround the lightly doped epitaxial layer.

[0108] As an example, see Figures 10 to 12, the first type high semiconductor column 201 and the initial first type low semiconductor column 2031 can be formed in the lightly doped epitaxial layer 102 by using, but not limited to, an ion implantation process, wherein the first type high semiconductor column 201 and the initial first type low semiconductor column 2031 circumferentially surround the lightly doped epitaxial layer 102. It should be noted that the formation of the first type high semiconductor column and the initial first type low semiconductor column in the lightly doped epitaxial layer may include the following steps:

[0109] S1221: forming an initial first-type semiconductor column in the lightly doped epitaxial layer, wherein the initial first-type semiconductor column circumferentially surrounds the lightly doped epitaxial layer.

[0110] For example, see Fig.10 The initial first-type semiconductor pillar 2011 may be formed in the lightly doped epitaxial layer by, but is not limited to, ion implantation.

[0111] S1222: forming an initial covering lightly doped epitaxial layer on the top surfaces of the initial first-type semiconductor pillar and the lightly doped epitaxial layer.

[0112] For example, see Fig.11 The initial covering lightly doped epitaxial layer 1031 may be formed on the top surface of the initial first-type semiconductor pillar and the lightly doped epitaxial layer by using, but not limited to, an epitaxial process.

[0113] S1223: forming a first-type high semiconductor column and an initial first-type low semiconductor column in the initial covering lightly doped epitaxial layer, wherein the first-type high semiconductor column and the initial first-type low semiconductor column cover the initial first-type semiconductor column and are respectively located on two opposite sides of the initial covering lightly doped epitaxial layer.

[0114] For example, see Fig.12 , the first-type high semiconductor pillar 201 and the initial first-type low semiconductor pillar 2031 may be formed in the initial covering lightly doped epitaxial layer 1031 by, but not limited to, ion implantation.

[0115] S123: forming a covering lightly doped epitaxial layer on top surfaces of the lightly doped epitaxial layer, the first-type high semiconductor pillars and the initial first-type low semiconductor pillars.

[0116] As an example, see Fig.13 The covering lightly doped epitaxial layer 103 may be formed on the top surfaces of the lightly doped epitaxial layer 102 , the first type high semiconductor pillars 201 and the initial first type low semiconductor pillars 2031 by using but not limited to an epitaxial process.

[0117] S124: Etching the lightly doped epitaxial layer to form a groove, wherein the bottom surface of the groove is flush with the top surface of the initial first-type low semiconductor column.

[0118] As an example, see Fig.14The covering lightly doped epitaxial layer 103 may be etched by, but not limited to, a wet etching process or a dry etching process to form a groove 70 , the bottom surface of the groove 70 being flush with the top surface of the initial first-type low semiconductor pillar 2031 .

[0119] Step 125 : forming a second-type stepped semiconductor column having a first step and a second step in the lightly doped epitaxial layer, and forming a first-type lower semiconductor column in the initial first-type lower semiconductor column to form a first stepped semiconductor layer.

[0120] As an example, see Fig.15 , an ion implantation process may be used but is not limited to form a second-type stepped semiconductor column 202 having a first step 2021 and a second step 2022 in the lightly doped epitaxial layer 102 , and a first-type lower semiconductor column 203 is formed in an initial first-type lower semiconductor column 2031 to form a first stepped semiconductor layer 20 .

[0121] In the embodiment of the present application, by forming a first-type high semiconductor column 201, a second-type stepped semiconductor column 202 and a first-type low semiconductor column 203, the first-type high semiconductor column 201 and the second-type stepped semiconductor column 202, as well as the second-type stepped semiconductor column 202 and the first-type low semiconductor column 203 can form two reverse-biased PN junctions to increase the width of the depletion layer, thereby enhancing the breakdown voltage of the semiconductor device.

[0122] In some embodiments, see Fig.16 , forming the second stepped semiconductor layer may include the following steps: S131~S132.

[0123] S131: forming a first-type semiconductor layer and an initial first-type stepped semiconductor layer in the covering lightly doped epitaxial layer having the groove.

[0124] As an example, see Fig.17 The first-type semiconductor layer 301 and the initial first-type stepped semiconductor layer 3023 may be formed in the covering lightly doped epitaxial layer 103 having the groove 70 by, but not limited to, ion implantation.

[0125] S132: forming a first-type stepped semiconductor layer having a third step and a fourth step in the initial first-type stepped semiconductor layer to form a second stepped semiconductor layer, wherein a top surface of the third step is flush with a top surface of the first step.

[0126] As an example, see Figure 1, an ion implantation process can be used but is not limited to form a first type stepped semiconductor layer 302 having a third step 3021 and a fourth step 3022 in the initial first type stepped semiconductor layer 3023 to form a second stepped semiconductor layer 30. It should be noted that the initial first type stepped semiconductor layer 3023 removes the ion portion implanted by the ion implantation process to form the first type stepped semiconductor layer 302.

[0127] In the embodiment of the present application, by setting the top surface of the first-type semiconductor layer 301 and the top surface of the first-type stepped semiconductor layer 302 to be uneven, space can be provided for the gate structure, so that the gate structure can be set on a partial top surface of the first step 2021 and the top surface of the third step 3021, and the planar channel in the traditional device can be converted into a vertical channel, thereby reducing the resistance of the JFET region.

[0128] It should be noted that after forming a first-type semiconductor layer and an initial first-type stepped semiconductor layer in the covering lightly doped epitaxial layer with a groove, the method for preparing the semiconductor device also includes forming a gate structure on a portion of the top surface of the first step and the top surface of the third step, which may include the following steps: S133~S136.

[0129] S133: forming a first gate dielectric layer on the sidewall and top surface of the groove.

[0130] As an example, see Fig.18 The first gate dielectric layer 4011 may be formed on the sidewall and top surface of the groove 70 by, but is not limited to, physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD) or thermal oxidation process.

[0131] S134: filling the groove with an initial gate dielectric layer, wherein the top surface of the initial gate dielectric layer is flush with the top surface of the first-type semiconductor layer.

[0132] As an example, see Fig.19 The initial gate conductive layer 4021 may be filled in the groove 70 by, but is not limited to, a physical vapor deposition process (PVD), a chemical vapor deposition process (CVD), or an atomic layer deposition process (ALD). The top surface of the initial gate conductive layer 4021 is flush with the top surface of the first semiconductor layer 301.

[0133] S135: etching the initial gate conductive layer and the first gate dielectric layer to form a gate conductive layer, wherein the bottom surface of the first gate dielectric layer covers a portion of the top surface of the second-type stepped semiconductor column and a portion of the top surface of the initial first-type stepped semiconductor layer.

[0134] As an example, see Fig. 20 The initial gate conductive layer 4021 and the first gate dielectric layer 4011 may be etched by, but not limited to, a wet etching process or a dry etching process to form a gate conductive layer 402, wherein the bottom surface of the first gate dielectric layer 4011 covers a portion of the top surface of the second-type stepped semiconductor column 202 and a portion of the top surface of the initial first-type stepped semiconductor layer 3023.

[0135] S136: forming a second gate dielectric layer on the exposed surface of the initial gate conductive layer to form a gate structure, wherein the first gate dielectric layer and the second gate dielectric layer together constitute a gate dielectric layer.

[0136] As an example, see Fig.21 A second gate dielectric layer (not shown) may be formed on the exposed surface of the initial gate conductive layer 4021 by, but not limited to, physical vapor deposition, chemical vapor deposition, atomic layer deposition or thermal oxidation.

[0137] In some embodiments, see Fig. 22 After forming the second stepped semiconductor layer and the gate structure, the following steps may also be included: S141~S142.

[0138] S141: forming a first doped region on a top surface of the second stepped semiconductor layer, wherein the top surface of the first doped region is flush with a top surface of the gate structure, and the first doped region includes a first type doped region and a second type doped region distributed along a first direction.

[0139] As an example, see Figure 1 The first doping region 50 may be formed on the top surface of the second stepped semiconductor layer 30 by, but not limited to, an ion implantation process. The first doping region 50 includes a first-type doping region 501 and a second-type doping region 502 distributed along a first direction ox.

[0140] S142: forming a second doped region on the top surface of the horizontal plane of the fourth step, wherein the top surface of the second doped region is flush with the top surface of the third step and the bottom surface of the gate structure, and the second doped region includes a second type injection region and a first type injection region distributed along the first direction.

[0141] As an example, see Figure 1The second doped region 60 can be formed on the top surface of the horizontal plane of the fourth step 3022 by, but not limited to, an ion implantation process. The top surface of the second doped region 60 is flush with the top surface of the third step 3021 and the bottom surface of the gate structure 40. The second doped region 60 includes a second type implantation region 601 and a first type implantation region 602 distributed along the first direction ox.

[0142] In the embodiment of the present application, the first doping region 50 and the second doping region 60 are formed so that when the device is in the on state, carriers flow between the second type doping region 502 in the first doping region 50 and the second type injection region in the second doping region 60, thereby forming an on-current.

[0143] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features of the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0144] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be construed as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent application shall be subject to the attached claims.

Claims

1. A semiconductor device, characterized in that: include: substrate; A first stepped semiconductor layer, located on the substrate, comprises a first-type high semiconductor column, a second-type stepped semiconductor column and a first-type low semiconductor column distributed along a first direction parallel to the substrate, wherein the top surface of the first-type high semiconductor column is higher than the top surface of the first-type low semiconductor column, and the second-type stepped semiconductor column comprises two groups of first steps and second steps consisting of interconnected horizontal planes and vertical planes; The second stepped semiconductor layer includes a first-type semiconductor layer and a first-type stepped semiconductor layer, wherein the first-type semiconductor layer covers the top surface of the first-type high semiconductor column and part of the top surface of the second-type stepped semiconductor column, the first-type stepped semiconductor layer covers the horizontal plane of the second step and the top surface of the first-type low semiconductor column, and the first-type stepped semiconductor layer includes a third step and a fourth step formed by interconnected horizontal planes and vertical planes; The gate structure is located on a portion of the top surface of the first step and the top surface of the third step, and includes a gate dielectric layer and a gate conductive layer covered by the gate dielectric layer.

2. The semiconductor device according to claim 1, wherein: The top surface of the third step is flush with the top surface of the first step.

3. The semiconductor device according to claim 1, wherein: Also includes: A first doping region, located on a top surface of the second stepped semiconductor layer, wherein a top surface of the first doping region is flush with a top surface of the gate structure, and comprises a first type doping region and a second type doping region distributed along a first direction; The second doping region is located on the top surface of the fourth step, and the top surface of the second doping region is flush with the top surface of the third step, and includes a second type injection region and a first type injection region distributed along the first direction.

4. The semiconductor device according to claim 3, characterized in that A top surface of the second doping region is flush with a bottom surface of the gate structure.

5. The semiconductor device according to any one of claims 1 to 4, characterized in that: The first type is P type, and the second type is N type; or The first type is N type, and the second type is P type.

6. An electronic device, characterized in that: include: A semiconductor device as claimed in any one of claims 1 to 5.

7. A method for preparing a semiconductor device, characterized in that: include: providing a substrate; A first stepped semiconductor layer is formed on the substrate, wherein the first stepped semiconductor layer includes first-type high semiconductor pillars, second-type stepped semiconductor pillars and first-type low semiconductor pillars distributed along a first direction parallel to the substrate, wherein the top surface of the first-type high semiconductor pillar is higher than the top surface of the first-type low semiconductor pillar, and the second-type stepped semiconductor pillar includes two groups of first steps and second steps consisting of interconnected horizontal planes and vertical planes; A second stepped semiconductor layer and a gate structure are formed, wherein the second stepped semiconductor layer includes a first-type semiconductor layer and a first-type stepped semiconductor layer, wherein the first-type semiconductor layer covers the top surface of the first-type high semiconductor column and part of the top surface of the second-type stepped semiconductor column, wherein the first-type stepped semiconductor layer covers the horizontal plane of the second step and the top surface of the first-type low semiconductor column, and the first-type stepped semiconductor layer includes a third step and a fourth step formed by interconnected horizontal planes and vertical planes, wherein the gate structure is located on part of the top surface of the first step and the top surface of the third step, and wherein the gate structure includes a gate dielectric layer and a gate conductive layer covered by the gate dielectric layer.

8. The method for preparing a semiconductor device according to claim 7, characterized in that: The step of forming a first stepped semiconductor layer on the substrate comprises: forming a lightly doped epitaxial layer on the substrate; Forming the first-type high semiconductor pillars and initial first-type low semiconductor pillars in the lightly doped epitaxial layer, wherein the first-type high semiconductor pillars and initial first-type low semiconductor pillars circumferentially surround the lightly doped epitaxial layer; forming a covering lightly doped epitaxial layer on top surfaces of the lightly doped epitaxial layer, the first-type tall semiconductor pillars and the initial first-type low semiconductor pillars; Etching the covering lightly doped epitaxial layer to form a groove, wherein the bottom surface of the groove is flush with the top surface of the initial first-type low semiconductor column; A second-type stepped semiconductor column having the first step and the second step is formed in the lightly doped epitaxial layer, and a first-type lower semiconductor column is formed in the initial first-type lower semiconductor column to form the first stepped semiconductor layer.

9. The method for preparing a semiconductor device according to claim 8, characterized in that: The forming of the second stepped semiconductor layer comprises: forming a first-type semiconductor layer and an initial first-type stepped semiconductor layer in the covering lightly doped epitaxial layer having the groove; A first-type stepped semiconductor layer having the third step and the fourth step is formed in the initial first-type stepped semiconductor layer to form the second stepped semiconductor layer, wherein a top surface of the third step is flush with a top surface of the first step.

10. The method for preparing a semiconductor device according to claim 7, characterized in that: After forming the second stepped semiconductor layer and the gate structure, the method further includes: forming a first doping region on the top surface of the second stepped semiconductor layer, wherein the top surface of the first doping region is flush with the top surface of the gate structure, and the first doping region includes a first-type doping region and a second-type doping region distributed along a first direction; A second doped region is formed on the top surface of the horizontal plane of the fourth step, the top surface of the second doped region is flush with the top surface of the third step and the bottom surface of the gate structure, and the second doped region includes a second type injection region and a first type injection region distributed along the first direction.

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