Nanowire integrated device, preparation method and application

Abstract

The invention relates to a highly integrated transistor which comprises a columnar trunk structure located on a substrate and one or more branch structures epitaxially growing on the columnar trunk structure. The columnar trunk and the branch structures form a tree-shaped structure; and a transistor is formed by a single branch structure or a plurality of branch structures. The substrate area occupied by an existing common transistor is 2.8 mu m < 2 > (the width is 1.14 mu m and the length is 2.44 mu m), and based on the transistor, under the same area, the integration level can be improved to 144 at least (four tree structures and 36 branches of each tree structure), and the integration level is continuously improved by changing the distance and the number of branch layers of the tree structures. Based on the integration level and device arrangement optimization, additional wiring is not needed, and the spatial layout of connection of different devices in the 3D space can be realized. The ring gate field effect transistor is manufactured through the branch structure, the manufacturing steps and difficulties of the ring gate field effect transistor are reduced, and the phenomenon that the transistor manufactured by a single III-V group material is too obvious in advantages and disadvantages and poor in comprehensive performance is solved.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor devices, and in particular relates to a nanowire integrated device, a preparation method and an application thereof. Background Art

[0002] Integrated circuits have evolved from integrating dozens of devices on a single chip to integrating millions of devices. The performance and complexity of traditional integrated circuits have far exceeded initial imagination. In order to achieve the increase in complexity and circuit density (the number of devices that can be accommodated on a certain chip area), the feature size of the device, also known as the "geometry size", has become smaller and smaller with each generation of integrated circuits.

[0003] Increasing the density of integrated circuits can improve the complexity and performance of integrated circuits. Based on the demand for high density, high speed and low power consumption of integrated circuit chips, integrated circuits are increasingly developing in the direction of high density, high speed and low power consumption.

[0004] The integration on the chip is mainly 2D. All chips and passive devices are installed on the substrate plane. The chips and passive devices are in direct contact with the XY plane. The wiring and vias on the substrate are all located below the XY plane. Electrical connections: All need to pass through the substrate (except for a very small number of bonding points directly connected by bonding wires). 3D integration currently refers to integration through 3DTSV to a large extent. Although the physical structure is 3D, the metal needs to pass through multiple chips. This is the same as 2D integration. The improvement over 2D integration is the structural stacking, which can save packaging space, so it is called 2D. + Integration. It is impossible to achieve true 3D integration. The present invention overcomes the technical prejudice that 3D space transistor architecture cannot be self-assembled, and proposes a technical structure for realizing independent control of different component 3D space transistors on different substrates, thereby overcoming the technical bottleneck of accelerated computing units with higher computing power density / greater computing power per unit area of ​​the chip and increasing the storage capacity per unit area of ​​the chip, thereby simplifying the complexity of the interconnection between the storage unit and the computing unit, and ultimately improving the write and read speed and computing speed, and realizing a chip with a new architecture. Summary of the invention

[0005] In order to solve the problem of low integration of existing solutions, the present invention provides a highly integrated transistor and a preparation process thereof.

[0006] The highly integrated transistor described in the present invention comprises a columnar trunk structure located on a substrate, and one or more branch structures epitaxially grown from the columnar trunk structure; the columnar trunk structure and the branch structures form a tree structure.

[0007] In some embodiments of the present invention, the columnar backbone structure is a nanowire, which can be obtained by epitaxial growth from a substrate.

[0008] In some embodiments of the present invention, the columnar trunk structure may be made of insulating dielectric material, conductive material, highly doped semiconductor material, or low doped semiconductor material.

[0009] In some embodiments of the present invention, a single branch structure constitutes a transistor, and the branch structure has a source region and a drain region with high concentration doping, and a channel region with low concentration doping. In this case, the columnar trunk structure can be an insulating dielectric material or a semiconductor material with high concentration doping or a semiconductor material with low concentration doping.

[0010] In some embodiments of the present invention, the source region, the channel region, and the drain region are arranged in sequence to form a main body.

[0011] In certain embodiments of the present invention, a racetrack-type channel is configured, specifically, a partition region is provided between the source region and the drain region, and the source region, the partition region, and the drain region form the main body of the branch structure; the channel region is located at the periphery of the main body, and preferably, the channel region surrounds the main body.

[0012] In some embodiments of the present invention, two branch structures form a transistor. In this case, the transistor may rely on the columnar trunk structure, or in other words, the columnar trunk structure will become a component of the transistor device.

[0013] In certain embodiments of the present invention, the branch structure has a low-concentration doping region located at the inner end and a high-concentration doping region located at the outer end; one high-concentration doping region constitutes a source region, and the other high-concentration doping region constitutes a drain region; at this time, the columnar trunk structure should be a low-concentration doped semiconductor medium; it communicates with the two proximal low-concentration doping regions to form a channel region.

[0014] In some embodiments of the present invention, the branch structure has a partition region located at the inner end and a high-concentration doped region located at the outer end; the partition region at the inner end and the high-concentration doped region at the outer end constitute the main part of the branch structure; the periphery of the main part of the branch structure is surrounded by a layer of semiconductor medium with low concentration doping; the low-concentration doped semiconductor mediums on the two branch structures are connected; thus, one high-concentration doped region constitutes a source region, and the other high-concentration doped region constitutes a drain region; the connected low-concentration doped semiconductor medium constitutes a channel region. Preferably, the channel region surrounds the main part.

[0015] In certain embodiments of the present invention, when the low-concentration doped semiconductor media on two branch structures are connected through a columnar trunk structure, the columnar trunk structure must be a low-concentration doped semiconductor medium; when the two branch structures are connected through another low-concentration doped semiconductor medium, the columnar trunk structure is not part of the transistor and can be any medium.

[0016] As a preferred solution, the low-concentration-doped semiconductor media on the two branch structures are connected through another low-concentration-doped semiconductor medium, and the low-concentration-doped semiconductor medium forms an annular medium surrounding the main parts of the two branch structures.

[0017] In addition, when the columnar trunk structure is a semiconductor medium doped with a high concentration or a conductor, the columnar trunk structure can be used as a part of a transistor to realize a common source or a common drain of multiple branches thereon.

[0018] In some embodiments of the present invention, the branch structure has a low-concentration doping region at the inner end and a high-concentration doping region at the outer end; the columnar trunk structure and the high-concentration doping region at the outer end of the branch structure constitute the drain region / source region.

[0019] In some embodiments of the present invention, the branch structure has a partition region at the inner end and a high-concentration doped region at the outer end; the partition region at the inner end and the high-concentration doped region at the outer end constitute the main part of the branch structure; the periphery of the main part of the branch structure also has a low-concentration doped semiconductor medium; thus, the columnar trunk structure and the high-concentration doped region at the outer end of the branch structure constitute the drain region / source region, and the low-concentration doped semiconductor medium constitutes the channel region. Preferably, the channel region surrounds the main part.

[0020] In addition, when the columnar trunk structure is an insulating medium, a transistor can be further formed through two branch structures; one branch structure has a high-concentration doped region as a source region, and the other branch structure has a high-concentration doped region as a drain region; the columnar trunk structure surrounds a low-concentration doped semiconductor medium and forms a channel region between the source and the drain.

[0021] The present invention also provides a method for preparing the above transistor, which at least comprises: (1) growing nanowires on a substrate to form a columnar trunk structure; (2) growing branch nanowires on the columnar trunk structure; and changing the growth conditions during the growth process to adjust the element composition during the growth. The electrode structure thereon can be constructed by deposition.

[0022] The beneficial effects of the present invention are:

[0023] (1) The existing common transistor (channel width 2um, length 0.18um) occupies a substrate area of ​​2.8um 2 (width 1.14um length 2.44um), based on the present invention, under the same area, the integration can be increased to at least 144 (4 tree-like nanowires, each tree-like nanowire has 6 directions and 6 layers of branches), and the tree-like nanowires can continuously improve the integration by shortening the distance between nanowires and the number of branch layers.

[0024] (2) Based on the improvement of integration and the optimization of device structure layout, the present invention can realize the spatial layout of different device connections in 3D space during the branch growth stage without the need for wiring and via leads on additional substrates, without the need to construct device layers, isolation layers, and connection layers in multiple steps.

[0025] (3) The present invention performs the manufacturing steps of the ring-gate field effect transistor based on the growing branch nanowires, utilizes the characteristics of the synchronous growth of the branch nanowires, and simplifies the doping process flow and manufacturing steps of the ring-gate field effect transistor, thereby solving the problem that the advantages and disadvantages of transistors made of a single III-V material are too obvious and the overall performance is poor. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 Schematic diagram of the structures of various transistors in the embodiments of the present invention;

[0027] Figure 2 A schematic diagram of the structure of a substrate "mask layer-heavily doped substrate" in an embodiment of the present invention;

[0028] Figure 3 Schematic diagram of the self-assembly of a single columnar trunk structure in an embodiment of the present invention;

[0029] Figure 4 Schematic diagram of a single branch structure self-assembly in an embodiment of the present invention; (a) is a 3D schematic diagram of a single tree-like nanowire as a whole; (b) is a top view of a single tree-like nanowire as a whole;

[0030] Figure 5 The proportion of the branch structure installed independently in the embodiment of the present invention;

[0031] Figure 6 Schematic diagram of the gate region of a single branch structure field effect transistor in an embodiment of the present invention; (a) is a partial common gate control and independent gate control structure; (b) is a fully independent gate control structure; (c) describes the channel: one is to form an inversion layer inside the branch nanowire, and the other is to prepare an external channel layer; (d) is the gate region of a horizontal wrap-around gate transistor; (e) is the gate region of a flat wrap-around floating gate transistor;

[0032] Figure 7 Schematic diagram of isolation between single branch structure field effect transistors in an embodiment of the present invention; (a) is a partial isolation structure; (b) is a full isolation structure; (c) is an illustration of the gate region and the isolation region of a horizontal wrap-around gate transistor; (d) is an illustration of the gate region and the isolation region of a flat wrap-around floating gate transistor;

[0033] Figure 8Schematic diagram of electrodes for constructing an xy spatial channel region around the space where a branch nanowire is located in a single branch structure field effect transistor in an embodiment of the present invention; wherein (a) is a schematic diagram of the source and drain electrodes not being on the branch nanowires at the same time, the entire tree-like structure sharing the source / drain, and independent gate control; (b) is a schematic diagram of the source and drain electrodes not being on the branch nanowires at the same time, the entire tree-like structure sharing the source / drain, and selective sidewall common gate control; (c) is a schematic diagram of the source and drain electrodes being on the branch nanowires at the same time, and the source / drain can be selected to be shared or the source / drain can be independently controlled, and selective sidewall common gate control;

[0034] Fig. 9 Schematic diagram of electrodes for constructing an xyz spatial channel region around the space where the branch nanowire is located in a single branch structure field effect transistor in an embodiment of the present invention; wherein (a) is a schematic diagram of the same xy, the source and drain electrodes of the channel direction change z are both on the branch nanowire, and the gate is independently controlled; (b) is a schematic diagram of the same z, the source and drain electrodes of the channel direction change xy are both on the branch nanowire, and the gate is independently controlled;

[0035] Fig.10 Schematic diagrams of top views of novel electrode designs according to embodiments of the present invention; wherein (a) a top view of electrode design-1; (b) a top view of electrode design-2; (c) a top view of electrode design-3; and (d) a top view of electrode design-4. DETAILED DESCRIPTION

[0036] The transistor described in the present invention mainly refers to a field effect transistor (FET, such as MOSFET). Field effect transistors use electric fields to control current, and the most common type is the metal-oxide-semiconductor field effect transistor (MOSFET). Its basic structure includes three key regions: a source region (Source), a drain region (Drain), and a channel region (Channel) located between the two. The source region is the source of electrons or holes. In an n-type MOSFET, the source region is a high-concentration n-type doped region; in a p-type MOSFET, the source region is a high-concentration p-type doped region. The drain region is the end point of electrons or holes, and its function is similar to that of the source region, but it is usually symmetrical with the source region. In an n-type MOSFET, the drain region is also a high-concentration n-type doped region; in a p-type MOSFET, it is a high-concentration p-type doped region. The channel region is generally located between the source region and the drain region, and is the path for the flow of electrons or holes. For an n-type MOSFET, when the gate voltage is high enough, an n-type conductive channel is formed under the insulating layer; for a p-type MOSFET, a p-type conductive channel is formed. By adjusting the gate voltage, the width and resistance of the channel can be controlled, thereby controlling the current flowing through the transistor.

[0037] In conventional FET designs, the source and drain semiconductors are N-type highly doped or P-type highly doped Si, Ge or III-V semiconductors (GaAs, GaN, InAs, InN, InP, etc.). N-type doping refers to doping by adding pentavalent elements (with five valence electrons) to semiconductor materials. These elements have one more valence electron than the semiconductor matrix, and this extra electron can easily become a free electron, thereby increasing the electron concentration in the semiconductor. Common N-type dopants include: phosphorus (P) for doping silicon (Si) and germanium (Ge); arsenic (As) for doping silicon (Si), germanium (Ge) and III-V compound semiconductors (such as GaAs, InP). P-type doping is doping by adding trivalent elements (with three valence electrons) to semiconductor materials. These elements have two fewer valence electrons than the semiconductor matrix, leaving a vacancy in the material, namely a hole, which can participate in the conduction process as a positive charge carrier. Common P-type dopants include: boron (B) is mainly used for doping silicon (Si) and germanium (Ge); aluminum (Al) can be used for III-V compound semiconductors, such as GaAs, InP, etc. The channel semiconductor is P-type low-concentration doped or N-type low-concentration doped Si, Ge or III-V semiconductor (InGaN, InGaAs, AlGaN, GaAsP, etc.); the doping type is the same as the source-drain doping mentioned above. However, it should be noted that for channel semiconductors, low-concentration doping can sometimes be replaced by Si, Ge or III-V intrinsic semiconductors. For example, in an enhanced MOSFET, when the gate voltage is high enough, a conductive channel can be formed on the surface of the intrinsic semiconductor. This is because the applied voltage attracts negatively charged electrons to gather on one side close to the insulating layer, thereby forming an n-type conductive channel in this area (for n-channel MOSFETs). For p-channel MOSFETs, the gate voltage attracts holes to form a p-type conductive channel. Although "low-concentration doped semiconductors" are used in the embodiments of the present invention, those skilled in the art should know that in some scenarios, they can also be intrinsic semiconductors.

[0038] In the present invention, high concentration doping for forming source / drain regions and low concentration doping for forming channel regions are common technical means in the art, and those skilled in the art can determine the doping concentrations described therein without any doubt. Therefore, high concentration doping and low concentration doping in the present invention are not limitations on doping concentrations. High concentration doping and low concentration doping are unambiguous technical terms in the art, and are generally referred to as N + , P + To represent N-type high concentration doping and P-type high concentration doping, N - , P -To represent N-type low-concentration doping and P-type low-concentration doping. As is common knowledge in the art, the dopant concentration of the low-concentration doping is generally 1×10 20 / cm 3 Up to 5×10 20 / cm 3 The high concentration doping layer has a dopant concentration of 5×10 20 / cm 3 Up to 1×10 21 / cm 3 .

[0039] The invention relates to a transistor device which realizes high integration based on a tree structure, and comprises a columnar trunk structure located on a substrate, and one or more branch structures epitaxially grown from the columnar trunk structure.

[0040] In some embodiments of the present invention, the columnar backbone structure is a nanowire, which can be obtained by epitaxial growth from a substrate. Figure 2 In the structure of the substrate, the substrate is a "mask layer-heavily doped substrate" structure, wherein the substrate is a heavily doped substrate [1], and the surface of the epitaxial substrate is covered with mask materials such as SiO2, SiN, TiO2, etc. by physical vapor deposition (PVD), chemical vapor deposition (CVD) or atomic layer deposition (ALD) methods to form a mask layer [2]. The N-type substrate is a Si substrate doped with pentavalent elements such as arsenic, phosphorus, and antimony, and the P-type substrate is a Si substrate doped with trivalent elements such as boron. The first layer of photoresist is deposited, and an opening pattern is formed by exposure through an electron beam writing device (EBL) and an ultraviolet lithography device. Subsequently, the mask layer is opened by etching technology to form patterned holes, and the holes expose the surface of the Si region. Figure 3 This is a schematic diagram of the self-assembly of a single tree-like nanowire trunk, using solution self-assembly, epitaxial growth (including MOCVD, LPCVD, MBE, etc.) and other growth techniques to self-assemble a columnar trunk structure at the patterned holes [3].

[0041] In some embodiments of the present invention, the columnar trunk structure [3] can be made of insulating dielectric material, conductive material, or highly doped semiconductor material or low-doped semiconductor material. Figure 1 After the growth of the columnar trunk structure [3] is completed, a catalyst is added to the growth atmosphere. The catalyst is attached to the side wall of the columnar trunk structure [3]. By adjusting the growth temperature and the source temperature of the growing heterostructure material, the atoms are controlled to nucleate below the catalyst (the side wall point of the trunk structure), and the growth of branch nanowires begins, thereby forming Figure 4 Construction of tree-like nanowire branches[4].

[0042] The existing ring-gate structure is usually formed by stacking and growing the channel material and other materials, and then etching to obtain a suspended channel, and then growing the dielectric material to obtain the ring-gate field effect transistor. For example, the nanosheet ring-gate field effect transistor is formed by stacking and growing Si and SiGe, and then removing SiGe by an isotropic etching method, so that a suspended channel is obtained, and then the high dielectric constant dielectric material is deposited to surround it, so that the ring-gate field effect transistor can be made. Moreover, the current channel, source, and drain doping is usually performed on the semiconductor material through the mask or the self-alignment effect of the gate, and then multiple ion implantation methods are used to achieve impurity doping of different concentrations and types. Among them, the ring-gate structure needs to go through multiple steps of growth and etching to form a suspended channel, which greatly increases the complexity of the process and the difficulty of manufacturing, and also increases the production cost of the product. In addition, as the performance requirements for devices become higher and higher, semiconductor devices made of traditional silicon materials will also become increasingly difficult to meet the requirements. In addition, the devices currently made using III-V group are usually manufactured using only one of the materials, such as InP, GaAs, etc. This means that although the resulting devices have the advantages of this material, they will also be plagued by its disadvantages, making it difficult to obtain devices with good overall performance.

[0043] The present invention utilizes the growth of branched nanowires to manufacture ring-gate field effect transistors, thereby simplifying the growth steps of traditional ring-gate field effect transistors. First, epitaxial technology is used on a substrate to grow vertical nanowires, and the height of the growth can be adjusted as needed. After the vertical growth is completed, the growth direction needs to be changed so that it continues to grow horizontally. In this process, the growth conditions can be changed during its growth, and the element composition during its growth can be adjusted, so that the doping steps of the channel, source and drain can be realized when the nanowire grows. For example, we simplify the nanowire into three sections: source, channel and drain, and these three sections grow in sequence. Then we can assume P-type elements when the source grows, and switch to N-type elements when it grows to the channel part, and switch back to P-type elements when it grows to the drain part, so that we can obtain a PNP transistor. Of course, the doping concentration can be adjusted by the element concentration during growth, which is also more conducive to achieving trapezoidal concentration doping. Similar to doping, when the characteristics of one III-V group material are more suitable for the source and drain part, and the characteristics of another material are more suitable for the channel part, we can directly grow the two materials in the appropriate position by adjusting the growth conditions, so that the performance of each material can be maximized. After the lateral nanowires are grown, it is necessary to manufacture the ring-gate field-effect transistor. Here we will only use the lateral nanowires.

[0044] When manufacturing the gate, first deposit a gate dielectric layer of high dielectric constant (High-K) material, then etch to remove the dielectric layer around the source and drain parts, leaving only the channel part, so that the dielectric material only surrounds the middle section of the nanowire to form a ring gate structure. Then deposit and etch the sidewalls to form the source and drain on both sides. Then deposit and cover the insulating layer, and finally etch the through holes and deposit the interconnects. In this way, a ring gate field effect transistor based on lateral nanowires is manufactured. There are no special requirements for the materials of the High-K dielectric layer, sidewalls, insulating layer, and interconnects, and they can be freely selected according to the needs of the device itself and the material performance characteristics.

[0045] Therefore, the present invention will manufacture ring-gate field effect transistors based on self-grown branched nanowires, reduce the manufacturing steps of ring-gate field effect transistors, and use nanowires to simplify the process flow of transistor doping at the same time, so as to solve the problem that the advantages and disadvantages of transistors made of single III-V group materials are too obvious and the overall performance is poor. Moreover, we can dope impurities at the same time when growing nanowires, which allows us to more accurately control the concentration and position of impurities and simplify subsequent doping steps. Since the surface of the nanowire can have atomic-level smoothness that cannot be achieved by traditional etching methods, this can greatly reduce carrier scattering caused by surface roughness. When made of III-V group materials, the carrier mobility of the nanowire is also greatly improved, which can be 4-60 times higher than Si. And because the nanowire components can be changed during growth, this allows us to have the advantages of different materials at the same time and obtain devices with better performance and stronger comprehensive capabilities.

[0046] Based on a columnar trunk structure, multiple transistors can be constructed to form a highly integrated device. The transistors can be storage transistors or computing transistors. The construction of transistors depends on the branch structure on the columnar trunk structure. Figures 4-5 As shown in the figure, after the trunk growth length reaches the design requirement, the branch nanowires are distributed in the overall tree-like nanowire structure, and the branch structure growth is started to form branch nanowires in six horizontal directions [4]. The nanostructure can be protected by in-situ passivation isolation technology or cavity sulfurization, ammoniation, and deposition of a protective layer.

[0047] The formation of multiple branch structures from a columnar main structure is a commonly used technical means for growing three-dimensional structures in the art. The branch structures on the columnar main structure can be homogeneous or heterogeneous. Both homogeneous and heterogeneous methods can change the material type through solution self-assembly and epitaxial growth (including MOCVD, MBE, etc.) methods to perform secondary or multiple growth on the original basis.

[0048] Figure 1In transistors ①, ②, and ③, a transistor is formed in a single branch structure, and the branch structure has a source region and a drain region with high concentration doping, and a channel region with low concentration doping. It is also a common method in this field to form different concentrations of doping on a single branch structure. Generally, different concentrations of doping can be achieved by turning on the doping source and controlling the temperature of the doping source when growing branch nanowires. At this time, the branch structure independently forms a transistor, and the columnar trunk structure can be an insulating dielectric material or a highly doped semiconductor dielectric material or a low-concentration doped semiconductor dielectric material. When the columnar trunk structure is a doped semiconductor material that can contact an electrode, it can be used as a common electrode for multiple transistors.

[0049] Figure 1 The transistor No. ① in the figure has a linear channel region, with a high-concentration doped semiconductor as the source region, a low-concentration doped semiconductor as the channel region, and a high-concentration doped semiconductor as the drain region arranged in sequence. The corresponding source, gate, and drain can be constructed on one side wall of the branch structure as shown in the figure, or the three electrodes can be formed into a sleeve structure and wrapped around the outside of the corresponding section, effectively enhancing electron transfer, enhancing the gate's ability to control the channel, and effectively enhancing I ON / I OFF .

[0050] Figure 1 In the transistor No. ②, a low-concentration doped semiconductor layer is set on one side of the branch structure to form a racetrack-type channel region. Specifically, a partition region is set between the high-concentration doped semiconductor as the source region and the high-concentration doped semiconductor as the drain region. The source region, the partition region, and the drain region form the main part of the branch structure; a layer of low-concentration doped semiconductor layer (low-concentration doped region) as the channel region is formed outside the main part. The partition region uses an insulating medium to block the direct migration of carriers between the source region and the drain region, making the outer racetrack-type channel the only migration path. In this structure, the length of the channel can almost match the branch structure itself, so that the channel length is almost unaffected by the length of the nanowire portion occupied by the source region and the drain region, and only depends on the overall length of the branch structure. In this way, the channel is cleverly "pulled out" to the outside, greatly extending the effective channel length. Compared with the existing nanowire GAAFET, under the same manufacturing process, the channel length of the field effect transistor (RPCFET, Ring-Pillar Channel FET) of this application can be significantly increased, thereby improving the driving current capability of the device. According to the existing nanowire GAAFET process, for example, a 3nm channel will show a short channel effect when the nanowire length is 5nm. However, through the present invention, the overall device size can be compressed to close to 3nm, effectively improving the device's miniaturization capability and almost doubling the number of transistors integrated per unit chip area.

[0051] In a more preferred embodiment, the low-concentration doped semiconductor layer is formed into a sleeve structure, such as Figure 1 As shown in transistor No. ③ in the middle, the communication area of ​​the sleeve structure wraps around the main part. Compared with the single-sided channel setting, it can have a more effective channel runway area, thereby greatly improving the density of mobile electrons and reducing the threshold voltage of the transistor.

[0052] Figure 1 Transistors ④, ⑤, and ⑥ in the figure all contain two branch structures (which are perpendicular to the columnar trunk structure and are located on the same side of the trunk structure).

[0053] In transistor No. ④, the branch structure has a low-concentration doped semiconductor (low-concentration doped region) at the inner end and a high-concentration doped semiconductor (high-concentration doped region) at the outer end; one high-concentration doped region constitutes the source region, and the other high-concentration doped region constitutes the drain region; in the first case, the columnar trunk structure should be a low-concentration doped semiconductor medium; it and the two proximal low-concentration doped regions together constitute the channel region, and it and the two low-concentration doped regions form a C-type channel region, which significantly extends the channel length. In the second case, an "external medium" is set between the two proximal low-concentration doped semiconductors. The external medium is a low-concentration doped semiconductor, which and the two low-concentration doped regions form a C-type channel region, which also significantly extends the channel length. In the third case, the two low-concentration doped regions grow in parallel, and the closer they are to the high-concentration region, the more separated they are, and the two low-concentration doped regions form a V-type channel region.

[0054] In transistor No. ⑤, the branch structure has a partition region located at the inner end and a high-concentration doped semiconductor (high-concentration doped region) located at the outer end; the partition region at the inner end and the high-concentration doped region at the outer end constitute the main part of the branch structure; the periphery of the main part of the branch structure also has a low-concentration doped semiconductor layer; the low-concentration doped semiconductor media on the two branch structures are connected; thus, one high-concentration doped region constitutes a source region, and the other high-concentration doped region constitutes a drain region; the connected low-concentration doped semiconductor medium constitutes a channel region. Preferably, the channel region surrounds the main part.

[0055] When the low-concentration doped semiconductor media on two branch structures are connected through a columnar trunk structure, the columnar trunk structure must be a low-concentration doped semiconductor medium; when the two branch structures are connected through another low-concentration doped semiconductor medium, the columnar trunk structure is not part of the transistor and can be any medium.

[0056] Transistor No. ⑥ is a preferred solution. The low-concentration doped semiconductor media on the above two branch structures are connected through another low-concentration doped semiconductor medium, and the low-concentration doped semiconductor medium forms a ring medium surrounding the main part of the two branch structures to form a surrounding channel area. When the surrounding channel area is formed as a whole, the carrier movement path is not limited and will be distributed in the overall surrounding area to form a variety of carrier movement flows.

[0057] In addition, when the columnar trunk structure is a semiconductor medium doped with a high concentration, the columnar trunk structure can be used as a part of a transistor to realize a common source or a common drain of multiple branches thereon.

[0058] Figure 1 Transistors ⑦, ⑧, and ⑨ in the figure all include a branch structure (perpendicular to the columnar trunk structure).

[0059] In transistor No. 7, the branch structure has a low-concentration doping region located at the inner end and a high-concentration doping region located at the outer end; the columnar trunk structure and the high-concentration doping region at the outer end of the branch structure constitute the drain region / source region.

[0060] In transistors No. ⑧ and No. ⑨, the branch structure has a partition area located at the inner end and a high-concentration doped area located at the outer end; the partition area at the inner end and the high-concentration doped area at the outer end constitute the main part of the branch structure; the periphery of the main part of the branch structure also has a low-concentration doped semiconductor medium, transistor No. ⑧ belongs to a half-enclosed, and transistor No. 9 belongs to a full-enclosed; thus, the columnar trunk structure and the high-concentration doped area at the outer end of the branch structure constitute the drain region / source region, and the low-concentration doped semiconductor medium constitutes the channel region.

[0061] Figure 1 The transistor No. ⑩ in the figure all includes two branch structures (which are perpendicular to the columnar trunk structure and located on different sides of the trunk structure).

[0062] In transistor No. ⑩, when the columnar trunk structure is an insulating medium, a transistor can be further formed through two branch structures; one branch structure has a high-concentration doped region as a source region, and the other branch structure has a high-concentration doped region as a drain region; the columnar trunk structure is surrounded by a layer of low-concentration doped semiconductor medium, and a channel region is formed between the source and the drain, so that carriers are transported on a plane perpendicular to the trunk structure, forming a three-dimensional transport track.

[0063] Based on the above transistor types ① to ⑩, the transistor can be defined as a storage unit device or a computing unit device during the design process to achieve direct connection between the storage unit and the computing unit; in the computing unit, the transistor design can be selected according to the required channel design or carrier transport path. The patent of this invention shows a single branch structure field effect transistor, which can be expanded into a tree-like nanowire array device.

[0064] Based on the transistor types ① to ⑩ above, Figure 6 to Figure 10 Some of the fabricated forms of the device are given.

[0065] Figure 6 The figure is a schematic diagram of the gate region of a single branch structure field effect transistor, where (a) is a partial common gate control and independent gate control structure; (b) is a fully independent gate control structure. The overall structure includes a heavily doped silicon substrate [1], a mask layer [2], a columnar trunk structure [3], a branch structure [4], and a gate region [5]. Figure 1 As described above, the branch structure [4] can adopt a linear channel region such as transistor ① or a racetrack channel region such as transistor ②, both of which include a channel region

[41] and an internal intrinsic region

[42] , such as Figure 6 (c).

[0066] Figure 6 (d) is a schematic diagram of the gate region of a horizontal surround gate transistor (computing unit device), in which a corresponding gate oxide layer

[51] , such as SiO2, Al2O3, HfO2, etc., is deposited outside the internal intrinsic region

[42] and the channel region

[41] by ALD. Figure 6 (e) is a schematic diagram of the gate region of a flat wrap-around floating gate transistor (c storage unit device), in which a tunneling layer

[52] , a floating gate layer

[53] , and a gate oxide layer

[51] are deposited outside the intrinsic region

[42] and the channel region

[41] by ALD. After the gate region material is deposited, a photoresist is filled, and an opening structure is formed by masking, exposure, and other photolithography processes, that is, the position of the gate region layer is protected. The gate region material at other irrelevant positions is removed by dry etching or wet etching processes, thereby forming an overall Figure 6 Schematic diagram of the structure.

[0067] Figure 7 The diagram is a schematic diagram of the isolation between the field effect transistors of a single tree-like nanowire branch; (a) is a partial isolation structure; (b) is a full isolation structure; (c) is a detailed description of the intrinsic region

[42] , channel region

[41] , gate oxide layer

[51] , isolation region

[11] , and gate metal layer

[12] inside the gate region [5] of the horizontal wrap-around gate oxide transistor (computing unit device); (d) is a detailed description of the intrinsic region

[42] , channel region

[41] , tunneling layer

[52] , floating gate layer

[53] , gate oxide layer

[51] , isolation region

[11] , and gate metal layer

[12] inside the gate region [5] of the flat wrap-around floating gate transistor (storage unit device). The isolation region

[11] is filled with photoresist after the gate region [5] is prepared, and an opening structure is formed through masking, exposure and other photolithography processes, that is, protecting the gate region position. The gap is filled with insulating material through magnetron sputtering, LPCVD, PECVD, ALD and other processes. Thus, Figure 7In the schematic diagrams (a) and (b), the gate region [5] can be selected to have multiple channels share a gate layer and the same gate material, or a single channel can be a gate layer, and the materials selected for each gate layer can be different. In field effect transistor applications, if a single horizontal branch nanowire or several horizontal branch nanowires are used as a horizontal wraparound field effect transistor to control the overall tree-like nanowire field effect transistor, different gate materials are selected to form multiple gate-controlled horizontal wraparound field effect transistor arrays, and because different materials lead to different gate capacity control, a multifunctional transistor array can be realized.

[0068] Figure 8 Schematic diagram of electrodes for constructing an xy spatial channel region around the space where the branch nanowires are located in a single branch structure field effect transistor in an embodiment of the present invention; wherein (a) is a schematic diagram of the case where the source and drain electrodes are not on the branch nanowires at the same time, the entire tree-like structure has a common source / drain, and the gate is independently controlled; (b) is a schematic diagram of the case where the source and drain electrodes are not on the branch nanowires at the same time, the entire tree-like structure has a common source / drain, and selective sidewall common gate control; (c) is a schematic diagram of the case where the source and drain electrodes are on the branch nanowires at the same time, and the common source / drain or independent source / drain control can be selected, and the sidewall common gate control is selective.

[0069] Fig. 9 Schematic diagram of electrodes of a single branch structure field effect transistor in an embodiment of the present invention constructing an xyz spatial channel region around the space where the branch nanowire is located; wherein (a) is the same as xy, the source and drain electrodes of the channel direction change z are both on the branch nanowire, and the gate is independently controlled; (b) is the same as z, the source and drain electrodes of the channel direction change xy are both on the branch nanowire, and the gate is independently controlled.

[0070] Figure 8-Figure 9 They all include a heavily doped silicon substrate [1], a mask layer [2], a tree-like nanowire trunk [3], a branch structure [4], a gate region [5], an isolation region

[11] , a gate metal

[12] , and a source / drain metal

[13]

[14] ; wherein the source electrode and the drain electrode structures can be interchanged. After forming the gate region [5] and the isolation region

[11] , photoresist is filled, and an electrode region opening structure is formed through masking, exposure and other photolithography processes, that is, the position

[12]

[13]

[14] is exposed. Through electrode preparation processes such as magnetron sputtering and thermal evaporation, gate metal

[12] and source / drain metal

[13]

[14] are formed, thereby forming a schematic diagram of the overall structure. In Figure 9-10 The main difference in electrode design in the schematic diagram is the location of the source and drain electrodes

[13] and

[14] . Figure 9-10In the tree-like nanowire branch field effect transistor, multiple source / drain electrodes can be interconnected to form a common source or common drain structure; or a single source / drain electrode can be formed, which greatly enriches the multifunctional transistor array design combination. The source / drain electrode can be prepared through the top of the trunk nanowire, and the horizontal wrap-around gate field effect transistor of the entire tree-like nanowire is a common source or common drain structure; or the source / drain electrode can be prepared through the electrode contact area of ​​the branch nanowire part, and the common source or common drain structure of different regions can be designed; so that the horizontal wrap-around gate field effect transistor of the entire tree-like nanowire has multiple control combinations.

[0071] Fig.10 Schematic diagram of top view of novel electrode design in an embodiment of the present invention; wherein (a) electrode design-1 top view; (b) electrode design-2 top view; (c) electrode design-3 top view; (d) electrode design-4 top view. After the gate metal

[12] , source / drain metal

[13]

[14] of a single tree-like nanowire branch field effect transistor are completed, the gate metal and source / drain metal Pad leads are respectively

[16] ,

[15] ,

[18] . The electrode metal Pad leads can be selected from the gaps of the six branch nanowires of the tree-like nanowire through circuit design. After the electrode metal is successfully prepared, the overall process is filled with photoresist, and the electrode metal Pad lead opening structure is formed through masking, exposure and other photolithography processes, that is, the positions

[16] ,

[15] ,

[18] are exposed. Electrode metal pad leads are prepared through electrode preparation processes such as magnetron sputtering and thermal evaporation. Then, the gate metal

[12] and source / drain metal

[13]

[14] are connected to the external metal pad through the electrode metal pad leads

[16] ,

[15] ,

[18] through lead equipment to form a chip.

[0072] Through the design of the present invention, the transistor interconnection between the computing unit and the storage unit realizes the physical xyz three-dimensional addressing address, that is, provides a primary address, and the addressing in the software algorithm provides a secondary address, which shortens the access time of the computing unit to the storage unit, thereby realizing an AI chip with a new architecture.

Claims

1. A highly integrated transistor, characterized in that: It comprises a columnar trunk structure located on a substrate, and one or more branch structures epitaxially grown from the columnar trunk structure; the columnar trunk structure and the branch structures form a tree structure; A single branch structure or a plurality of branch structures constitutes a transistor.

2. The transistor according to claim 1, characterized in that The columnar backbone structure is a one-dimensional nanowire.

3. The transistor according to claim 1, characterized in that The columnar trunk structure can be made of insulating dielectric material, conductive material, highly doped semiconductor material or low doped semiconductor material.

4. The transistor according to claim 1, characterized in that A single branch structure constitutes a transistor, and the branch structure has a high-concentration doping region as a source region, a high-concentration doping region as a drain region, and a low-concentration doping region as a channel region.

5. The transistor according to claim 4, characterized in that The source region, channel region, and drain region are arranged in sequence to form the main part.

6. The transistor according to claim 4, characterized in that There is a partition region between the source region and the drain region. The source region, the partition region and the drain region form the main body of the branch structure; the channel region is located at the periphery of the main body.

7. The transistor according to claim 6, characterized in that The channel region surrounds the isolation region.

8. The transistor according to claim 1, characterized in that Two branch structures constitute a transistor, wherein one branch structure has a high-concentration doped region as a source region, and the other branch structure has a high-concentration doped region as a drain region; the source region and the drain region are located at the outer ends of the branch structures, and the inner ends of the two branch structures have low-concentration doped regions; the two low-concentration doped regions and the columnar trunk structure or the peripheral medium constitute a channel region.

9. The transistor according to claim 1, characterized in that Two branch structures constitute a transistor, wherein one branch structure has a high-concentration doped region as a source region, and the other branch structure has a high-concentration doped region as a drain region; the source region and the drain region are located at the outer ends of the branch structures, and the inner ends of the two branch structures have a partition region; the partition region at the inner end and the high-concentration doped region located at the outer end constitute the main part of the branch structure; the periphery of the main part of the branch structure is also surrounded by a layer of low-concentration doped semiconductor medium; the low-concentration doped semiconductor media on the two branch structures are connected to form a channel region.

10. The transistor according to claim 9, characterized in that The channel region surrounds the two branch structure main parts.

11. The transistor according to claim 1, characterized in that The columnar trunk structure is a semiconductor medium or a conductor medium doped with a high concentration. The columnar trunk structure is a part of a transistor, and realizes a common source or a common drain of multiple branches thereon.

12. The transistor according to claim 1, characterized in that The columnar trunk structure is an insulating medium, and the two branch structures form a transistor; one branch structure has a high-concentration doped region as a source region, and the other branch structure has a high-concentration doped region as a drain region; the columnar trunk structure surrounds a low-concentration doped semiconductor medium and forms a channel region between the source and the drain.

13. The method for preparing a transistor according to claim 1, wherein: At least: (1) Growing nanowires on a substrate to form a columnar trunk structure; (2) Growing branch nanowires on the columnar trunk structure; and changing the growth conditions during the growth process to adjust the elemental composition during the growth.

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