Two-transistor embedded flash memory array

Abstract

The invention provides a double-transistor embedded flash memory array. The double-transistor embedded flash memory array comprises a plurality of memory units which are arranged on a substrate in rows and columns, each storage unit comprises a selection tube and a storage tube which are arranged in pairs along a first direction; the active area of the storage array comprises a plurality of strip-shaped first active areas extending along a first direction and a strip-shaped second active area along a second direction; the selection tubes and the storage tubes of the two adjacent storage units in the first direction are arranged in a mirroring mode relative to the second active area, each storage unit forms a second electrode on the second active area, and the second active area is connected with the second electrodes of all the storage units in the second direction. According to the storage array, the continuous active regions are added in the word line direction, and one side of the substrate can be connected with the source line, so that the space between two control grids of an existing structure is reduced, the size of a storage unit is greatly reduced, and the storage density of the storage array is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor devices, in particular to a dual-transistor embedded flash memory array. Background Art

[0002] SONOS (Silicon-Oxide-Nitride-Oxide-Silicon) memory is a memory with simple structure and high reliability, which is widely used in embedded storage. SONOS memory is usually composed of a 2T (2Transistor) structure of a selector (SG) and a memory tube (MG). The SONOS memory tube is formed from substrate silicon, tunneling oxide layer, trap nitride layer, barrier oxide layer and polysilicon stack from bottom to top. The SONOS flash memory array forms a source line (SL) through the source terminal CT (SCT), a node line (BL) through the drain terminal CT (DCT), and a word line (WL) through the gate of the selector and the memory tube. In order to pursue a smaller area, the miniaturization of the gate of the selector and the memory tube has approached the limit. How to reduce the area of ​​the memory cell by designing the distribution of the memory cell in the memory array and thus improve the storage density has always been a technical problem to be solved in the storage field.

[0003] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present invention, and therefore may include information that does not constitute the prior art known to those skilled in the art. Summary of the invention

[0004] In view of the problems in the prior art, the purpose of the present invention is to provide a dual-transistor embedded flash memory array, which can be connected to the source line on one side of the substrate by adding a continuous source active area in the word line direction, thereby reducing the space required for the metal contact connecting the source to be set between the two control gates in the existing structure, greatly reducing the size of the memory cell and improving the storage density of the memory array.

[0005] Specifically, the present invention provides a dual-transistor embedded flash memory array, the memory array comprising a plurality of memory cells arranged in rows and columns on a substrate;

[0006] Each of the storage units comprises a selection tube and a storage tube arranged in a first direction;

[0007] The active area of ​​the memory array includes a plurality of first active areas in a strip shape extending along a first direction and a second active area in a strip shape extending along a second direction;

[0008] The selection tubes and storage tubes of two adjacent storage cells along the first direction are arranged in a mirror image relative to the second active area, each storage cell forms a second electrode on the second active area, and the second active area connects the second electrodes of all storage cells along the second direction.

[0009] According to some examples of the present invention, the second electrode is a source of the memory cell, or the second electrode is a drain of the memory cell.

[0010] According to some examples of the present invention, the resistivity of the second active region is 80-100 ohm / count.

[0011] According to some examples of the present invention, the memory array further comprises a plurality of bit lines;

[0012] A first electrode of the memory cell is formed on the first active region of each memory cell, and each of the first electrodes is connected to a bit line through a first through hole;

[0013] And the first electrodes of the plurality of memory cells along the first direction are connected to the same bit line.

[0014] According to some examples of the present invention, the second active region is connected to a source line of the memory array through a second through hole.

[0015] According to some examples of the present invention, the second through hole is arranged on one side of the second direction of the substrate.

[0016] According to some examples of the present invention, the storage array further includes:

[0017] A plurality of word lines, each of the word lines is connected to the gates of the storage tubes in a plurality of the storage cells in the same column.

[0018] According to some examples of the present invention, the selection tube and / or the storage tube is a charge capture type storage tube; or

[0019] The selection tube and / or the storage tube is a floating gate storage tube.

[0020] According to some examples of the present invention, both the selection tube and the storage tube are N-type storage tubes.

[0021] According to some examples of the present invention, both the selection tube and the storage tube are P-type storage tubes.

[0022] The dual-transistor embedded flash memory array of the present invention increases an active area in the word line direction, the active area is connected to the source electrodes of multiple memory cells in the word line direction of the storage arrangement, the active area can be connected to the remote source terminal through a through hole, and the memory array forms a source line through the source terminal, thereby reducing the spacing between the gates on both sides and realizing the miniaturization of the memory cell area. Taking the 55nm process node (the minimum characteristic size of the transistor in the integrated circuit) as an example, the area of ​​the memory cell of the present invention can be reduced by 8.3% to 10.4%, greatly improving the storage density. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The drawings herein are incorporated into the specification and constitute a part of the specification, showing embodiments consistent with the present application, and together with the specification, are used to explain the principles of the present application. By reading the detailed description of the non-limiting embodiments with reference to the following drawings, other features, purposes and advantages of the present invention will become more apparent. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can also be obtained based on these drawings without creative work. In addition, the drawings are only schematic illustrations of the present disclosure and are not necessarily drawn to scale. The same figure numbers in the figures represent the same or similar parts, and their repeated descriptions will be omitted. Some of the block diagrams shown in the drawings are functional entities and do not necessarily correspond to physically or logically independent entities.

[0024] Figure 1 A layout diagram of a dual-transistor embedded flash memory array according to an embodiment of the present invention;

[0025] Figure 2 A schematic diagram of a cross-sectional structure of two adjacent storage units along a first direction according to an embodiment of the present invention; and

[0026] Figure 3 It is a schematic cross-sectional structural diagram of two adjacent storage units along a first direction according to another embodiment of the present invention. DETAILED DESCRIPTION

[0027] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in the present invention. The present invention can also be implemented or applied through other different specific embodiments, and the details in the present invention can also be modified or changed according to different viewpoints and application systems without departing from the spirit of the present invention. It should be noted that the embodiments and features in the embodiments of the present invention can be combined with each other without conflict.

[0028] The following is a detailed description of the embodiments of the present invention with reference to the accompanying drawings so that those skilled in the art can easily implement the present invention. The present invention can be embodied in many different forms and is not limited to the embodiments described herein.

[0029] In the representation of the present invention, the reference terms "one embodiment", "some embodiments", "examples", "specific examples", or "some examples" etc. mean that the specific features, structures, materials or characteristics represented in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. Moreover, the specific features, structures, materials or characteristics represented may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine different embodiments or examples represented in the present invention and the features of different embodiments or examples, unless they are contradictory.

[0030] In order to clearly describe the present invention, components not related to the description are omitted, and the same reference numerals are given to the same or similar components throughout the specification.

[0031] Throughout the specification, when a device is said to be "connected" to another device, this includes not only the case of "direct connection" but also the case of "indirect connection" by placing other elements therebetween. In addition, when a device is said to "include" a certain component, unless otherwise stated, it does not exclude other components, but means that other components may be included.

[0032] When a device is said to be "on" another device, it may be directly on the other device, but there may also be other devices between it. In contrast, when a device is said to be "directly" on another device, there are no other devices between it.

[0033] Although the terms first, second, etc. are used to represent various elements in some examples, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, the first interface and the second interface, etc. are represented. Moreover, as used in this article, the singular forms "one", "one" and "the" are intended to also include plural forms, unless there is an opposite indication in the context. It should be further understood that the terms "comprising" and "including" indicate the existence of features, steps, operations, elements, components, projects, kinds, and / or groups, but do not exclude the existence, occurrence or addition of one or more other features, steps, operations, elements, components, projects, kinds, and / or groups. The terms "or" and "and / or" used herein are interpreted as inclusive, or mean any one or any combination. Therefore, "A, B or C" or "A, B and / or C" means "any of the following: A; B; C; A and B; A and C; B and C; A, B and C". Only when the combination of elements, functions, steps or operations is inherently mutually exclusive in some way, will there be an exception to this definition.

[0034] The technical terms used herein are only used to refer to specific embodiments and are not intended to limit the present invention. The singular form used herein also includes the plural form as long as the sentence does not clearly indicate the opposite meaning. The meaning of "including" used in the specification is to specify specific characteristics, regions, integers, steps, operations, elements and / or components, and does not exclude the existence or addition of other characteristics, regions, integers, steps, operations, elements and / or components.

[0035] Although not defined differently, all terms, including technical and scientific terms used herein, have the same meaning as those generally understood by those skilled in the art to which the present invention belongs. Terms defined in commonly used dictionaries are additionally interpreted as having meanings consistent with the content of relevant technical literature and current disclosures, and unless defined, shall not be overly interpreted as ideal or very formal meanings.

[0036] In response to the existing technical problems, the present invention provides a dual-transistor embedded flash memory array, the memory array comprising a plurality of memory cells arranged in rows and columns on a substrate; each of the memory cells comprises a selection tube and a storage tube arranged in a first direction; the active area of ​​the memory array comprises a plurality of first active areas in the form of strips extending along the first direction and a second active area in the form of strips extending along the second direction; the arrangement of the selection tubes and the storage tubes of two adjacent memory cells along the first direction is mirrored relative to the second active area, each of the memory cells forms a source on the second active area, and the second active area connects the sources of all the memory cells along the second direction.

[0037] The dual-transistor embedded flash memory array of the present invention increases an active area in the word line direction, the active area is connected to the source electrodes of multiple memory cells in the word line direction of the storage arrangement, the active area can be connected to the remote source terminal through a through hole, and the memory array forms a source line through the source terminal, thereby reducing the spacing between the gates on both sides and realizing the miniaturization of the memory cell area. Taking the 55nm process node (the minimum characteristic size of the transistor in the integrated circuit) as an example, the area of ​​the memory cell of the present invention can be reduced by 8.3% to 10.4%, greatly improving the storage density.

[0038] The structure of the dual-transistor embedded flash memory array of the present invention is further described below in conjunction with the accompanying drawings and specific embodiments. It should be understood that the specific embodiments are not intended to limit the protection scope of the present invention.

[0039] Figure 1 1 is a layout diagram of a dual-transistor embedded flash memory array according to an embodiment of the present invention. Specifically, the dual-transistor embedded flash memory array includes a plurality of memory cells 100 / 100' arranged in rows and columns on a substrate. Figure 2 The cross-sectional structure diagram of two adjacent memory cells along the first direction of an embodiment of the present invention, each of the memory cells 100 / 100' comprises a selection tube SG and a storage tube MG arranged in a pair along the first direction. The memory cell of the present invention is a memory cell structure with two transistors (2T) with an additional control gate structure, each memory cell having a selection tube and a storage tube connected in series, at which time, the selection tube and the storage tube share a terminal therebetween, which serves as the drain of the storage tube and the source of the selection tube. The use of a two-transistor structure can completely separate the control gate and the selection gate, greatly reducing the voltage between the source (S) and the drain (D), and further reducing the possibility of half-selection destruction. For convenience, the gate is used herein to refer to the transistor in the memory cell structure, such as the selection tube SG and the storage tube MG.

[0040] In an embodiment, the selection tube SG and / or the storage tube MG may be a charge trapping flash (CTF), and in some other embodiments, the selection tube and / or the storage tube may be a floating gate storage tube. The basic reading and writing principle of the charge trapping flash is the same as that of the floating gate, but the medium of the charge storage bit between the charge trapping flash and the floating gate flash is different. The floating gate type Flash stores the charge in the floating gate and isolates it through the intermediate oxide layer. After repeated erasure and writing, the oxide layer of the floating gate structure Flash is prone to defects. Since the floating gate is a conductor, once the isolation oxide layer has defects, the electrons in the floating gate will be lost from the defects, resulting in the loss of Flash storage information. In the floating gate process, the reliability of the Flash is often improved by thickening the oxide layer. Increasing the thickness of the gate oxide layer will increase the threshold voltage, and the adverse effect brought about is to reduce the erasure speed of the Flash. The charge trapping type can reduce the problem of poor reliability caused by repeated erasure and writing.

[0041] The active area of ​​the memory array is an N-type doped area or a P-type doped area, and the active area of ​​the memory array includes a plurality of first active areas 101 in a strip shape extending along a first direction and a second active area 102 in a strip shape extending along a second direction; here, the first direction can be Figure 1 The second direction is the X direction in the image, and the second direction may be a direction forming a certain angle with the first direction. In practice, when the second direction is perpendicular to the first direction, the corresponding storage density is the highest. Therefore, in the present application, the second direction is the Y direction perpendicular to the first direction.

[0042] The arrangement of the selection tube SG and the storage tube MG of two adjacent storage cells along the first direction is mirrored relative to the second active area 102, or is called a symmetrical arrangement, each of the storage cells forms a second electrode on the second active area 102, and the second active area 102 connects the second electrodes of all the storage cells along the second direction. Figure 2 As shown, the memory cell here is mirrored relative to the second active region 102, which means that when the memory cell 100' includes a drain D, a select gate SG, a control gate MG and a source S arranged along the X direction, the memory cell 100 mirrored therewith includes a source S, a control gate MG, a select gate SG and a drain D in the X direction. In this embodiment, it can be seen that the source S of the memory cell 100' and the source S of the memory cell 100 are formed at the second active region 102, and the source S of the memory cell 100' and the source S of the memory cell 100 are shared, that is, the second electrode is the source S of the memory cell. At the same time, the multiple sources S of the multiple memory cells arranged along the Y direction are electrically connected through the second active region 102 extending along the Y direction.

[0043] In other embodiments, the second electrode may be a drain D of the memory cell. Figure 3 As shown, the memory cell on the left side of the second active area 102 is sequentially arranged with a source S, a control gate MG, a select gate SG and a drain D in the X direction, while the memory cell on the right side of the second active area 102 is sequentially arranged with a drain D, a select gate SG, a control gate MG and a source S in the X direction. At this time, the drain D of the memory cells 100 mirror-arranged on both sides of the second active area 102 is shared, and the multiple drains D of the multiple memory cells arranged along the Y direction are electrically connected through the second active area 102 extending along the Y direction.

[0044] The second active region 102 can be obtained by photolithography and ion implantation, and the type of ion implantation can be selected according to the conductivity type of the source S / drain D at that location. As shown above, the second electrodes of the plurality of memory cells arranged along the Y direction are electrically connected through the second active region 102. Accordingly, the resistivity of the second active region 102 needs to be relatively low. The second active region 102 with low resistivity can be obtained by controlling the concentration of ion implantation in the region, that is, the doping concentration of the ion implantation at that location can be increased, thereby improving the conductivity of the second active region 102. Preferably, the resistivity of the second active region 102 is 80-100 ohm / count, which is lower than the resistivity of the existing active region (400-600 ohm / count).

[0045] The storage cells arranged along an X direction can be arranged inside and on the surface of the same injection well on the substrate. When the injection well is P-type, the selection tube SG and the storage tube MG are both N-type storage tubes; when the injection well is N-type, the selection tube SG and the storage tube MG are both P-type storage tubes. The active area of ​​the storage tube is P-type.

[0046] At the same time, each memory array includes a plurality of word lines WLn-1, WLn, ..., wherein the word lines connect the gates of the memory tubes MG in the plurality of memory cells in the same column. For example, the word line WLn-1 connects the gates of the memory tubes MG in the plurality of memory cells arranged along the Y direction on the left side of the second active area 102, and the gates of the selection tubes SG in the plurality of memory cells arranged along the Y direction on the left side of the second active area 102 can be connected through a gate line SGn-1. Since the memory cells on both sides of the second active area 102 are symmetrically arranged, the word line WLn connects the gates of the memory tubes MG in the plurality of memory cells arranged along the Y direction on the right side of the second active area 102, and the gates of the selection tubes SG in the plurality of memory cells arranged along the Y direction on the right side of the second active area 102 can be connected through a gate line SGn.

[0047] The memory array further includes a plurality of bit lines (BL). The first electrode of the memory cell 100 or the first electrode of the memory cell 100' is formed on the first active region 101 of each memory cell. When the second electrode is the source S of the memory cell, the first electrode of the memory cell formed on the first active region is the drain D of the memory cell; when the second electrode is the drain D of the memory cell, the first electrode of the memory cell formed on the first active region is the source S drain of the memory cell. Each first electrode is connected to a bit line through a first through hole A, and the first electrodes of a plurality of memory cells along the first direction are connected to the same bit line. Figure 2 As shown, the drain D of the memory cell 100 and the drain D of the memory cell 100' are connected to the bit line BLm-1. More specifically, a metal contact is formed above the drain D of the memory cell, which is the bit line terminal DCT of the memory cell, and the bit line terminal DCT is connected to the bit line BL of the memory array.

[0048] A plurality of bit lines BLm+3, BLm+2, BLm+2, BLm, BLm-1, BLm-2, ... are arranged orthogonally to the plurality of word lines WL. Since the second active area 102 needs to be electrically connected to the second electrodes of the plurality of memory cells arranged along the Y direction, the second active area 102 is usually arranged in parallel with the plurality of word lines. At the same time, the second active area 102 is connected to the source line SL of the memory array only through a second through hole B. More specifically, a metal contact is formed at the second through hole, and the metal contact is the source terminal SCT of the memory array, and the source terminal SCT is connected to the source line SL of the memory array. It can be seen that by electrically connecting the source electrodes S of the memory cells arranged along the Y direction of the memory array through the second active area 102, the plurality of source electrodes S of the memory cells in the array can be led to the source line SL through only one through hole, thereby saving the space occupied by the setting of a source terminal SCT for each memory cell in the existing storage organization structure. In one embodiment, the second through hole B can be arranged on one side of the second direction (Y direction) of the substrate, from Figure 1 It can be seen that, since the source terminal SCT does not need to be arranged between the gates on both sides of the second active region, the distance between the gates on both sides can be reduced, thereby reducing the area of ​​a single memory cell.

[0049] It should be noted that the number of memory cells that can be electrically connected to a second active region in the present invention can be further determined based on the structure (size) of the memory cell itself, the structure (size) of the second active region, and the conductivity of the second active region. In actual use, a memory device may include a plurality of the above-mentioned memory arrays. Taking the 55nm process node (the minimum feature size of transistors in integrated circuits) as an example, the area of ​​the memory cell of the present invention can be reduced by 8.3% to 10.4%, greatly improving the storage density.

[0050] Although the embodiments of the present invention have been shown and described above, it is to be understood that the above embodiments are exemplary and are not to be construed as limitations of the present invention. A person skilled in the art may change, modify, replace and vary the above embodiments within the scope of the present invention.

[0051] The above contents are further detailed descriptions of the present invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is limited to these descriptions. For ordinary technicians in the technical field to which the present invention belongs, several simple deductions or substitutions can be made without departing from the concept of the present invention, which should be regarded as falling within the protection scope of the present invention.

Claims

1. A dual-transistor embedded flash memory array, characterized in that: The memory array includes a plurality of memory cells arranged in rows and columns on a substrate; Each of the storage units comprises a selection tube and a storage tube arranged in a first direction; The active area of ​​the memory array includes a plurality of first active areas in a strip shape extending along a first direction and a second active area in a strip shape extending along a second direction; The selection tubes and storage tubes of two adjacent storage cells along the first direction are arranged in a mirror image relative to the second active area, each storage cell forms a second electrode on the second active area, and the second active area connects the second electrodes of all storage cells along the second direction.

2. The dual-transistor embedded flash memory array according to claim 1, characterized in that: The second electrode is a source of the memory cell, or the second electrode is a drain of the memory cell.

3. The dual-transistor embedded flash memory array according to claim 1, characterized in that: The resistivity of the second active region is 80-100 ohm / count.

4. The dual-transistor embedded flash memory array according to claim 1, characterized in that: The memory array further comprises a plurality of bit lines; A first electrode of the memory cell is formed on the first active region of each memory cell, and each of the first electrodes is connected to a bit line through a first through hole; And the first electrodes of the plurality of memory cells along the first direction are connected to the same bit line.

5. The dual-transistor embedded flash memory array according to claim 1, characterized in that: The second active area is connected to the source line of the memory array through a second through hole.

6. The dual-transistor embedded flash memory array according to claim 5, characterized in that: The second through hole is arranged on one side of the substrate in the second direction.

7. The dual-transistor embedded flash memory array according to claim 1, characterized in that: The storage array further comprises: A plurality of word lines, each of the word lines is connected to the gates of the storage tubes in a plurality of the storage cells in the same column.

8. The dual-transistor embedded flash memory array according to claim 1, characterized in that: The selection tube and / or the storage tube is a charge trapping storage tube; or The selection tube and / or the storage tube is a floating gate storage tube.

9. The dual-transistor embedded flash memory array according to claim 1, characterized in that: The selection tube and the storage tube are both N-type storage tubes.

10. The dual-transistor embedded flash memory array according to claim 1, characterized in that: The selection tube and the storage tube are both P-type storage tubes.

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