Novel temperature compensation type TC-SAW process

Abstract

The invention relates to a novel temperature compensation type TC-SAW (Temperature Compensation Surface Acoustic Wave) process, which belongs to the field of temperature compensation type surface acoustic wave filters, and comprises the following steps: firstly, forming an IDT metal pattern on an LN substrate; preparing a hot oxygen silicon wafer, and grooving the SiO2 layer to present a shape corresponding to the IDT pattern; bonding the LN substrate and the slotted hot oxygen silicon wafer by adopting a bonding process; thinning and chemically and mechanically polishing the silicon substrate and the SiO2 layer; siO2 in the target area is etched; evaporating a thickening layer metal on the SiO2; and a passivation layer is deposited, and holes are formed in the passivation layer at the PAD position. The SiO2 temperature compensation layer formed by the thermal oxidation silicon wafer is few in defect, high in compactness, better in temperature compensation effect and higher in TCF coefficient. Meanwhile, SiO2 dust can be prevented from appearing in the SiO2 sputtering process, and the influence on the performance of the device can be avoided.

Description

Technical Field

[0001] The invention belongs to the field of temperature-compensated surface acoustic wave filters, and in particular relates to a novel temperature-compensated TC-SAW process. Background Art

[0002] The temperature-compensated surface acoustic wave filter (TC-SAW for short) is a technical improvement on the conventional SAW filter by covering its IDT with a temperature compensation layer, so that the frequency temperature coefficient (TCF) of the device is reduced to 0 to -25ppm / ℃, which is a significant improvement over the temperature characteristics of conventional SAW (usually about -45 to -60ppm / ℃).

[0003] The traditional technology uses a sputtering process to directly sputter the SiO2 temperature compensation layer on the LN substrate. The sputtering power is large, and the morphology and density of the SiO2 film formed are relatively poor. In addition, the sputtering process is prone to form SiO2 dust, which affects the performance of the device. In addition, the SiO2 temperature compensation layer formed by the traditional sputtering process has a large difference in film thickness between the SiO2 on the LN substrate and the SiO2 on the IDT, which in turn affects the performance of the device. It takes a long time for CMP to grind the SiO2 film thickness difference to within 1nm. Summary of the invention

[0004] The present invention aims at the problems of relatively poor film morphology and film density in the existing SiO2 temperature compensation layer preparation process, as well as large film thickness difference between the substrate and the IDT, and proposes a new temperature compensation type TC-SAW process. The present invention grooves one side of the SiO2 film of the thermal oxide silicon wafer to present the shape corresponding to the IDT pattern; uses a bonding process to bond the LN substrate and the thermal oxide silicon wafer after the groove; and thins and chemically mechanically polishes the silicon substrate and SiO2 to form a SiO2 temperature compensation layer. The SiO2 temperature compensation layer has high flatness, simplifies the production process, and saves production costs.

[0005] In order to achieve the above object, the present invention is implemented by the following technical scheme: a new temperature compensation TC-SAW process is carried out according to the following steps:

[0006] Step 1) cleaning the substrate to prepare for subsequent photolithography;

[0007] Step 2) Preparation of interdigital electrodes: coating, exposing and developing photoresist on the substrate to make the photoresist present a shape corresponding to the finger stripe, evaporating metal on the substrate, and using a lift-off process to peel off the photoresist and the metal deposited on the photoresist to form interdigital electrodes corresponding to the IDT pattern;

[0008] Step 3) preparing a thermal oxide silicon wafer, wherein the thickness of the SiO2 layer of the thermal oxide silicon wafer is 0.5 to 2 μm;

[0009] Step 4) grooves are formed on one side of the SiO2 of the thermal oxide silicon wafer to form grooves corresponding to the interdigital electrode pattern;

[0010] Step 5) flipping the thermal oxide silicon wafer so that the SiO2 side faces the substrate, and bonding the substrate and the thermal oxide silicon wafer using a bonding process;

[0011] Step 6) Thinning the thermal oxide silicon wafer to completely remove the Si substrate and remove part of the SiO2;

[0012] Step 7) performing CMP polishing on the thinned SiO2 film layer;

[0013] Step 8) coating, exposing and developing the photoresist so that the photoresist shape presents a corresponding shape and etching SiO2 in the corresponding area;

[0014] Step 9) evaporating MET metal on the SiO2 film layer, and then depositing a second dielectric layer on the MET metal;

[0015] Step 10) performing hole etching on the passivation layer to etch away the film layer in the PAD pattern area.

[0016] Furthermore, the substrate is a lithium niobate LN substrate.

[0017] Furthermore, the bonding process adopts adhesive bonding, or eutectic bonding, or thermal compression bonding.

[0018] Furthermore, the thickness of the thinned SiO2 film layer is 1.2-1.4 μm.

[0019] Compared with the prior art, the present invention has the following beneficial effects:

[0020] 1. The present invention is different from the traditional TC-SAW process. The thermally oxidized silicon wafer is bonded to the LN substrate through a bonding process. Compared with directly sputtering SiO2 on the LN substrate, the SiO2 film layer of the thermally oxidized silicon wafer has fewer defects, higher density, better temperature compensation effect, and higher TCF coefficient. At the same time, it can avoid the generation of SiO2 dust during the sputtering process of SiO2, which affects the performance of the device.

[0021] 2. The present invention uses a bonding method to bond the slotted thermal oxide silicon wafer and the LN substrate plated with IDT. The SiO2 film has high flatness, simplifies the production process of the temperature compensation surface acoustic wave filter, and saves production costs.

[0022] 3. The present invention uses thermal oxide silicon wafers to bond with the substrate instead of using SiO2 wafers to bond directly with the substrate. Since SiO2 wafers are difficult to prepare and the temperature compensation coefficient of SiO2 wafers on the market cannot meet the requirements of TC-SAW, the SiO2 thickness required by this process is relatively thin, and thermal oxide silicon wafers can meet the requirements. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 Schematic diagram of LN substrate.

[0024] Figure 2 Schematic diagram of the preparation of interdigitated electrodes.

[0025] Figure 3 Schematic diagram of thermal oxide silicon wafer.

[0026] Figure 4 Schematic diagram of trenching a thermal oxide silicon wafer.

[0027] Figure 5 Schematic diagram of thermal oxide bonding between silicon wafer and substrate.

[0028] Figure 6 Schematic diagram of thinning a thermal oxide silicon wafer.

[0029] Figure 7 Schematic diagram of CMP polishing.

[0030] Figure 8 Schematic diagram of photoresist coating for MET.

[0031] Fig. 9 Schematic diagram of MET metal evaporation.

[0032] Fig.10 It is a schematic diagram of the structure of the temperature compensation surface acoustic wave filter of the present invention. DETAILED DESCRIPTION

[0033] The following will describe the implementation methods of the present invention in detail with reference to the accompanying drawings and examples, so as to fully understand and implement the implementation process of how the present invention applies technical means to solve technical problems and achieve technical effects.

[0034] Embodiment 1

[0035] A new temperature-compensated TC-SAW process is carried out in the following steps:

[0036] Step 1) Figure 1 As shown, a LN substrate is provided and cleaned in preparation for subsequent photolithography.

[0037] Step 2) Preparation of interdigitated electrodes: Figure 1 As shown, photoresist is coated, exposed, and developed on the substrate to make the photoresist shape present a corresponding finger shape, metal is evaporated on the substrate, and a lift-off process is used to peel off the photoresist and the metal deposited on the photoresist to form interdigital electrodes corresponding to the IDT pattern.

[0038] Step 3) Prepare Figure 3The thermal oxide silicon wafer shown in the figure consists of a lower Si layer and an upper SiO2 layer. The thickness of the SiO2 layer of the thermal oxide silicon wafer is 1 μm.

[0039] Step 4) groove one side of the SiO2 of the prepared thermal oxide silicon wafer, such as Figure 4 As shown, grooves corresponding to the interdigital electrode patterns are formed.

[0040] Step 5) Figure 5 As shown, the thermal oxide silicon wafer is turned over so that the SiO2 layer side is opposite to the substrate, and the substrate and the thermal oxide silicon wafer are bonded by adhesive bonding.

[0041] Step 6) Thinning the thermal oxide silicon wafer, such as Figure 6 As shown, the Si layer of the thermal oxide silicon wafer is completely removed and part of the SiO2 layer is removed.

[0042] Step 7) Figure 7 As shown, the thinned SiO2 layer is subjected to CMP polishing, and the thickness of the thinned SiO2 layer is 1.2 μm.

[0043] Step 8) photoresist coating, exposure, and development, such as Figure 8 As shown, the photoresist shape is made to present a corresponding shape, and the SiO2 layer in the corresponding area is etched.

[0044] Step 9) Fig. 9 As shown, MET metal is evaporated on the SiO2 film layer, and then a second dielectric layer is deposited on the MET metal. The second dielectric layer is SiN x .

[0045] Step 10) Fig.10 As shown, the passivation layer is etched to open holes and the film layer in the PAD pattern area is etched away.

[0046] Embodiment 2

[0047] A new temperature-compensated TC-SAW process is carried out in the following steps:

[0048] Step 1) Figure 1 As shown, a LN substrate is provided and cleaned in preparation for subsequent photolithography.

[0049] Step 2) Preparation of interdigitated electrodes: Figure 1 As shown, photoresist is coated, exposed, and developed on the substrate to make the photoresist shape present a corresponding finger shape, metal is evaporated on the substrate, and a lift-off process is used to peel off the photoresist and the metal deposited on the photoresist to form interdigital electrodes corresponding to the IDT pattern.

[0050] Step 3) Prepare Figure 3The thermal oxide silicon wafer shown in the figure consists of a lower Si layer and an upper SiO2 layer. The thickness of the SiO2 layer of the thermal oxide silicon wafer is 1.5μm.

[0051] Step 4) groove one side of the SiO2 of the prepared thermal oxide silicon wafer, such as Figure 4 As shown, grooves corresponding to the interdigital electrode patterns are formed.

[0052] Step 5) Figure 5 As shown, the thermal oxide silicon wafer is turned over so that the SiO2 layer side is opposite to the substrate, and the substrate and the thermal oxide silicon wafer are bonded by adhesive bonding.

[0053] Step 6) Thinning the thermal oxide silicon wafer, such as Figure 6 As shown, the Si layer of the thermal oxide silicon wafer is completely removed and part of the SiO2 layer is removed.

[0054] Step 7) Figure 7 As shown, the thinned SiO2 layer is subjected to CMP polishing, and the thickness of the thinned SiO2 layer is 1.3 μm.

[0055] Step 8) photoresist coating, exposure, and development, such as Figure 8 As shown, the photoresist shape is made to present a corresponding shape, and the SiO2 layer in the corresponding area is etched.

[0056] Step 9) Fig. 9 As shown, MET metal is evaporated on the SiO2 film layer, and then a second dielectric layer is deposited on the MET metal. The second dielectric layer is AlN x .

[0057] Step 10) Fig.10 As shown, the passivation layer is etched to open holes and the film layer in the PAD pattern area is etched away.

[0058] Embodiment 3

[0059] A new temperature-compensated TC-SAW process is carried out in the following steps:

[0060] Step 1) Figure 1 As shown, a LN substrate is provided and cleaned in preparation for subsequent photolithography.

[0061] Step 2) Preparation of interdigitated electrodes: Figure 1 As shown, photoresist is coated, exposed, and developed on the substrate to make the photoresist shape present a corresponding finger shape, metal is evaporated on the substrate, and a lift-off process is used to peel off the photoresist and the metal deposited on the photoresist to form interdigital electrodes corresponding to the IDT pattern.

[0062] Step 3) Prepare Figure 3The thermal oxide silicon wafer shown in the figure consists of a lower Si layer and an upper SiO2 layer. The thickness of the SiO2 layer of the thermal oxide silicon wafer is 2μm.

[0063] Step 4) groove one side of the SiO2 of the prepared thermal oxide silicon wafer, such as Figure 4 As shown, grooves corresponding to the interdigital electrode patterns are formed.

[0064] Step 5) Figure 5 As shown, the thermal oxide silicon wafer is turned over so that the SiO2 layer side is opposite to the substrate, and the substrate and the thermal oxide silicon wafer are bonded by adhesive bonding.

[0065] Step 6) Thinning the thermal oxide silicon wafer, such as Figure 6 As shown, the Si layer of the thermal oxide silicon wafer is completely removed and part of the SiO2 layer is removed.

[0066] Step 7) Figure 7 As shown, the thinned SiO2 layer is subjected to CMP polishing, and the thickness of the thinned SiO2 layer is 1.4 μm.

[0067] Step 8) photoresist coating, exposure, and development, such as Figure 8 As shown, the photoresist shape is made to present a corresponding shape, and the SiO2 layer in the corresponding area is etched.

[0068] Step 9) Fig. 9 As shown, MET metal is evaporated on the SiO2 film layer, and then a second dielectric layer is deposited on the MET metal, and the second dielectric layer is amorphous silicon.

[0069] Step 10) Fig.10 As shown, the passivation layer is etched to open holes and the film layer in the PAD pattern area is etched away.

[0070] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed by the present invention should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention shall be based on the protection scope of the claims.

Claims

1. A new type of temperature-compensated TC-SAW process, Features: Follow these steps: Step 1) cleaning the substrate to prepare for subsequent photolithography; Step 2) Preparation of interdigital electrodes: coating, exposing and developing photoresist on the substrate to make the photoresist present a shape corresponding to the finger stripe, evaporating metal on the substrate, and using a lift-off process to peel off the photoresist and the metal deposited on the photoresist to form interdigital electrodes corresponding to the IDT pattern; Step 3) Prepare the thermal oxide silicon wafer. 2 The thickness of the layer is 0.5 to 2 μm; Step 4) Thermally oxidize the SiO2 wafer 2 One side of the layer is grooved to form a groove corresponding to the interdigital electrode pattern; Step 5) Flip the thermally oxidized silicon wafer to make SiO 2 One side is opposite to the substrate, and the substrate and the thermal oxide silicon wafer are bonded by a bonding process; Step 6) Thinning the thermal oxide silicon wafer to completely remove the Si substrate and remove part of the SiO 2 layer; Step 7) After thinning, SiO 2 The layer is subjected to CMP polishing; Step 8) photoresist coating, exposure, and development to make the photoresist shape present a corresponding shape, and etch the SiO2 in the corresponding area. 2 ; Step 9) In SiO 2 The MET metal is evaporated on the layer, and then a second dielectric layer is deposited on the MET metal; Step 10) performing hole etching on the passivation layer to etch away the film layer in the PAD pattern area.

2. A novel temperature-compensated TC-SAW process according to claim 1, Features: The substrate is a lithium niobate substrate.

3. A novel temperature-compensated TC-SAW process according to claim 1, Features: The bonding process adopts adhesive bonding, eutectic bonding, or thermal compression bonding.

4. A novel temperature-compensated TC-SAW process according to claim 1, Features: The thinned SiO 2 The thickness of the film layer is 1.2 to 1.4 μm.

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