Novel high-precision pulse modulation system and use method thereof
Through the new high-precision pulse modulation system, the calibration and delay chain modules are used to improve pulse accuracy without changing the PWM frequency, solving the problem of limited power quality and reliability, and achieving high-precision control of key parameters, which is suitable for Communications, radar and other fields.
Patent Information
- Application Number
- CN202411155168.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-22
- Publication Date
- 2024-12-13
AI Technical Summary
The existing PWM pulse modulation system is difficult to improve pulse accuracy without changing the frequency, resulting in limited power quality and reliability.
A new high-precision pulse modulation system was designed, including calibration module, high-precision control module, register group module, delay chain decoding module and modulation output module. The calibration was determined based on the external reference clock and delay chain self-loop oscillation clock through the calibration module. Counting, the number of delay steps is determined using calibration algorithm, and the delay code is calculated through the high-precision control module, the delay block circuit is enabled for delay processing, and the pulse modulation output is finally realized.
It significantly improves pulse accuracy without changing the PWM frequency, improves the quality and reliability of electrical energy, and can achieve high-precision control of parameters such as duty cycle, dead zone, period and phase, and is suitable for fields where precise waveform control is required.
Smart Images
Figure CN119135137A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of pulse modulation technology, and in particular to a novel high-precision pulse modulation system and a method for using the same. Background Art
[0002] The research and development background of HRPWM (high-precision pulse modulation circuit) mainly stems from the demand for high precision, high efficiency and high reliability of modern power electronic systems. More and more fields are beginning to apply high-precision pulse modulation systems to achieve precise control and efficient conversion of electrical energy.
[0003] For example, in the fields of renewable energy generation, electric vehicles, smart grids, etc., electric energy needs to be accurately converted and controlled to improve energy efficiency. HRPWM can achieve efficient conversion and utilization of electric energy by accurately adjusting the width and position of the pulse. In the fields of industrial automation, robotics, aerospace, etc., the motor is the core actuator. HRPWM can achieve precise speed and position control of the motor, improving the motion performance and response speed of the system. In the power system, problems such as harmonics and voltage fluctuations can affect the quality and stability of electric energy. By optimizing the pulse sequence, the HRPWM system can reduce harmonics and electromagnetic interference and improve the quality and reliability of electric energy.
[0004] At present, in the traditional electronic power field, PWM (pulse modulation system) is generally used to control current or voltage. The pulse width accuracy of the pulse is an important indicator to measure the accuracy of controlling the output voltage or current. With the rapid development of electronic technology, the system has higher and higher requirements for the frequency and accuracy of the control signal. However, the PWM pulse accuracy is naturally limited by the chip clock frequency. How to improve the pulse accuracy without changing the PWM frequency has become an urgent problem to be solved in the electronics industry. Summary of the invention
[0005] The purpose of this application is to provide a novel high-precision pulse modulation system and its use method, which can improve pulse accuracy and improve the quality and reliability of electric energy without changing the PWM frequency.
[0006] To achieve the above objectives, this application provides the following solutions:
[0007] In the first aspect, the present application provides a novel high-precision pulse modulation system, comprising: a calibration module, a high-precision control module, a register group module, a delay chain decoding module, a delay chain module and a modulation output module; the delay chain module comprises a plurality of delay block circuits; the register group module comprises a high-precision phase register, a high-precision period register, a high-precision duty cycle register and a high-precision dead zone register.
[0008] The calibration module is used to determine the calibration count according to the external reference clock signal and the delay chain self-loop oscillation clock signal, and determine the delay step number by using the calibration algorithm according to the calibration counts of different channels of the delay chain module; the high-precision control module is used to calculate the delay code according to the delay step number and the decimal delay count of the output result of the register group module; the delay chain decoding module is used to generate a delay code decoding result according to the delay code, and the delay code decoding result is an enable status signal of each delay block circuit; the delay chain module is used to enable the corresponding delay block circuit according to the delay code decoding result, delay the input pulse, and obtain a delayed output result; the pulse modulation output module is used to modulate and output according to the input pulse and the delayed output result.
[0009] Optionally, the calibration module includes: a first logic gate, a second logic gate, a third logic gate and a calibration block.
[0010] The first input end of the first logic gate is connected to an oscillation enable signal, the second input end of the first logic gate is connected to a self-loop oscillation output end of the delay chain module, the output end of the first logic gate outputs a delay chain self-loop oscillation clock signal, and the first input end of the delay chain module is connected to the output end of the first logic gate.
[0011] The first input end of the second logic gate is connected to the forced delay code, the second input end of the second logic gate is connected to the forced delay code write enable signal, the output end of the second logic gate outputs the forced delay signal, and the second input end of the delay chain module is connected to the output end of the second logic gate.
[0012] The first input end of the third logic gate is connected to the output end of the first logic gate, the second input end of the third logic gate is connected to the calibration enable signal, and the output end of the third logic gate outputs the delay chain self-loop oscillation clock signal.
[0013] The first input end of the calibration block is connected to the output end of the third logic gate, the first input end of the calibration block is connected to the external reference clock signal, and the output end of the calibration block calculates a single calibration count based on the delay chain self-loop oscillation clock signal and the external reference clock signal.
[0014] Optionally, the novel high-precision pulse modulation system further includes: a delay tracking module; the delay tracking module is used to monitor in real time whether the delay processing of the delay chain module is offset according to the forced delay code, the tracking enable signal and the external reference clock signal.
[0015] Optionally, the delay tracking module includes: a fourth logic gate, a buffer, an inverter, a first trigger and a second trigger.
[0016] The first input end of the fourth logic gate is connected to the tracking enable signal, the second input end of the fourth logic gate is connected to the external reference clock signal, the output end of the fourth logic gate is connected to the second input end of the delay chain module, the first input end of the delay chain module is connected to the forced delay code, and the output end of the delay chain module is respectively connected to the input end of the buffer and the first input end of the first trigger; the output end of the buffer is connected to the input end of the inverter, and the output end of the inverter is connected to the first input end of the second trigger; the second input end of the first trigger and the second input end of the second trigger are respectively connected to the external reference clock signal; the output end of the first trigger outputs a first delay state signal, when the first delay state signal is at a high level, it reflects that the delay processing of the delay chain module becomes faster; the output end of the second trigger outputs a second delay state signal, when the second delay state signal is at a high level, it reflects that the delay processing of the delay chain module becomes slower.
[0017] Optionally, when the delay processing of the delay chain module becomes slower or faster, the calibration module is restarted to calculate a new delay step number.
[0018] Optionally, the delay block circuit includes: a first two-input NAND gate, a second two-input NAND gate, a third two-input NAND gate, a fourth two-input NAND gate and a fifth two-input NAND gate.
[0019] The first input end of the first two-input NAND gate is connected to a high level, the second input end of the first two-input NAND gate is connected to the output end of the second two-input NAND gate of the previous delay block circuit, and the second input end of the first two-input NAND gate of the first delay block circuit is connected to the input pulse; the output end of the first two-input NAND gate is respectively connected to the second input end of the second two-input NAND gate and the second input end of the third two-input NAND gate.
[0020] The first input end of the second two-input NAND gate is connected to the inverted signal of the enable state signal of the delay block circuit; the output end of the second two-input NAND gate is connected to the second input end of the first two-input NAND gate of the next delay block circuit, and the output end of the second two-input NAND gate of the last delay block circuit is connected to the second input end of the fourth two-input NAND gate of the last delay block circuit.
[0021] The first input terminal of the third two-input NAND gate is connected to the enable state signal of the delay block circuit; the output terminal of the third two-input NAND gate is connected to the first input terminal of the fifth two-input NAND gate.
[0022] The first input end of the fourth two-input NAND gate is connected to a high level, the second input end of the fourth two-input NAND gate is connected to the output end of the fifth two-input NAND gate of the next delay block circuit, and the second input end of the fourth two-input NAND gate of the last delay block circuit is connected to the output end of the second two-input NAND gate of the last delay block circuit.
[0023] The second input end of the fifth two-input NAND gate is connected to the output end of the fourth two-input NAND gate, the output end of the fifth two-input NAND gate is connected to the second input end of the fourth two-input NAND gate of the previous delay block circuit, and the output end of the fifth two-input NAND gate of the first delay block circuit outputs the delayed output result.
[0024] In a second aspect, the present application provides a method for using the novel high-precision pulse modulation system as described above, comprising the following steps:
[0025] The calibration count is determined according to the external reference clock signal and the delay chain self-loop oscillation clock signal, and the delay step number is determined by using a calibration algorithm according to the calibration counts of different channels of the delay chain module.
[0026] The delay code is calculated based on the delay step number and the decimal delay count of the output result of the register group module.
[0027] A delay code decoding result is generated according to the delay code; the delay code decoding result is an enabling state signal of each delay block circuit.
[0028] According to the decoding result of the delay code, the corresponding delay block circuit is enabled to perform delay processing on the input pulse to obtain a delayed output result.
[0029] Modulation output is performed according to the input pulse and the delayed output result.
[0030] Optionally, a calibration count is determined according to an external reference clock signal and a delay chain self-loop oscillation clock signal, and a calibration algorithm is used to determine the number of delay steps according to the calibration counts of different channels of the delay chain module, specifically including the following steps:
[0031] Configure the forced delay code and turn on the forced delay code write enable, oscillation enable, and calibration enable in sequence.
[0032] The calibration counts of different channels of the delay chain module are determined according to the external reference clock signal and the delay chain self-loop oscillation clock signal.
[0033] Sequentially turn off the forced delay code write enable, oscillation enable, and calibration enable.
[0034] Change the forced delay code, and turn on the forced delay code write enable, oscillation enable, and calibration enable in sequence.
[0035] The calibration counts of different channels of the delay chain module after the forced delay code is changed are determined according to the external reference clock signal and the delay chain self-loop oscillation clock signal.
[0036] Sequentially turn off the forced delay code write enable, oscillation enable, and calibration enable.
[0037] Delay step numbers of different channels of the delay chain module are determined according to calibration counts of different channels of the delay chain module and calibration counts of different channels of the delay chain module after the forced delay code is changed.
[0038] The number of delay steps of the delay chain module is determined according to the number of delay steps of different channels of the delay chain module.
[0039] Optionally, the delay code is calculated according to the following formula:
[0040] code_in=(decimal_delay*hrmstep+0.5)*256.
[0041] Where code_in is the delay code, decimal_delay is the decimal delay count, and hrmstep is the delay step number of the delay chain module.
[0042] Optionally, the method of use further comprises the following steps:
[0043] Whether the delay processing of the delay chain module is offset is monitored in real time according to the forced delay code, the tracking enable signal and the external reference clock signal.
[0044] When the delay processing of the delay chain module is offset, the calibration module is restarted to calculate a new delay step number.
[0045] According to the specific embodiments provided in this application, this application discloses the following technical effects:
[0046] The present application provides a novel high-precision pulse modulation system and a method for using the same. The high-precision pulse modulation system includes: a calibration module, a high-precision control module, a register group module, a delay chain decoding module, a delay chain module and a modulation output module; the calibration module determines the calibration count according to an external reference clock signal and a delay chain self-loop oscillation clock signal, and uses a calibration algorithm to determine the delay step number according to the calibration counts of different channels of the delay chain module; the high-precision control module calculates the delay code according to the delay step number and the decimal delay count of the output result of the register group module; the delay code decoding result is generated according to the delay code by the delay chain decoding module, and the corresponding delay block circuit is enabled accordingly to delay the input pulse to obtain a delayed output result; finally, the input pulse and the delayed output result are modulated and output. The above scheme of the present application improves the pulse accuracy without changing the PWM frequency, improves the quality and reliability of the electric energy, and can achieve high-precision edge control of key parameters such as duty cycle, dead zone, period and phase. This high-precision control capability enables the novel HRPMW system of the present application to perform well in various application scenarios, especially in occasions where waveform parameters need to be precisely controlled, such as communications, radar, power electronics and other fields.
[0047] In addition, in the slave scheme, a delay chain real-time tracking function is designed for the chip to continue running in different environments, and its internal delay parameters will change with factors such as temperature, voltage, and humidity. This function can automatically detect and calibrate the delay parameters of the delay chain during chip operation and ensure its real-time accuracy. This mechanism can effectively eliminate the delay deviation caused by external environmental factors and ensure the long-term stable generation of ideal high-precision pulses. These functions further improve its performance stability and reliability. BRIEF DESCRIPTION OF THE DRAWINGS
[0048] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.
[0049] Figure 1 A circuit structure diagram of a novel high-precision pulse modulation system provided in one embodiment of the present application.
[0050] Figure 2 A circuit structure diagram of a calibration module in a novel high-precision pulse modulation system provided in one embodiment of the present application.
[0051] Figure 3 A circuit structure diagram of a delay block circuit in a novel high-precision pulse modulation system provided in one embodiment of the present application.
[0052] Figure 4 A circuit structure diagram of a delay tracking module in a novel high-precision pulse modulation system provided in one embodiment of the present application.
[0053] Figure 5 A schematic diagram of waveforms of various signals of a delay tracking module in a novel high-precision pulse modulation system provided in one embodiment of the present application.
[0054] Figure 6 A circuit structure diagram of a high-precision control module in a novel high-precision pulse modulation system provided in one embodiment of the present application.
[0055] Figure 7 A circuit structure diagram of a delay code decoding module in a novel high-precision pulse modulation system provided in one embodiment of the present application.
[0056] Figure 8 A flowchart of a method for using a novel high-precision pulse modulation system provided in another embodiment of the present application. DETAILED DESCRIPTION
[0057] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.
[0058] In order to make the above-mentioned objects, features and advantages of the present application more obvious and easy to understand, the present application is further described in detail below with reference to the accompanying drawings and specific implementation methods.
[0059] In an exemplary embodiment, Figure 1 As shown, a novel high-precision pulse modulation system is provided, including: a calibration module, a high-precision control module, a register group module, a delay chain decoding module, a delay chain module and a modulation output module; the delay chain module includes a plurality of delay block circuits; the register group module includes a high-precision phase register, a high-precision period register, a high-precision duty cycle register and a high-precision dead zone register.
[0060] The calibration module is used to determine the calibration count according to the external reference clock signal and the delay chain self-loop oscillation clock signal, and to determine the delay step number by using the calibration algorithm according to the calibration counts of different channels of the delay chain module; the high-precision control module is used to calculate the delay code according to the delay step number and the decimal delay count of the output result of the register group module; the delay chain decoding module is used to generate a delay code decoding result according to the delay code; the delay code decoding result is an enabling state signal of each delay block circuit; the delay chain module is used to enable the corresponding delay block circuit according to the delay code decoding result, delay the input pulse, and obtain a delayed output result; the pulse modulation output module is used to modulate and output according to the input pulse and the delayed output result.
[0061] Since there are process and production deviations in the chip manufacturing process, the delays between different chips will be different. In order to ensure the accuracy of the delay, a calibration circuit is designed to calibrate the delay. Figure 2 As shown in the circuit structure diagram, the calibration module includes: a first logic gate, a second logic gate, a third logic gate and a calibration block.
[0062] The first input end of the first logic gate is connected to the oscillation enable signal, the second input end of the first logic gate is connected to the self-loop oscillation output end of the delay chain module, the output end of the first logic gate outputs the delay chain self-loop oscillation clock signal, and the first input end of the delay chain module is connected to the output end of the first logic gate.
[0063] The first input end of the second logic gate is connected to the forced delay code, the second input end of the second logic gate is connected to the forced delay code write enable signal, the output end of the second logic gate outputs the forced delay signal, and the second input end of the delay chain module is connected to the output end of the second logic gate.
[0064] A first input end of the third logic gate is connected to an output end of the first logic gate, a second input end of the third logic gate is connected to a calibration enable signal, and an output end of the third logic gate outputs a delay chain self-loop oscillation clock signal.
[0065] The first input end of the calibration block is connected to the output end of the third logic gate, the first input end of the calibration block is connected to the external reference clock signal, and the output end of the calibration block calculates a single calibration count based on the delay chain self-loop oscillation clock signal and the external reference clock signal.
[0066] The working principle of the calibration circuit is as follows: configure code_force (force delay code writing. Different from the normal code_in input, code_force can be written directly from the register. The next step is to turn on the oscillation enable osc_en to make the delay chain self-loop oscillate (osc_loop shadow), turn on the calibration enable cali_en, and use the oscillating osc_clk to count the external reference clock (ref_clk). The osc_clk frequencies oscillated by two different code_forces are different, and the count values of ref_clk will also be different. The two count values are calculated according to the calibration algorithm to obtain the real delay.
[0067] In a specific embodiment, Figure 3 As shown in the circuit structure diagram, the delay block circuit includes: a first two-input NAND gate, a second two-input NAND gate, a third two-input NAND gate, a fourth two-input NAND gate and a fifth two-input NAND gate.
[0068] The first input end of the first two-input NAND gate is connected to a high level, the second input end of the first two-input NAND gate is connected to the output end of the second two-input NAND gate of the previous delay block circuit, and the second input end of the first two-input NAND gate of the first delay block circuit is connected to the input pulse; the output end of the first two-input NAND gate is respectively connected to the second input end of the second two-input NAND gate and the second input end of the third two-input NAND gate.
[0069] The first input end of the second two-input NAND gate is connected to the inverted signal of the enable state signal of the delay block circuit; the output end of the second two-input NAND gate is connected to the second input end of the first two-input NAND gate of the next delay block circuit, and the output end of the second two-input NAND gate of the last delay block circuit is connected to the second input end of the fourth two-input NAND gate of the last delay block circuit.
[0070] A first input terminal of the third two-input NAND gate is connected to the enable state signal of the delay block circuit; an output terminal of the third two-input NAND gate is connected to a first input terminal of the fifth two-input NAND gate.
[0071] The first input terminal of the fourth two-input NAND gate is connected to a high level, the second input terminal of the fourth two-input NAND gate is connected to the output terminal of the fifth two-input NAND gate of the next delay block circuit, and the second input terminal of the fourth two-input NAND gate of the last delay block circuit is connected to the output terminal of the second two-input NAND gate of the last delay block circuit.
[0072] The second input end of the fifth two-input NAND gate is connected to the output end of the fourth two-input NAND gate, the output end of the fifth two-input NAND gate is connected to the second input end of the fourth two-input NAND gate of the previous delay block circuit, and the output end of the fifth two-input NAND gate of the first delay block circuit outputs the delayed output result.
[0073] Since the chip will also be affected by environmental factors such as voltage and temperature during actual use, in order to ensure the real-time accuracy of the delay, in some improved embodiments, the new high-precision pulse modulation system also includes: a delay tracking module; the delay tracking module is used to monitor in real time whether the delay processing of the delay chain module is offset based on the forced delay code, the tracking enable signal and the external reference clock signal.
[0074] Specifically, if Figure 4 As shown in the circuit structure diagram, the delay tracking module includes: a fourth logic gate, a buffer, an inverter, a first trigger and a second trigger.
[0075] The first input end of the fourth logic gate is connected to the tracking enable signal, the second input end of the fourth logic gate is connected to the external reference clock signal, the output end of the fourth logic gate is connected to the second input end of the delay chain module, the first input end of the delay chain module is connected to the forced delay code, and the output end of the delay chain module is respectively connected to the input end of the buffer and the first input end of the first trigger; the output end of the buffer is connected to the input end of the inverter, and the output end of the inverter is connected to the first input end of the second trigger; the second input end of the first trigger and the second input end of the second trigger are respectively connected to the external reference clock signal; the output end of the first trigger outputs a first delay state signal, when the first delay state signal is at a high level, it reflects that the delay processing of the delay chain module becomes faster; the output end of the second trigger outputs a second delay state signal, when the second delay state signal is at a high level, it reflects that the delay processing of the delay chain module becomes slower.
[0076] When the delay processing of the delay chain module becomes slower or faster, that is, when the delay processing of the delay chain module shifts, the calibration module is restarted to calculate a new delay step number.
[0077] In specific applications, the following process is used to determine whether the delay processing of the delay chain module is offset:
[0078] Configure code_force (forced delay code) and turn on track_en to make the reference clock (ref_clk) input delay less than half the reference clock (ref_clk) cycle output. The delayed output is d0, d1 is the output of the d0 signal after the buffer, and d2 is the output of the d1 signal after the inverter. The waveform is as follows Figure 5 as shown
[0079] Observe the change of the output STA[0] of the observation trigger DFF1. Theoretically, at this time, the trigger DFF1 samples d0 ( Figure 5 the shaded area) should be at a low level. If the chip delay increases, the sampled d0 in the shaded area will be at a high level, and the increase of STA[0] indicates that the delay chain becomes slower.
[0080] Observe the change of the output STA[1] of the observation trigger DFF2. Theoretically, at this time, DFF2 samples d2 ( Figure 5 the shaded area) should be at a low level. If the chip delay decreases, the sampled d2 in the shaded area will be at a high level, and the increase of STA[1] indicates that the delay chain becomes faster.
[0081] That is, if a high level is sampled at any output terminal of the trigger DFF1 / DFF2, it indicates that the delay has shifted. When the delay shift is detected, the calibration module can be restarted to recalculate hrmstep.
[0082] In addition, as Figure 6 shown, the delay of hrpwm is obtained by accumulating the results of the high-precision phase register (PHSHR), high-precision period register (PRDHR), high-precision duty cycle register (CMPXHR), and high-precision dead-time register (DBHR). If the accumulated result is greater than one system clock, the integer part of the accumulated delay (integerdelay) is counted by the PWM (pwm_cnt) counter, and the fractional part of the delay (decimal delay) is implemented by the delay chain module. The fractional delay is finally converted into the delay code code_in according to the internal algorithm ((decimal delay * hrmstep + 0.5) * 256). The circuit structure diagram of the delay code decoding module is as Figure 7 shown, the decoding circuit S[127:0] = 1 << N, where N is code_in or code_force, and S[127:0] is the decoding result of the delay chain decoder.
[0083] Based on the same inventive concept, the embodiment of the present application also provides a usage method for the above-mentioned novel high-precision pulse modulation system. In an exemplary embodiment, as Figure 8 shown, the usage method of the above-mentioned novel high-precision pulse modulation system includes the following steps:
[0084] S1. Determine the calibration count according to the external reference clock signal and the delay chain self-loop oscillation clock signal, and determine the delay steps according to the calibration count of different channels of the delay chain module using the calibration algorithm. Step S1 specifically includes the following steps:
[0085] S11. Configure the forced delay code and turn on the forced delay code write enable, oscillation enable and calibration enable in sequence.
[0086] S12. Determine calibration counts of different channels of the delay chain module according to the external reference clock signal and the delay chain self-loop oscillation clock signal.
[0087] S13, turn off the forced delay code write enable, oscillation enable and calibration enable in sequence.
[0088] S14, change the forced delay code, and turn on the forced delay code write enable, oscillation enable and calibration enable in sequence.
[0089] S15. Determine the calibration counts of different channels of the delay chain module after the forced delay code is changed according to the external reference clock signal and the delay chain self-loop oscillation clock signal.
[0090] S16. Turn off the forced delay code write enable, oscillation enable and calibration enable in sequence.
[0091] S17, determining the number of delay steps of different channels of the delay chain module according to the calibration counts of different channels of the delay chain module and the calibration counts of different channels of the delay chain module after the forced delay code is changed.
[0092] S18. Determine the delay step number of the delay chain module according to the delay step numbers of different channels of the delay chain module.
[0093] As an optional implementation, the process of step S1 can be represented by the following steps:
[0094] A. Configure code_force (forced delay code) = code_fc0, and turn on code_force_en (forced delay code write enable).
[0095] B. Turn on the oscillation enable osc_en.
[0096] C. Enable calibration enable cali_en. Steps a to b are configured three times to ensure that the delayline is stable when it oscillates.
[0097] D. The software reads the corresponding registers and records the results of cali_cnt1a and cali_cnt1b.
[0098] E. Turn off enable signals such as code_force_en, osc_en, and cali_en.
[0099] F. Repeat steps a to e, configure new code_force = code_fc1, and obtain new cali_cnt2a, cali_cnt2b.
[0100] G. Calculate the hrmstep of the delay chains of the A and B channels respectively according to the following calibration algorithm:
[0101] hrmstep_cha=1024*(code_f1-code_f0) / (cali_cnt2a-cali_cnt1a).
[0102] hrmstep_chb=1024*(code_f1-code_f0) / (cali_cnt2b-cali_cnt1b).
[0103] H. Write the averaged result hrmstep = (hrmstep_cha + hrmstep_chb + 0.5) / 2. hrmstep actually means that a pwm_cnt counting clock can be subdivided by N delay units, and N is the hrmstep value.
[0104] S2. The delay code is calculated based on the delay step number and the decimal delay count of the output result of the register group module. Specifically in this embodiment, the delay code is calculated according to the following formula:
[0105] code_in=(decimal_delay*hrmstep+0.5)*256.
[0106] Wherein, code_in is the delay code, decimal_delay is the decimal delay count, and hrmstep is the delay step number of the delay chain module. Step S2 is implemented by a high-precision control module.
[0107] S3. Generate a delay code decoding result according to the delay code; the delay code decoding result is an enable state signal of each delay block circuit.
[0108] S4. According to the result of the delay code decoding, the corresponding delay block circuit is enabled to delay the input pulse and obtain the delayed output result. The basic structure of the delay block circuit (DE) is as follows. Each delay block circuit (DE) implements the delay of 5 NAND2 (two-input NAND gates). The internal delay time of each delay block circuit (DE) is closely related to the target process. The average delay of each NAND2 is 25ps, and the delay parameter of a delay block circuit (DE) is 100ps.
[0109] After the input pulse (hrpwm_in) enters the delay chain module, the corresponding number of delay block circuits DE is selected according to the decoding result S[127:0]. The specific selection mechanism is that when the decoding result S[n] is 1, it means that n+1 delay units are selected, and hrpwm_in starts from NAND2_A of DE[0], passes through NAND2_B and goes all the way to NAND2_A of DE[n]. At this time, the hrpwm_in pulse selects the NAND2_C path of DE[n], and then passes through NAND2_E all the way back to NAND2_E of DE[0]. Its output delay_out is the final pulse after delay processing. TIE1 represents a fixed high level, and TIE0 represents a fixed low level.
[0110] S5. Perform modulation output according to the input pulse and the delayed output result.
[0111] Since the chip is also affected by the environment such as voltage and temperature during actual use, in order to ensure the real-time accuracy of the delay, corresponding to the delay tracking module added in the above improved embodiment, the method of use also includes the following steps:
[0112] Whether the delay processing of the delay chain module is offset is monitored in real time according to the forced delay code, the tracking enable signal and the external reference clock signal.
[0113] When the delay processing of the delay chain module is offset, the calibration module is restarted to calculate a new delay step number.
[0114] As an optional implementation manner, the above process of real-time monitoring whether the delay processing of the delay chain module is offset can be represented by the following process:
[0115] Configure code_force (forced delay code) and turn on track_en to make the reference clock (ref_clk) input delay less than half the reference clock (ref_clk) cycle output. The delayed output is d0, d1 is the output of the d0 signal after the buffer, and d2 is the output of the d1 signal after the inverter. The waveform is as follows Figure 5 shown.
[0116] Observe the change of the output STA[0] of the trigger DFF1. Theoretically, at this time, the trigger DFF1 samples d0( Figure 5 The shaded area) should be at a low level. If the chip delay increases, the sample d0 at the shaded area will be at a high level, and pulling STA[0] high will slow down the reaction delay chain.
[0117] Observe the change of the output STA[1] of the trigger DFF2. Theoretically, at this time, DFF2 samples d2( Figure 5The shaded area) should be at a low level. If the chip delay is reduced, the shaded area sample d2 will be at a high level. Pulling STA[1] high will speed up the reaction delay chain.
[0118] That is, if any output terminal of the trigger DFF1 / DFF2 samples a high level, it means that the delay has shifted. When the delay shift is detected, the calibration module can be restarted to recalculate the hrmstep.
[0119] The specific implementation of the present application provides a new type of high-precision pulse modulation system and its use method, which has two significant improvements in this field: on the one hand, the high-precision resolution is increased to 100 picoseconds, which is the highest resolution in the same field. The solution can achieve high-precision edge control of key parameters such as duty cycle, dead zone, period and phase. This high-precision control capability enables HRPMW technology to perform well in various application scenarios, especially in situations where waveform parameters need to be accurately controlled, such as communications, radar, power electronics and other fields. On the other hand, the functions of real-time tracking and self-calibration of the delay chain are added. The chip continues to operate in different environments, and its internal delay parameters will change with factors such as temperature, voltage, and humidity. The tracking and self-calibration technology can automatically detect and calibrate the delay parameters of the delay chain during chip operation and ensure its real-time accuracy. This mechanism can effectively eliminate the delay deviation caused by external environmental factors, and ensure that the ideal high-precision pulse can be generated stably for a long time. These functions further improve its performance stability and reliability.
[0120] The technical features of the above embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0121] This article uses specific examples to illustrate the principles and implementation methods of this application. The description of the above embodiments is only used to help understand the method and core ideas of this application. At the same time, for those skilled in the art, according to the ideas of this application, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as limiting this application.
Claims
1. A new type of high-precision pulse modulation system, characterized in that: include: A calibration module, a high-precision control module, a register group module, a delay chain decoding module, a delay chain module and a modulation output module; the delay chain module includes a plurality of delay block circuits; the register group module includes a high-precision phase register, a high-precision period register, a high-precision duty cycle register and a high-precision dead zone register; The calibration module is used to determine the calibration count according to the external reference clock signal and the delay chain self-loop oscillation clock signal, and determine the delay step number by using the calibration algorithm according to the calibration counts of different channels of the delay chain module; the high-precision control module is used to calculate the delay code according to the delay step number and the decimal delay count of the output result of the register group module; the delay chain decoding module is used to generate a delay code decoding result according to the delay code, and the delay code decoding result is an enable status signal of each delay block circuit; the delay chain module is used to enable the corresponding delay block circuit according to the delay code decoding result, delay the input pulse, and obtain a delayed output result; the pulse modulation output module is used to modulate and output according to the input pulse and the delayed output result.
2. The novel high-precision pulse modulation system according to claim 1 is characterized in that: The calibration module comprises: a first logic gate, a second logic gate, a third logic gate and a calibration block; The first input end of the first logic gate is connected to an oscillation enable signal, the second input end of the first logic gate is connected to a self-loop oscillation output end of the delay chain module, the output end of the first logic gate outputs a delay chain self-loop oscillation clock signal, and the first input end of the delay chain module is connected to the output end of the first logic gate; The first input end of the second logic gate is connected to the forced delay code, the second input end of the second logic gate is connected to the forced delay code write enable signal, the output end of the second logic gate outputs the forced delay signal, and the second input end of the delay chain module is connected to the output end of the second logic gate; The first input end of the third logic gate is connected to the output end of the first logic gate, the second input end of the third logic gate is connected to the calibration enable signal, and the output end of the third logic gate outputs the delay chain self-loop oscillation clock signal; The first input end of the calibration block is connected to the output end of the third logic gate, the first input end of the calibration block is connected to the external reference clock signal, and the output end of the calibration block calculates a single calibration count based on the delay chain self-loop oscillation clock signal and the external reference clock signal.
3. The novel high-precision pulse modulation system according to claim 1 is characterized in that: The novel high-precision pulse modulation system also includes: a delay tracking module; the delay tracking module is used to monitor in real time whether the delay processing of the delay chain module is offset according to the forced delay code, the tracking enable signal and the external reference clock signal.
4. The novel high-precision pulse modulation system according to claim 3 is characterized in that: The delay tracking module includes: a fourth logic gate, a buffer, an inverter, a first trigger and a second trigger; The first input end of the fourth logic gate is connected to the tracking enable signal, the second input end of the fourth logic gate is connected to the external reference clock signal, the output end of the fourth logic gate is connected to the second input end of the delay chain module, the first input end of the delay chain module is connected to the forced delay code, and the output end of the delay chain module is respectively connected to the input end of the buffer and the first input end of the first trigger; the output end of the buffer is connected to the input end of the inverter, and the output end of the inverter is connected to the first input end of the second trigger; the second input end of the first trigger and the second input end of the second trigger are respectively connected to the external reference clock signal; the output end of the first trigger outputs a first delay state signal, when the first delay state signal is at a high level, it reflects that the delay processing of the delay chain module becomes faster; the output end of the second trigger outputs a second delay state signal, when the second delay state signal is at a high level, it reflects that the delay processing of the delay chain module becomes slower.
5. The novel high-precision pulse modulation system according to claim 4 is characterized in that: When the delay processing of the delay chain module becomes slower or faster, the calibration module is restarted to calculate a new delay step number.
6. The novel high-precision pulse modulation system according to claim 1 is characterized in that: The delay block circuit includes: a first two-input NAND gate, a second two-input NAND gate, a third two-input NAND gate, a fourth two-input NAND gate and a fifth two-input NAND gate; The first input end of the first two-input NAND gate is connected to a high level, the second input end of the first two-input NAND gate is connected to the output end of the second two-input NAND gate of the previous delay block circuit, and the second input end of the first two-input NAND gate of the first delay block circuit is connected to the input pulse; the output end of the first two-input NAND gate is connected to the second input end of the second two-input NAND gate and the second input end of the third two-input NAND gate respectively; The first input end of the second two-input NAND gate is connected to the inverted signal of the enable state signal of the delay block circuit; the output end of the second two-input NAND gate is connected to the second input end of the first two-input NAND gate of the next delay block circuit, and the output end of the second two-input NAND gate of the last delay block circuit is connected to the second input end of the fourth two-input NAND gate of the last delay block circuit; The first input terminal of the third two-input NAND gate is connected to the enable state signal of the delay block circuit; the output terminal of the third two-input NAND gate is connected to the first input terminal of the fifth two-input NAND gate; The first input end of the fourth two-input NAND gate is connected to a high level, the second input end of the fourth two-input NAND gate is connected to the output end of the fifth two-input NAND gate of the next delay block circuit, and the second input end of the fourth two-input NAND gate of the last delay block circuit is connected to the output end of the second two-input NAND gate of the last delay block circuit; The second input end of the fifth two-input NAND gate is connected to the output end of the fourth two-input NAND gate, the output end of the fifth two-input NAND gate is connected to the second input end of the fourth two-input NAND gate of the previous delay block circuit, and the output end of the fifth two-input NAND gate of the first delay block circuit outputs the delayed output result.
7. A method for using the novel high-precision pulse modulation system according to any one of claims 1 to 6, characterized in that: include: Determine a calibration count according to an external reference clock signal and a delay chain self-loop oscillation clock signal, and determine a delay step number using a calibration algorithm according to the calibration counts of different channels of the delay chain module; The delay code is calculated based on the delay step number and the decimal delay count of the output result of the register group module; Generate a delay code decoding result according to the delay code; the delay code decoding result is an enable state signal of each delay block circuit; According to the decoding result of the delay code, the corresponding delay block circuit is enabled to delay the input pulse to obtain a delayed output result; Modulation output is performed according to the input pulse and the delayed output result.
8. The method for using the novel high-precision pulse modulation system according to claim 7, characterized in that: The calibration count is determined according to the external reference clock signal and the delay chain self-loop oscillation clock signal, and the number of delay steps is determined by using a calibration algorithm according to the calibration counts of different channels of the delay chain module, specifically including: Configure the forced delay code and enable forced delay code write enable, oscillation enable, and calibration enable in sequence; Determine calibration counts of different channels of the delay chain module according to an external reference clock signal and a delay chain self-loop oscillation clock signal; Turn off the forced delay code write enable, oscillation enable and calibration enable in sequence; Change the forced delay code, and turn on the forced delay code write enable, oscillation enable, and calibration enable in sequence; Determine calibration counts of different channels of the delay chain module after the forced delay code is changed according to the external reference clock signal and the delay chain self-loop oscillation clock signal; Turn off the forced delay code write enable, oscillation enable and calibration enable in sequence; Determine the number of delay steps for different channels of the delay chain module based on the calibration counts of different channels of the delay chain module and the calibration counts of different channels of the delay chain module after the forced delay code is changed The number of delay steps of the delay chain module is determined according to the number of delay steps of different channels of the delay chain module.
9. The method for using the novel high-precision pulse modulation system according to claim 7, characterized in that: The delay code is calculated according to the following formula: code_in=(decimal_delay*hrmstep+0.5)*256; Where code_in is the delay code, decimal_delay is the decimal delay count, and hrmstep is the delay step number of the delay chain module.
10. The method for using the novel high-precision pulse modulation system according to claim 7, characterized in that: Also includes: Monitoring in real time whether the delay processing of the delay chain module is offset according to the forced delay code, the tracking enable signal and the external reference clock signal; When the delay processing of the delay chain module is offset, the calibration module is restarted to calculate a new delay step number.