Multi-trigger-mode digital-to-analog conversion control device and control method

Abstract

The invention belongs to the field of digital-to-analog conversion controller design, and discloses a multi-trigger-mode digital-to-analog conversion control device and a multi-trigger-mode digital-to-analog conversion control method. The device receives scheduling of a CPU (central processing unit) through a system bus and generates a control signal to control a digital-to-analog converter; comprising an interface conversion unit, a decoding unit, an event selector, a shadow register, an isolation unit, a data continuous generator, a mode selector and a physical register, according to the multi-trigger-mode digital-to-analog conversion control device, a user can conveniently select a matched mode according to an application scene. The digital-to-analog conversion method and the digital-to-analog conversion device support operation ways in the prior art, support various ways of continuously generating digital values for conversion, generating digital values for conversion under special events and the like, expand digital-to-analog conversion modes, improve digital-to-analog conversion efficiency, expand application range and can meet various application scenes.

Description

Technical Field

[0001] The invention belongs to the field of digital-to-analog conversion controller design, and in particular relates to a digital-to-analog conversion control device and a control method with multiple trigger modes. Background Art

[0002] MCUs usually integrate digital-to-analog converters, which can be used to convert digital values ​​into analog signals to characterize changes in light, sound, and pressure. To ensure the efficient operation of the digital-to-analog converter, accurate control of the digital-to-analog converter controller is required. The digital-to-analog converter controller is interconnected with the system bus, and the CPU is used to schedule the operation of the digital-to-analog converter. After receiving the CPU's scheduling, the digital-to-analog converter controller generates a control signal to directly control the digital-to-analog converter to convert digital quantities into analog quantities.

[0003] Existing digital-to-analog conversion controllers usually only support one trigger mode, that is, the CPU generates a digital value for conversion by configuring the register in the digital-to-analog conversion controller. This mode passes through the CPU, the system bus, the register, and finally reaches the port of the digital-to-analog converter. The entire operation path is long and cannot generate digital values ​​for conversion in real time and continuously. Therefore, the existing technology cannot support the scenario of generating digital values ​​for conversion in real time and continuously.

[0004] In addition, once the data arrives at the register, the data will be transferred to the port of the digital-to-analog converter for conversion, and it is not possible to control whether the value actually needs to be converted. Therefore, the prior art cannot support the scenario of converting data after a special event occurs. Summary of the invention

[0005] In order to solve the above technical problems, the present invention provides a digital-to-analog conversion control device and a control method with multiple trigger modes, so as to achieve the purpose of using multiple modes to adapt to different application scenarios.

[0006] To achieve the above object, the technical solution of the present invention is as follows: A multi-trigger mode digital-to-analog conversion control device, the device receives the CPU's scheduling through a system bus and generates a control signal to control the digital-to-analog converter, including an interface conversion unit, a decoding unit, an event selector, a shadow register, an isolation unit, a data continuous generator, a mode selector and a physical register; The CPU is a central processing unit that accesses the digital-to-analog conversion controller via a system bus; The interface conversion unit is connected to the system bus and converts the bus protocol into read and write operations; The decoding unit decodes the read and write operations generated by the interface conversion unit, generates an event selection signal and sends it to the event selector, generates a delay cycle number and sends it to the isolation unit, generates an enable signal, initial data, data step length, increase and decrease mode and time interval and sends them to the data continuous generator, generates a mode selection signal and sends it to the mode selector, receives the actual conversion value of the physical register, and sends it to the interface conversion unit; The event selector: according to the event selection signal sent by the decoding unit, selects one of the N events as a trigger signal, and sends it to the data continuous generator and the isolation unit; The shadow register stores the pending conversion value sent by the decoding unit and outputs the value to the isolation unit and the mode selector; The isolation unit detects the trigger signal sent by the event selector. Once the trigger signal has a rising edge or a falling edge, the trigger signal is valid, the internal counter starts counting, and the channel is opened after the required number of delay cycles is counted. The isolation unit sends the pending conversion value sent by the shadow register to the mode selector; The data continuous generator: after detecting the enable signal sent by the decoding unit and the trigger signal sent by the event selector is valid, it uses the initial data, data step, increase / decrease mode and time interval sent by the decoding unit to convert and generate continuous data sequences with different initial values, different increase / decrease modes, different data increase / decrease steps and different time intervals, and outputs them to the mode selector; The mode selector: according to the mode selection signal sent by the decoding unit, selects the conversion value corresponding to the matching mode and outputs it to the physical register; The physical register: saves the conversion value output by the mode selector in real time, and outputs the saved actual conversion value to the decoding unit and the digital-to-analog converter.

[0007] A multi-trigger mode digital-to-analog conversion control method, using the multi-trigger mode digital-to-analog conversion control device as described above, comprises the following steps: (1) The CPU issues a series of write bus operations to the DAC controller. (2) The interface conversion unit that reaches the digital-to-analog conversion controller via the system bus; (3) The interface conversion unit converts the bus operation into a write operation and sends it to the decoding unit; (4) After the decoding unit processes, it generates a pending conversion value and sends it to the shadow register, and generates a mode selection signal and sends it to the mode selector; (5) The shadow register sends the received pending conversion value to the isolation unit and the mode selector. At this time, the event selector does not receive the event selection signal sent by the decoding unit, so it does not work. The isolation unit does not receive the trigger signal sent by the event selector, so it does not work. (6) The mode selector mode selection signal selects the conversion value corresponding to the matching mode and outputs it to the physical register; (7) The physical register saves the conversion value output by the mode selector in real time and outputs the saved actual conversion value to the decoding unit and the digital-to-analog converter.

[0008] A multi-trigger mode digital-to-analog conversion control method, using the multi-trigger mode digital-to-analog conversion control device as described above, comprises the following steps: (1) The CPU issues a series of write bus operations to the DAC controller. (2) The interface conversion unit that reaches the digital-to-analog conversion controller via the system bus; (3) The interface conversion unit converts the bus operation into a write operation and sends it to the decoding unit; (4) After the decoding unit processes, it generates an event selection signal and sends it to the event selector, generates a pending conversion value and sends it to the shadow register, generates a delay cycle number and sends it to the isolation unit, and generates a mode selection signal and sends it to the mode selector; (5) The shadow register sends the received pending conversion value to the isolation unit and the mode selector; the event selector selects one of the N events as the trigger signal according to the event selection signal, and sends it to the data serial generator and the isolation unit; at this time, the data serial generator does not receive the enable signal sent by the decoding unit, so it does not work; (6) The isolation unit detects the trigger signal sent by the event selector. Once the trigger signal has a rising edge or a falling edge, the trigger signal is valid, the internal counter starts counting, and the channel is opened after the required number of delay cycles is reached. The isolation unit sends the pending conversion value to the mode selector. (7) The mode selector selects the conversion value corresponding to the matching mode according to the mode selection signal and outputs it to the physical register; (8) The physical register saves the conversion value output by the mode selector in real time and outputs the saved actual conversion value to the decoding unit and the digital-to-analog converter.

[0009] A multi-trigger mode digital-to-analog conversion control method, using the multi-trigger mode digital-to-analog conversion control device as described above, comprises the following steps: (1) The CPU issues a series of write bus operations to the DAC controller. (2) The interface conversion unit that reaches the digital-to-analog conversion controller via the system bus; (3) The interface conversion unit converts the bus operation into a write operation and sends it to the decoding unit; (4) After the decoding unit processes, it generates an event selection signal and sends it to the event selector, generates a mode selection signal and sends it to the mode selector, generates an enable signal, initial data, data step size, increase and decrease mode and time interval and sends them to the data continuous generator; (5) The event selector selects one of the N events as a trigger signal based on the event selection signal, and sends it to the data continuous generator and the isolation unit. At this time, the isolation unit does not receive the delay cycle number sent by the decoding unit, so it does not work. (6) After the data continuous generator detects the enable signal sent by the decoding unit and the trigger signal sent by the event selector is valid, it uses the initial data, data step size, increase / decrease mode and time interval sent by the decoding unit to convert and generate continuous data sequences with different initial values, different increase / decrease modes, different data increase / decrease steps and different time intervals, and outputs them to the mode selector; (7) The mode selector selects the conversion value corresponding to the matching mode according to the mode selection signal and outputs it to the physical register; (8) The physical register saves the conversion value output by the mode selector in real time and outputs the saved actual conversion value to the decoding unit and the digital-to-analog converter.

[0010] Through the above technical solution, the multi-trigger mode digital-to-analog conversion control device and control method provided by the present invention have the following beneficial effects: The multi-trigger mode digital-to-analog conversion control device of the present invention can facilitate users to select matching modes according to application scenarios. It supports both the operation methods of the prior art and multiple methods such as continuously generating digital values ​​for conversion and generating digital values ​​for conversion under special events, thereby expanding the digital-to-analog conversion mode, improving the efficiency of digital-to-analog conversion, and expanding the scope of application, and can meet multiple application scenarios. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art are briefly introduced below.

[0012] Figure 1 A schematic diagram of a digital-to-analog conversion control device with multiple trigger modes disclosed in an embodiment of the present invention. DETAILED DESCRIPTION

[0013] The technical solutions in the embodiments of the present invention will be described clearly and completely below in conjunction with the accompanying drawings in the embodiments of the present invention.

[0014] The present invention provides a multi-trigger mode digital-to-analog conversion control device, such as Figure 1As shown, the device receives the CPU's scheduling through the system bus and generates a control signal to control the digital-to-analog converter, including an interface conversion unit, a decoding unit, an event selector, a shadow register, an isolation unit, a data continuity generator, a mode selector and a physical register.

[0015] CPU: Central Processing Unit, accesses the digital-to-analog converter controller through the system bus.

[0016] Interface conversion unit: connected to the system bus and converts the bus protocol into read and write operations.

[0017] Decoding unit: decodes the read and write operations generated by the interface conversion unit, generates an event selection signal and sends it to the event selector, generates a delay cycle number and sends it to the isolation unit, generates an enable signal, initial data, data step size, increase and decrease mode and time interval and sends them to the data continuity generator, generates a mode selection signal and sends it to the mode selector, receives the actual conversion value of the physical register, and sends it to the interface conversion unit.

[0018] Event selector: According to the event selection signal sent by the decoding unit, select one of the N events as the trigger signal and send it to the data continuous generator and isolation unit.

[0019] Shadow register: Saves the pending conversion value sent by the decoding unit and outputs the value to the isolation unit and mode selector.

[0020] Isolation unit: detects the trigger signal sent by the event selector. Once the trigger signal has a rising edge or a falling edge, the trigger signal is valid, the internal counter starts counting, and the channel is opened after the required number of delay cycles is reached. The isolation unit sends the pending conversion value sent by the shadow register to the mode selector.

[0021] Data continuous generator: After detecting the enable signal sent by the decoding unit and the trigger signal sent by the event selector is valid, it uses the initial data, data step, increase and decrease mode and time interval sent by the decoding unit to convert and generate continuous data sequences with different initial values, different increase and decrease methods, different data increase and decrease steps, and different time intervals, and outputs them to the mode selector.

[0022] Mode selector: According to the mode selection signal sent by the decoding unit, the conversion value corresponding to the matching mode is selected and output to the physical register.

[0023] Physical register: Saves the conversion value output by the mode selector in real time, and outputs the saved actual conversion value to the decoding unit and the digital-to-analog converter.

[0024] According to actual conditions, the number of supported events is set to 16, and the system can use 16 different events to trigger the operation of the digital-to-analog converter.

[0025] The basic mode 1 supported by the present invention has the same effect as the prior art, and discretely generates digital values ​​for conversion. The details are as follows:

[0026] A multi-trigger mode digital-to-analog conversion control method, using the multi-trigger mode digital-to-analog conversion control device as above, comprises the following steps: (1) The CPU issues a series of write bus operations to the DAC controller. (2) The interface conversion unit that reaches the digital-to-analog conversion controller via the system bus; (3) The interface conversion unit converts the bus operation into a write operation and sends it to the decoding unit; (4) After the decoding unit processes, it generates a pending conversion value and sends it to the shadow register, and generates a mode selection signal and sends it to the mode selector; (5) The shadow register sends the received pending conversion value to the isolation unit and the mode selector. At this time, the event selector does not receive the event selection signal sent by the decoding unit, so it does not work. The isolation unit does not receive the trigger signal sent by the event selector, so it does not work. (6) The mode selector mode selection signal selects the conversion value corresponding to the matching mode and outputs it to the physical register; (7) The physical register saves the conversion value output by the mode selector in real time and outputs the saved actual conversion value to the decoding unit and the digital-to-analog converter.

[0027] The second mode supported by the present invention is to generate discrete digital values ​​for conversion after the trigger event is effective. The details are as follows:

[0028] A multi-trigger mode digital-to-analog conversion control method, using the multi-trigger mode digital-to-analog conversion control device as above, comprises the following steps: (1) The CPU issues a series of write bus operations to the DAC controller. (2) The interface conversion unit that reaches the digital-to-analog conversion controller via the system bus; (3) The interface conversion unit converts the bus operation into a write operation and sends it to the decoding unit; (4) After the decoding unit processes, it generates an event selection signal and sends it to the event selector, generates a pending conversion value and sends it to the shadow register, generates a delay cycle number and sends it to the isolation unit, and generates a mode selection signal and sends it to the mode selector; (5) The shadow register sends the received pending conversion value to the isolation unit and the mode selector; the event selector selects one of the N events as the trigger signal according to the event selection signal, and sends it to the data serial generator and the isolation unit; at this time, the data serial generator does not receive the enable signal sent by the decoding unit, so it does not work; (6) The isolation unit detects the trigger signal sent by the event selector. Once the trigger signal has a rising edge or a falling edge, the trigger signal is valid, the internal counter starts counting, and the channel is opened after the required number of delay cycles is reached. The isolation unit sends the pending conversion value to the mode selector. (7) The mode selector selects the conversion value corresponding to the matching mode according to the mode selection signal and outputs it to the physical register; (8) The physical register saves the conversion value output by the mode selector in real time and outputs the saved actual conversion value to the decoding unit and the digital-to-analog converter.

[0029] Mode 3 supported by the present invention is to continuously generate digital values ​​for conversion after the trigger event is effective. The details are as follows:

[0030] A multi-trigger mode digital-to-analog conversion control method, using the multi-trigger mode digital-to-analog conversion control device as above, comprises the following steps: (1) The CPU issues a series of write bus operations to the DAC controller. (2) The interface conversion unit that reaches the digital-to-analog conversion controller via the system bus; (3) The interface conversion unit converts the bus operation into a write operation and sends it to the decoding unit; (4) After the decoding unit processes, it generates an event selection signal and sends it to the event selector, generates a mode selection signal and sends it to the mode selector, generates an enable signal, initial data, data step size, increase and decrease mode and time interval and sends them to the data continuous generator; (5) The event selector selects one of the N events as a trigger signal based on the event selection signal, and sends it to the data continuous generator and the isolation unit. At this time, the isolation unit does not receive the delay cycle number sent by the decoding unit, so it does not work. (6) After the data continuous generator detects the enable signal sent by the decoding unit and the trigger signal sent by the event selector is valid, it uses the initial data, data step size, increase / decrease mode and time interval sent by the decoding unit to convert and generate continuous data sequences with different initial values, different increase / decrease modes, different data increase / decrease steps and different time intervals, and outputs them to the mode selector; (7) The mode selector selects the conversion value corresponding to the matching mode according to the mode selection signal and outputs it to the physical register; (8) The physical register saves the conversion value output by the mode selector in real time and outputs the saved actual conversion value to the decoding unit and the digital-to-analog converter.

[0031] In summary, the multi-trigger mode digital-to-analog conversion controller structure of the present invention facilitates users to select a matching mode according to the application scenario, and supports multiple methods such as discrete generation of digital values ​​for conversion, continuous generation of digital values ​​for conversion, and generation of digital values ​​for conversion under special events.

[0032] The above description of the disclosed embodiments enables one skilled in the art to implement or use the present invention. Various modifications to these embodiments will be apparent to one skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but rather to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A multi-trigger mode digital-to-analog conversion control device, the device receives the CPU's scheduling through the system bus and generates a control signal to control the digital-to-analog converter, It is characterized in that It includes an interface conversion unit, a decoding unit, an event selector, a shadow register, an isolation unit, a data continuous generator, a mode selector and a physical register; The CPU is a central processing unit that accesses the digital-to-analog conversion controller via a system bus; The interface conversion unit is connected to the system bus and converts the bus protocol into read and write operations; The decoding unit decodes the read and write operations generated by the interface conversion unit, generates an event selection signal and sends it to the event selector, generates a delay cycle number and sends it to the isolation unit, generates an enable signal, initial data, data step length, increase and decrease mode and time interval and sends them to the data continuous generator, generates a mode selection signal and sends it to the mode selector, receives the actual conversion value of the physical register, and sends it to the interface conversion unit; The event selector: according to the event selection signal sent by the decoding unit, selects one of the N events as a trigger signal, and sends it to the data continuous generator and the isolation unit; The shadow register stores the pending conversion value sent by the decoding unit and outputs the value to the isolation unit and the mode selector; The isolation unit detects the trigger signal sent by the event selector. Once the trigger signal has a rising edge or a falling edge, the trigger signal is valid, the internal counter starts counting, and the channel is opened after the required number of delay cycles is counted. The isolation unit sends the pending conversion value sent by the shadow register to the mode selector; The data continuous generator: after detecting the enable signal sent by the decoding unit and the trigger signal sent by the event selector is valid, it uses the initial data, data step, increase / decrease mode and time interval sent by the decoding unit to convert and generate continuous data sequences with different initial values, different increase / decrease modes, different data increase / decrease steps and different time intervals, and outputs them to the mode selector; The mode selector: according to the mode selection signal sent by the decoding unit, selects the conversion value corresponding to the matching mode and outputs it to the physical register; The physical register: saves the conversion value output by the mode selector in real time, and outputs the saved actual conversion value to the decoding unit and the digital-to-analog converter.

2. A multi-trigger mode digital-to-analog conversion control method, using a multi-trigger mode digital-to-analog conversion control device as claimed in claim 1, It is characterized in that The steps include: (1) The CPU issues a series of write bus operations to the DAC controller. (2) The interface conversion unit that reaches the digital-to-analog conversion controller via the system bus; (3) The interface conversion unit converts the bus operation into a write operation and sends it to the decoding unit; (4) After the decoding unit processes, it generates a pending conversion value and sends it to the shadow register, and generates a mode selection signal and sends it to the mode selector; (5) The shadow register sends the received pending conversion value to the isolation unit and the mode selector. At this time, the event selector does not receive the event selection signal sent by the decoding unit, so it does not work. The isolation unit does not receive the trigger signal sent by the event selector, so it does not work. (6) The mode selector mode selection signal selects the conversion value corresponding to the matching mode and outputs it to the physical register; (7) The physical register saves the conversion value output by the mode selector in real time and outputs the saved actual conversion value to the decoding unit and the digital-to-analog converter.

3. A multi-trigger mode digital-to-analog conversion control method, using a multi-trigger mode digital-to-analog conversion control device as claimed in claim 1, It is characterized in that The steps include: (1) The CPU issues a series of write bus operations to the DAC controller. (2) The interface conversion unit that reaches the digital-to-analog conversion controller via the system bus; (3) The interface conversion unit converts the bus operation into a write operation and sends it to the decoding unit; (4) After the decoding unit processes, it generates an event selection signal and sends it to the event selector, generates a pending conversion value and sends it to the shadow register, generates a delay cycle number and sends it to the isolation unit, and generates a mode selection signal and sends it to the mode selector; (5) The shadow register sends the received pending conversion value to the isolation unit and mode selector; The event selector selects one of the N events as a trigger signal according to the event selection signal, and sends it to the data continuous generator and the isolation unit; at this time, the data continuous generator does not receive the enable signal sent by the decoding unit, so it does not work; (6) The isolation unit detects the trigger signal sent by the event selector. Once the trigger signal has a rising edge or a falling edge, the trigger signal is valid, the internal counter starts counting, and the channel is opened after the required number of delay cycles is reached. The isolation unit sends the pending conversion value to the mode selector. (7) The mode selector selects the conversion value corresponding to the matching mode according to the mode selection signal and outputs it to the physical register; (8) The physical register saves the conversion value output by the mode selector in real time and outputs the saved actual conversion value to the decoding unit and the digital-to-analog converter.

4. A multi-trigger mode digital-to-analog conversion control method, using a multi-trigger mode digital-to-analog conversion control device as claimed in claim 1, It is characterized in that The steps include: (1) The CPU issues a series of write bus operations to the DAC controller. (2) The interface conversion unit that reaches the digital-to-analog conversion controller via the system bus; (3) The interface conversion unit converts the bus operation into a write operation and sends it to the decoding unit; (4) After the decoding unit processes, it generates an event selection signal and sends it to the event selector, generates a mode selection signal and sends it to the mode selector, generates an enable signal, initial data, data step size, increase and decrease mode and time interval and sends them to the data continuous generator; (5) The event selector selects one of the N events as a trigger signal based on the event selection signal, and sends it to the data generator and the isolation unit. At this time, the isolation unit does not receive the delay cycle number sent by the decoding unit, so it does not work. (6) After the data continuous generator detects the enable signal sent by the decoding unit and the trigger signal sent by the event selector is valid, it uses the initial data, data step size, increase / decrease mode and time interval sent by the decoding unit to convert and generate continuous data sequences with different initial values, different increase / decrease modes, different data increase / decrease steps and different time intervals, and outputs them to the mode selector; (7) The mode selector selects the conversion value corresponding to the matching mode according to the mode selection signal and outputs it to the physical register; (8) The physical register saves the conversion value output by the mode selector in real time and outputs the saved actual conversion value to the decoding unit and the digital-to-analog converter.

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