SDL frame flow control device
By combining FPGA and DDR3, the SDL frame traffic control device is designed, which solves the problem of insufficient FPGA storage capacity, and realizes the cache and traffic control of SDL frames, which has the advantages of low delay, strong processing capabilities and flexible configuration.
Patent Information
- Application Number
- CN202411026626.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-07-30
- Publication Date
- 2024-12-13
AI Technical Summary
In the prior art, the storage capacity of the FPGA is insufficient and it is difficult to effectively process the SDL frames transmitted at high speed, resulting in data blockage and packet loss problems, and a lack of an SDL frame flow control scheme based on FPGA and DDR3.
Design an SDL frame flow control device, combining FPGA and DDR3, and realizes the cache and flow control of SDL frames through the front interface module, control module, rear interface module and flow control module, and uses DDR3 to read and write data at high speed to ensure SDL frames storage and transmission.
It realizes the cache and traffic control of SDL frames, with the advantages of low delay, strong processing capabilities and flexible configuration, and meets the needs of high-speed transmission links.
Smart Images
Figure CN119135607A_ABST
Abstract
Description
Technical Field
[0001] The invention relates to the field of communication technology, and in particular to an SDL frame flow control device. Background Art
[0002] Large-capacity, high-speed broadband satellite communication systems have increasingly higher requirements for the transmission rate of digital signals. The Simple Data Link Protocol (SDL) has the advantages of good error detection and correction performance, high network security and reliability, low overhead, and simple implementation, and is more adaptable to the requirements of high-speed transmission links.
[0003] The SDL frame length is variable and supports the transmission of service packets with variable lengths. A large number of SDL frames of variable length and irregular intervals are transmitted to the physical layer through the high-speed interface. The high-speed interface transmission rate is 100M, 1G network port or 10G optical port. The physical layer FPGA (field programmable gate array) storage capacity is only tens of megabytes. Relying solely on FPGA cache can easily cause data congestion and packet loss. DDR3SDRAM is the third generation of double-rate synchronous dynamic random access memory, which has the characteristics of fast transmission speed, large storage capacity, and low power consumption. By using FPGA external DDR3 chip, the problem of insufficient FPGA storage capacity can be solved, and high-speed data reading and writing can be achieved to meet the requirements of SDL frame cache and flow control. However, there is no SDL frame flow control solution based on FPGA and DDR3 in the prior art. Summary of the invention
[0004] In view of this, the present invention proposes an SDL frame flow control device, which combines DDR3 and FPGA to convert the high-speed SDL frame received by FPGA into DDR3 data frame. FPGA controls the DDR3 read and write operation to write or read the SDL frame into DDR3, thereby realizing SDL frame storage and flow control. The device has the advantages of low latency, strong processing capability, flexible configuration, etc.
[0005] In order to achieve the above object, the technical solution adopted by the present invention is:
[0006] An SDL frame flow control device comprises an FPGA and DDR3, wherein the FPGA is used to implement a front interface module, a control module, a rear interface module, and a flow control module; the SDL frame is written into the DDR3 through the front interface module and the control module to implement SDL frame buffering, and then the SDL frame is read out from the DDR3 as needed through the rear interface module and the flow control module to implement SDL frame flow control; wherein:
[0007] (1) The front interface module adapts to the FPGA peripheral high-speed interface, converts the received SDL frame into DDR3 data format, and caches it in RAM; in addition, it generates a front interface data indication signal and sends it to the control module; when the DDR3 write status indication is pulled high, the SDL frame in RAM is read;
[0008] (2) The control module completes the DDR3 control operation, writes the SDL frame into the DDR3 or reads the SDL frame from the DDR3; when the DDR3 is in the write state, the data is written into the DDR3 to complete the SDL frame storage; when the DDR3 is in the read state, the fixed-length data is started to be read from the DDR3;
[0009] (3) The rear interface module is used for DDR3 data format conversion, adapting to the discontinuous DDR3 output, and extracting SDL frames;
[0010] (4) The flow control module stores the data output by the rear interface module into the FIFO queue and generates a flow control indication signal to implement SDL frame flow control.
[0011] Furthermore, the front interface module works as follows:
[0012] (101) Convert the received SDL frame into DDR3 data and write it into the front interface RAM. Each time data is written, the counter is incremented by 1.
[0013] (102) When the counter>5, the front interface data indication is pulled high, and when the counter<5 or the counter=5, the front interface data indication is pulled low;
[0014] (103) When the DDR3 write status indication signal is pulled high, the front interface RAM starts to be read, and the counter is reduced by 1 each time data is read.
[0015] Furthermore, the control module maintains a state machine having four states: idle state, write state, read state, and wait state, and jumps to the idle state when powered on or when a wait state is completed;
[0016] In the idle state, it jumps to the write state if one of the following three conditions is met: first, the front interface data indication is pulled high; second, the front interface data is pulled low and DDR3 has no data; third, the front interface data is pulled low and DDR3 has data, but the flow indication signal is pulled low;
[0017] When a single write operation is not completed, it remains in the write state. After completing a single write operation or maintaining the write state for a certain period of time, it is forced to jump to the wait state.
[0018] When a single read operation is not completed, it remains in the reading state; after a single read operation is completed or the reading state is maintained for a certain period of time, it is forced to jump to the waiting state;
[0019] If the wait state exceeds 10 microseconds, the system will jump to the idle state.
[0020] Furthermore, the working mode of the rear interface module is as follows:
[0021] (301) Convert the format of the intermittent data output by DDR3 and write it into the rear interface RAM;
[0022] (302) every fixed interval, start outputting SDL frames from the rear interface RAM, wherein the SDL frame length is multiplexed in front of the data;
[0023] (303) Extract the SDL frame length from the SDL frame, and read the effective length of the SDL data according to the SDL length.
[0024] Furthermore, the flow control module works as follows:
[0025] (401) storing the SDL frame in the FIFO queue of the flow control module;
[0026] (402) Determine the amount of data in the FIFO queue and generate a flow control pulse. When the amount of data is less than the set amount, the flow control pulse is pulled high. When the amount of data is more than the set amount, the flow control pulse is pulled low to complete the SDL frame flow control.
[0027] The beneficial effects achieved by adopting the above technical solution are:
[0028] 1. The present invention realizes high-speed data reading and writing by combining FPGA with DDR3 chip, meeting the requirements of SDL frame buffering and flow control.
[0029] 2. The present invention has the advantages of low latency, strong processing capability, and flexible configuration. BRIEF DESCRIPTION OF THE DRAWINGS
[0030] Figure 1 It is a schematic diagram of the principle of the SDL frame flow control device in an embodiment of the present invention.
[0031] Figure 2 It is a state control diagram of DDR3 in an embodiment of the present invention. DETAILED DESCRIPTION
[0032] The present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.
[0033] An SDL frame flow control device combines the advantages of FPGA and DDR3 chips, uses a small amount of FPGA on-chip cache to achieve high-speed SDL frame cache and flow control. Through the front interface module and control module, the SDL frame is written into DDR3 to achieve SDL frame cache; then through the back interface module and flow control module, the SDL frame is read out from DDR3 on demand to achieve SDL frame flow control. Figure 1 As shown, the FPGA of the device is used to implement the following modules:
[0034] (1) The front interface module adapts to the FPGA peripheral high-speed interface, converts the received SDL frame into DDR3 data format, and caches it in RAM; at the same time, it generates a front interface data indication signal and sends it to the DDR3 control module; when the DDR3 write status indication is pulled high, the SDL frame in the RAM is read;
[0035] (2) The control module completes the DDR3 control operation to write the SDL frame into the DDR3 or read the SDL frame from the DDR3. When the DDR3 is in the write state, the data is written into the DDR3 to complete the SDL frame storage; when the DDR3 is in the read state, the fixed-length data is read from the DDR3;
[0036] (3) The rear interface module completes DDR3 data format conversion, adapts to the discontinuous DDR3 output, and extracts SDL frames;
[0037] (4) The flow control module stores the output data of the rear interface module into the FIFO and generates a flow control indication signal to implement SDL frame flow control.
[0038] The specific working mode of the front interface module is as follows:
[0039] (101) Convert the received SDL frame into DDR3 data format; write it into the front interface RAM, and increment the counter by 1 each time data is written;
[0040] (102) When counter>5, the front interface data indication is pulled high, and when counter<5 or counter=5, the front interface data indication is pulled low;
[0041] (103) When the DDR3 write status indication signal is pulled high, the front interface RAM starts to be read, and the counter is incremented by 1 each time data is read.
[0042] like Figure 2 As shown, the control module maintains a state machine with four states: idle state, write state, read state, and wait state. The specific control method is as follows:
[0043] (201) Jump to the idle state when power is turned on or when a waiting state is completed;
[0044] (202) In the idle state, if one of the following conditions is met, the device jumps to the write state: the front interface data indication is pulled high; the front interface data is pulled low and DDR3 has no data; the front interface data is pulled low and DDR3 has data, but the flow indication signal is pulled low; if a single write operation is not completed, the device remains in the write state; after a single write operation is completed or the device remains in the write state for a certain period of time, the device forcibly jumps to the wait state;
[0045] (203) In the idle state, when the current interface data is pulled low and DDR3 has data, and the flow indication signal is pulled high, it jumps to the read state; when a single read operation is not completed, it remains in the read state; after a single read operation is completed or the read state is maintained for a certain period of time, it is forced to jump to the waiting state;
[0046] (204) When the waiting state is maintained for more than 10us, it jumps to the idle state.
[0047] The specific working mode of the rear interface module is as follows:
[0048] (301) Convert the format of the intermittent data output by DDR3 and write it into the rear interface RAM;
[0049] (302) SDL frames are output from the RAM at fixed intervals, and the length of the SDL frame is multiplexed in front of the data;
[0050] (303) Extract the SDL frame length and read the effective length of the SDL data based on the length.
[0051] The specific working mode of the flow control module is:
[0052] (401) storing the SDL frame in the FIFO of the flow control module;
[0053] (402) Determine the amount of data in the FIFO and generate a flow control pulse. When the amount of data is less than a certain amount, the flow control pulse is pulled high. When the amount of data is more than a certain amount, the flow control pulse is pulled low to complete the SDL frame flow control.
[0054] In summary, the present invention can realize SDL frame buffering and flow control, and has the advantages of low delay, strong processing capability, flexible configuration, etc.
Claims
1. An SDL frame flow control device, characterized in that: It includes FPGA and DDR3. FPGA is used to realize the front interface module, control module, back interface module and flow control module. Through the front interface module and control module, SDL frame is written into DDR3 to realize SDL frame buffering. Then, through the back interface module and flow control module, SDL frame is read out from DDR3 as needed to realize SDL frame flow control. Among them: The front interface module adapts to the FPGA peripheral high-speed interface, converts the received SDL frame into DDR3 data format, and caches it; in addition, it generates a front interface data indication signal and sends it to the control module; when the DDR3 write status indication is pulled high, the SDL frame in the cache is read; The control module completes the DDR3 control operation, writes the SDL frame into the DDR3 or reads the SDL frame from the DDR3; when the DDR3 is in the write state, the data is written into the DDR3 to complete the SDL frame storage; when the DDR3 is in the read state, the fixed-length data is started to be read from the DDR3; The rear interface module is used for DDR3 data format conversion, adapting to the discontinuous DDR3 output, and extracting SDL frames; The flow control module stores the data output by the rear interface module into the FIFO queue and generates a flow control indication signal to implement SDL frame flow control.
2. The SDL frame flow control device according to claim 1, characterized in that: The front interface module works as follows: (101) Convert the received SDL frame into DDR3 data format and write it into the front interface RAM. Each time data is written, the counter is incremented by 1. (102) When the counter>5, the front interface data indication is pulled high, and when the counter<5 or the counter=5, the front interface data indication is pulled low; (103) When the DDR3 write status indication signal is pulled high, the front interface RAM starts to be read, and the counter is reduced by 1 each time data is read.
3. The SDL frame flow control device according to claim 1, characterized in that: The control module maintains a state machine with four states: idle state, write state, read state, and wait state, and jumps to the idle state when power is turned on or when a wait state is completed; In the idle state, it jumps to the write state if one of the following three conditions is met: first, the front interface data indication is pulled high; second, the front interface data is pulled low and DDR3 has no data; third, the front interface data is pulled low and DDR3 has data, but the flow indication signal is pulled low; When a single write operation is not completed, it remains in the write state. After completing a single write operation or maintaining the write state for a certain period of time, it is forced to jump to the wait state. When a single read operation is not completed, it remains in the reading state; after a single read operation is completed or the reading state is maintained for a certain period of time, it is forced to jump to the waiting state; If the wait state exceeds 10 microseconds, the system will jump to the idle state.
4. The SDL frame flow control device according to claim 1, characterized in that: The working mode of the rear interface module is as follows: (301) Convert the format of the intermittent data output by DDR3 and write it into the rear interface RAM; (302) every fixed interval, start outputting SDL frames from the rear interface RAM, wherein the SDL frame length is multiplexed in front of the data; (303) Extract the SDL frame length from the SDL frame, and read the effective length of the SDL data according to the SDL length.
5. The SDL frame flow control device according to claim 1, characterized in that: The flow control module works as follows: (401) storing the SDL frame in the FIFO queue of the flow control module; (402) Determine the amount of data in the FIFO queue and generate a flow control pulse. When the amount of data is less than the set amount, the flow control pulse is pulled high. When the amount of data is more than the set amount, the flow control pulse is pulled low to complete the SDL frame flow control.