Semiconductor structure and manufacturing method thereof

Abstract

The invention provides a semiconductor structure and a manufacturing method thereof, relates to the technical field of semiconductors, and aims to solve the technical problem of relatively high resistance of a word line structure. The manufacturing method of the semiconductor structure comprises the following steps: forming a word line groove in a substrate; forming a gate dielectric layer covering the word line groove in a shape follow-up manner; a diffusion barrier layer covering the gate dielectric layer in a shape follow-up mode is formed, and the diffusion barrier layer located in the word line groove comprises a first sub-part and remaining sub-parts except the first sub-part; covering the remaining sub-parts and exposing the first sub-parts, and oxidizing part of the first sub-parts; a metal layer covering the diffusion barrier layer is formed in the word line groove, and in the process of forming the metal layer, the oxidized first sub-part reacts with a precursor used for forming the metal layer to be removed, so that the size of the diffusion barrier layer in the word line groove is reduced, the size of the metal layer of the word line groove is increased, and resistance is reduced. In addition, the oxidized first sub-part does not need to be removed independently, so that the manufacturing of the semiconductor structure is simplified.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a semiconductor structure and a manufacturing method thereof. Background Art

[0002] With the continuous development of science and technology, the application of semiconductor structures is becoming more and more extensive. In the fields of computers, communications, etc., semiconductor structures with different functions are needed. Semiconductor structures include transistors and word line (Word Line, referred to as WL) structures, among which the word line structure is often used for the gate of the transistor. The word line structure usually includes a metal layer and a barrier layer covering the side and bottom of the metal layer. The barrier layer can prevent the ions of the metal layer from diffusing outward. However, semiconductor structures often have the problem of large resistance of the word line structure. Summary of the invention

[0003] In view of the above problems, the embodiments of the present disclosure provide a semiconductor structure and a method for manufacturing the same, so as to reduce the resistance of the semiconductor structure.

[0004] According to some embodiments, a first aspect of the present disclosure provides a method for manufacturing a semiconductor structure, comprising:

[0005] forming a word line trench in a substrate;

[0006] forming a gate dielectric layer conformally covering the word line trench;

[0007] forming a diffusion barrier layer conformally covering the gate dielectric layer, wherein the diffusion barrier layer located in the word line trench includes a first sub-portion and a remaining sub-portion except the first sub-portion;

[0008] covering the remaining sub-portion and exposing the first sub-portion, and oxidizing a portion of the first sub-portion;

[0009] A metal layer covering the diffusion barrier layer is formed in the word line trench, wherein during the formation of the metal layer, the oxidized first sub-portion reacts with a precursor for forming the metal layer and is removed.

[0010] The method for manufacturing a semiconductor structure provided by the embodiment of the present disclosure has at least the following advantages:

[0011] In the method for manufacturing a semiconductor structure provided by the embodiment of the present disclosure, a gate dielectric layer conformally covering a word line groove is formed, and a diffusion barrier layer conformally covering the gate dielectric layer is formed, a first sub-portion of the diffusion barrier layer is exposed and partially oxidized, and the oxidized first sub-portion reacts with a precursor for forming a metal layer and is removed, so as to thin the first sub-portion, reduce the volume of the diffusion barrier layer in the word line groove, increase the volume of the metal layer in the word line groove, and reduce the resistance. In addition, the oxidized first sub-portion does not need to be removed separately, that is, the first sub-portion is thinned at the same time during the process of forming the metal layer, thereby simplifying the manufacturing steps of the semiconductor structure.

[0012] According to some embodiments, a second aspect of the present disclosure provides a semiconductor structure, comprising:

[0013] a substrate and a wordline trench in the substrate;

[0014] a word line structure located in the word line trench, the word line structure comprising a gate dielectric layer, a diffusion barrier layer, a metal layer and an isolation layer, the gate dielectric layer conformally covers the word line trench, the diffusion barrier layer covers the gate dielectric layer, the metal layer covers the diffusion barrier layer, the isolation layer covers the top surfaces of the diffusion barrier layer and the metal layer and fills the word line trench;

[0015] The diffusion barrier layer includes a first sub-portion and a remaining sub-portion except the first sub-portion, and a thickness of the first sub-portion is smaller than a thickness of the remaining sub-portion.

[0016] The semiconductor structure provided by the embodiments of the present disclosure has at least the following advantages:

[0017] The semiconductor structure provided by the embodiment of the present disclosure includes a substrate and a word line structure arranged in the substrate, the diffusion barrier layer in the word line structure includes a first sub-portion and remaining sub-portions except the first sub-portion, and the thickness of the first sub-portion is less than the thickness of the remaining sub-portions, so as to reduce the volume of the diffusion barrier layer, increase the volume of the metal layer, and reduce the resistance of the word line structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 is a flow chart of a method for manufacturing a semiconductor structure in an embodiment of the present disclosure;

[0019] Figure 2 A schematic diagram of a word line trench formed in one embodiment is disclosed;

[0020] Figure 3 It is a schematic diagram after forming a gate dielectric layer in one embodiment of the present disclosure;

[0021] Figure 4 It is a schematic diagram after forming a diffusion barrier layer in one embodiment of the present disclosure;

[0022] Figure 5 is a schematic diagram of a first structure of a diffusion barrier layer in an embodiment of the present disclosure;

[0023] Figure 6 It is a schematic diagram of a first metal layer formed in the first diffusion barrier layer in one embodiment of the present disclosure;

[0024] Figure 7 It is a schematic diagram of the first metal layer after etching back in the first diffusion barrier layer in one embodiment of the present disclosure;

[0025] Figure 8 A schematic diagram of a first sub-portion of a first diffusion barrier layer after partial oxidation in an embodiment of the present disclosure;

[0026] Fig. 9 It is a schematic diagram of a second metal layer formed in the first diffusion barrier layer in one embodiment of the present disclosure;

[0027] Fig.10 A schematic diagram of a first diffusion barrier layer after an isolation layer is formed in an embodiment of the present disclosure;

[0028] Fig.11 It is a schematic diagram of a first sacrificial layer formed in the first diffusion barrier layer in one embodiment of the present disclosure;

[0029] Fig.12 It is a schematic diagram of the first sacrificial layer after etching back in the first diffusion barrier layer in one embodiment of the present disclosure;

[0030] Fig.13 Another schematic diagram of a first sub-portion of the first diffusion barrier layer after partial oxidation in one embodiment of the present disclosure;

[0031] Fig.14 It is a schematic diagram of a first diffusion barrier layer after removing the first sacrificial layer in an embodiment of the present disclosure;

[0032] Fig.15 It is a schematic diagram of a first diffusion barrier layer after a metal layer is formed in an embodiment of the present disclosure;

[0033] Fig.16 Another schematic diagram of an embodiment of the present disclosure after an isolation layer is formed in the first diffusion barrier layer;

[0034] Fig.17 is a schematic diagram of a second structure of a diffusion barrier layer in an embodiment of the present disclosure;

[0035] Fig.18 It is a schematic diagram of a second diffusion barrier layer after forming a first sacrificial layer in an embodiment of the present disclosure;

[0036] Fig.19It is a schematic diagram of the second diffusion barrier layer after the first sacrificial layer is etched back in one embodiment of the present disclosure;

[0037] Fig. 20 It is a schematic diagram of a second sacrificial layer formed in the second diffusion barrier layer in one embodiment of the present disclosure;

[0038] Fig.21 It is a schematic diagram of the second sacrificial layer after etching back in the second diffusion barrier layer in one embodiment of the present disclosure;

[0039] Fig. 22 It is a schematic diagram of a second diffusion barrier layer after removing the first sacrificial layer in an embodiment of the present disclosure;

[0040] Fig.23 It is a schematic diagram of a first sub-portion of the second diffusion barrier layer after partial oxidation in one embodiment of the present disclosure;

[0041] Fig.24 It is a schematic diagram of a second type of diffusion barrier layer after removing the second sacrificial layer in one embodiment of the present disclosure;

[0042] Fig.25 It is a schematic diagram of a second diffusion barrier layer after a metal layer is formed in an embodiment of the present disclosure;

[0043] Fig.26 Another schematic diagram of an embodiment of the present disclosure after an isolation layer is formed in the second diffusion barrier layer;

[0044] Fig. 27 is a schematic diagram of a third structure of a diffusion barrier layer in an embodiment of the present disclosure;

[0045] Fig.28 It is a schematic diagram of a third diffusion barrier layer after forming a first metal layer in an embodiment of the present disclosure;

[0046] Fig.29 It is a schematic diagram of the third diffusion barrier layer after the first metal layer is etched back in one embodiment of the present disclosure;

[0047] Fig.30 It is a schematic diagram of a third diffusion barrier layer after forming a first sacrificial layer in an embodiment of the present disclosure;

[0048] Fig.31 It is a schematic diagram of the third diffusion barrier layer after the first sacrificial layer is etched back in one embodiment of the present disclosure;

[0049] Fig.32 It is a schematic diagram of a third diffusion barrier layer after forming a second sacrificial layer in an embodiment of the present disclosure;

[0050] Fig.33It is a schematic diagram of the second sacrificial layer after etching back in the third diffusion barrier layer in one embodiment of the present disclosure;

[0051] Fig.34 This is a schematic diagram of a third diffusion barrier layer after removing the first sacrificial layer in an embodiment of the present disclosure;

[0052] Fig.35 A schematic diagram of a first sub-portion of a third diffusion barrier layer after partial oxidation in an embodiment of the present disclosure;

[0053] Fig.36 It is a schematic diagram of a third diffusion barrier layer after removing the second sacrificial layer in an embodiment of the present disclosure;

[0054] Fig.37 It is a schematic diagram of a third diffusion barrier layer after a metal layer is formed in an embodiment of the present disclosure;

[0055] Fig.38 A schematic diagram of a third diffusion barrier layer after an isolation layer is formed in an embodiment of the present disclosure;

[0056] Fig.39 It is a schematic diagram of a third diffusion barrier layer after forming a first sacrificial layer in an embodiment of the present disclosure;

[0057] Fig.40 It is a schematic diagram of the third diffusion barrier layer after the first sacrificial layer is etched back in one embodiment of the present disclosure;

[0058] Fig.41 It is a schematic diagram of a third diffusion barrier layer after forming a second sacrificial layer in an embodiment of the present disclosure;

[0059] Fig.42 It is a schematic diagram of the second sacrificial layer after etching back in the third diffusion barrier layer in one embodiment of the present disclosure;

[0060] Fig.43 It is a schematic diagram of a third sacrificial layer formed in the third diffusion barrier layer in one embodiment of the present disclosure;

[0061] Fig.44 It is a schematic diagram of the third sacrificial layer after etching back in the third diffusion barrier layer in one embodiment of the present disclosure;

[0062] Fig.45 This is a schematic diagram of a third diffusion barrier layer after removing the first sacrificial layer in an embodiment of the present disclosure;

[0063] Fig.46 Another schematic diagram of a third diffusion barrier layer in an embodiment of the present disclosure after partial oxidation of the first sub-portion;

[0064] Fig.47This is a schematic diagram of a third type of diffusion barrier layer after removing the third sacrificial layer in an embodiment of the present disclosure;

[0065] Fig.48 It is a schematic diagram of a third diffusion barrier layer after a metal layer is formed in an embodiment of the present disclosure;

[0066] Fig.49 Another schematic diagram of a third diffusion barrier layer after an isolation layer is formed in an embodiment of the present disclosure;

[0067] Fig.50 is a schematic structural diagram of a semiconductor structure in an embodiment of the present disclosure;

[0068] Fig.51 is another structural schematic diagram of a semiconductor structure in an embodiment of the present disclosure;

[0069] Fig.52 is another structural schematic diagram of a semiconductor structure in an embodiment of the present disclosure;

[0070] Fig.53 A process diagram of forming a gate dielectric layer of a semiconductor structure in an embodiment of the present disclosure;

[0071] Fig.54 A process diagram of forming a metal layer of a semiconductor structure in one embodiment of the present disclosure.

[0072] Description of reference numerals:

[0073] 10-substrate; 11-word line groove; 12-active pillar; 13-second isolation layer; 20-gate dielectric layer; 30-diffusion barrier layer; 31-first sub-section; 32-remaining sub-section; 33-second sub-section; 34-third sub-section; 40-metal layer; 41-first metal layer; 42-second metal layer; 51-first sacrificial layer; 52-second sacrificial layer; 53-third sacrificial layer; 60-first isolation layer. DETAILED DESCRIPTION

[0074] The problem of a large resistance of the word line structure exists in the related art. The inventor has found that the reason is that in order to prevent ions in the metal layer from diffusing to other film layers, the thickness of the diffusion barrier layer is often large. Since the resistance value of the diffusion barrier layer is greater than the resistance value of the metal layer, the thicker diffusion barrier layer makes the resistance of the word line structure larger.

[0075] To this end, the embodiment of the present disclosure provides a method for manufacturing a semiconductor structure, wherein a word line groove is formed in a substrate, and a gate dielectric layer conformally covering the word line groove and a diffusion barrier layer conformally covering the gate dielectric layer are formed, wherein a first sub-portion of the diffusion barrier layer is exposed and partially oxidized, and the oxidized first sub-portion reacts with a precursor for forming a metal layer and is removed, thereby reducing the volume of the diffusion barrier layer in the word line groove, increasing the volume of the metal layer in the word line groove, and reducing the resistance of the semiconductor structure. In addition, the oxidized first sub-portion does not need to be removed separately, that is, the first sub-portion is thinned at the same time during the process of forming the metal layer, thereby simplifying the manufacturing of the semiconductor structure.

[0076] In order to make the above-mentioned purposes, features and advantages of the embodiments of the present disclosure more obvious and understandable, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present disclosure.

[0077] See also Figure 1 The present disclosure provides a method for manufacturing a semiconductor structure, which may include the following steps:

[0078] Step S100: forming a word line trench in a substrate.

[0079] The substrate 10 includes a semiconductor substrate, which may be a silicon substrate, a germanium substrate, a silicon germanium substrate, a silicon on insulator (SOI) substrate, a silicon carbide substrate, or a gallium nitride substrate. Figure 2 , a word line trench 11 is formed in the substrate 10 , and there may be a plurality of word line trenches 11 , which are arranged at intervals.

[0080] In some examples, such as Figure 2 As shown, an active area and a shallow trench isolation structure defining the active area are formed in the semiconductor substrate, and the active area includes a source area, a drain area and a channel area. The word line trench 11 passes through the active area and the shallow trench isolation structure, and the active areas located on both sides of the word line trench 11 are the source area and the drain area respectively, and the active area located at the bottom of the word line trench 11 forms a channel area, and the two ends of the channel area are connected to the source area and the drain area respectively. The word line trench 11 is used to form a buried word line structure so that the semiconductor structure is formed into a recessed channel transistor.

[0081] For other examples, see Fig.53An active column 12 is formed in the semiconductor substrate, and the active column 12 includes a source region, a channel region and a drain region stacked in sequence. A word line groove 11 is formed on the side of the active column 12, and the word line groove 11 exposes the channel region, which is located on at least one side of the channel region or surrounds the channel region. The word line groove 11 is used to form a single-sided word line structure, a double-sided word line structure or a fully surrounding word line structure, so that the semiconductor structure forms a vertical channel transistor. Among them, a second isolation layer 13 is arranged between two adjacent columns of active columns 12 to isolate different word line structures from each other.

[0082] Step S200: forming a gate dielectric layer conformally covering the word line trench.

[0083] See also Figure 2 and Figure 3 , a gate dielectric layer 20 is formed in the word line trench 11, and the gate dielectric layer 20 conformally covers the word line trench 11. The gate dielectric layer 20 covers the inner wall of the word line trench 11, the outer wall of the gate dielectric layer 20 contacts the inner wall of the word line trench 11, and the shape of the gate dielectric layer 20 matches the shape of the inner wall of the word line trench 11. The gate dielectric layer 20 does not fill the word line trench 11, and the gate dielectric layer 20 located in the word line trench 11 is also enclosed in a groove shape.

[0084] The gate dielectric layer 20 may be made of an insulating material, such as silicon oxide. The gate dielectric layer 20 may have a thickness of 2-6 nm and may be formed by a thermal process or by in-situ steam generation (ISSG).

[0085] Step S300: forming a diffusion barrier layer conformally covering the gate dielectric layer, wherein the diffusion barrier layer located in the word line trench includes a first sub-portion and remaining sub-portions except the first sub-portion.

[0086] See also Figure 4 A diffusion barrier layer 30 is formed on the gate dielectric layer 20, and the diffusion barrier layer 30 conformally covers the gate dielectric layer 20. The diffusion barrier layer 30 covers the inner wall of the gate dielectric layer 20, and the shape of the diffusion barrier layer 30 is adapted to the shape of the gate dielectric layer 20. The diffusion barrier layer 30 does not completely fill the word line trench 11 covered with the gate dielectric layer 20, and the diffusion barrier layer 30 located in the word line trench 11 also surrounds the groove shape.

[0087] The material of the diffusion barrier layer 30 may be titanium nitride, and the thickness of the diffusion barrier layer 30 may be 2 nm to 5 nm. The process temperature of the diffusion barrier layer 30 is 400 to 700° C., and the diffusion barrier layer 30 may be formed by reactive plasma spraying, or by plasma enhanced chemical vapor deposition (PECVD), plasma atomic layer deposition (PEALD), or metal organic chemical vapor deposition (MOVCD).

[0088] Among them, see Figure 5 The diffusion barrier layer 30 in the word line trench 11 includes a first sub-portion 31 and a remaining sub-portion 32. The remaining sub-portion 32 is the remaining portion of the diffusion barrier layer 30 in the word line trench 11 except the first sub-portion 31. The first sub-portion 31 and the remaining sub-portion 32 are connected to form a whole.

[0089] Step S400: covering the remaining sub-portions and exposing the first sub-portion, and oxidizing a portion of the first sub-portion.

[0090] A material is deposited on the exposed surface of the remaining sub-portion 32 to cover the remaining sub-portion 32 and expose the first sub-portion 31. A portion of the first sub-portion 31 is oxidized, that is, the exposed surface of the first sub-portion 31 is oxidized, and the oxidation is inward to a certain depth, the oxidation depth is less than the thickness of the first sub-portion 31, and the area of ​​the first sub-portion 31 that contacts the gate dielectric layer 20 is not oxidized. In the example where the material of the diffusion barrier layer 30 includes titanium nitride, the material of the oxidized first sub-portion 31 includes titanium oxynitride.

[0091] Step S500: forming a metal layer covering the diffusion barrier layer in the word line trench, wherein during the process of forming the metal layer, the oxidized first sub-portion reacts with a precursor for forming the metal layer and is removed.

[0092] See also Figures 6 to 10 , a metal layer 40 is formed in the word line groove 11, and the metal layer 40 covers the diffusion barrier layer 30, for example, the metal layer 40 fills the area enclosed by the diffusion barrier layer 30. In the process of forming the metal layer 40, the precursor used to form the metal layer 40 reacts with the oxidized first sub-portion 31, and the oxidized first sub-portion 31 is removed, so that the first sub-portion 31 is thinned, thereby making the volume of the metal layer 40 in the word line groove 11 larger, reducing the resistance of the metal layer 40, and improving the electrical performance of the semiconductor structure. In addition, the oxidized first sub-portion 31 does not need to be removed separately, that is, the first sub-portion 31 is thinned at the same time in the process of forming the metal layer 40, which simplifies the manufacturing steps of the semiconductor structure.

[0093] The material of the metal layer 40 may be tungsten, and the thickness may be 10 to 50 nm. It may be formed by chemical vapor deposition at a process temperature of 200 to 500° C. The material of the oxidized first sub-portion 31 includes titanium oxynitride, and the material of the precursor includes tungsten hexafluoride. Titanium oxynitride reacts with tungsten hexafluoride to generate gaseous titanium tetrafluoride and is removed. By oxidizing part of the first sub-portion 31 and removing the oxidized first sub-portion 31, the volume of the remaining first sub-portion 31 is reduced. The material of the precursor may also include hydrogen, silane, and diborane. Hydrogen, silane, diborane and tungsten hexafluoride react and deposit to form tungsten.

[0094] It is understood that in the example where the semiconductor structure is formed as a recessed channel transistor, the manufacturing process of the semiconductor structure can be referred to in Figures 6 to 10 In the example of a semiconductor structure formed as a vertical channel transistor, the manufacturing process of the semiconductor structure can be referred to Fig.53 and Fig.54 , but not limited thereto. It can be understood that the word line structure in the vertical channel transistor and the word line structure in the recessed channel transistor are both buried word line structures, and therefore, the manufacturing method of one of them (such as the word line structure of the recessed channel transistor) can be referred to to manufacture the other (such as the word line structure in the vertical channel transistor), and no further details will be given here.

[0095] In some examples, after forming a metal layer covering the diffusion barrier layer in the word line trench (step S500), the method further includes:

[0096] Step S600: etching back the diffusion barrier layer and the metal layer, wherein the top surface of the retained diffusion barrier layer is lower than the top surface of the retained metal layer.

[0097] See also Fig.10 , the diffusion barrier layer 30 and the metal layer 40 are etched back, and the part of the diffusion barrier layer 30 and the part of the metal layer 40 far from the bottom of the word line trench 11 are removed, and the part of the diffusion barrier layer 30 and the part of the metal layer 40 near the bottom of the word line trench 11 are retained, and the top surface of the retained diffusion barrier layer 30 is lower than the top surface of the retained metal layer 40. The top surface of the retained diffusion barrier layer 30 is 30 to 120 nm away from the top surface of the substrate 10, and the top surface of the retained metal layer 40 is 30 to 90 nm away from the top surface of the substrate 10.

[0098] Step S700: forming an isolation layer, where the isolation layer covers the retained diffusion barrier layer and the retained metal layer and fills the word line trench.

[0099] A first isolation layer 60 (also referred to as a "first isolation layer" to distinguish it from the second isolation layer 13) is formed on the retained diffusion barrier layer 30 and the retained metal layer 40, that is, the first isolation layer 60 covers the top surface of the retained diffusion barrier layer 30 and the top surface of the retained metal layer 40, and the first isolation layer 60 also fills the word line trench 11, that is, the top surface of the first isolation layer 60 is at least flush with the top surface of the substrate 10. For example, the first isolation layer 60 is formed by deposition, and back etching or planarization.

[0100] Since the top surface of the retained diffusion barrier layer 30 is lower than the top surface of the retained metal layer 40, part of the first isolation layer 60 is located on the diffusion barrier layer 30 and filled between the diffusion barrier layer 30 and the gate dielectric layer 20 to reduce leakage. The material of the first isolation layer 60 can be an insulating material, such as silicon nitride.

[0101] In summary, the manufacturing method in the embodiment of the present disclosure forms a gate dielectric layer 20 that conformally covers the word line trench 11, and forms a diffusion barrier layer 30 that conformally covers the gate dielectric layer 20, the first sub-portion 31 of the diffusion barrier layer 30 is exposed and partially oxidized, and the oxidized first sub-portion 31 reacts with a precursor for forming a metal layer 40 and is removed, so as to thin the first sub-portion 31, reduce the volume of the diffusion barrier layer 30 in the word line trench 11, increase the volume of the metal layer 40 in the word line trench 11, and reduce the resistance of the semiconductor structure. In addition, the oxidized first sub-portion 31 does not need to be removed separately, that is, the first sub-portion 31 is thinned at the same time during the process of forming the metal layer 40, which simplifies the manufacturing of the semiconductor structure.

[0102] See also Figure 5 The first sub-portion 31 is located on the side of the remaining sub-portion 32 away from the bottom of the word line groove 11, that is, the remaining sub-portion 32 is close to the bottom of the word line groove 11, the first sub-portion 31 is close to the opening of the word line groove 11, and the top surface of the first sub-portion 31 can be flush with the top surface of the substrate 10. The thickness of the first sub-portion 31 is equal to the thickness of the remaining sub-portion 32, so as to facilitate the formation of the first sub-portion 31 and the remaining sub-portion 32.

[0103] For some possible examples, see Figure 6 and Figure 7 , covering the remaining sub-portion 32 and exposing the first sub-portion 31 , including: forming a first metal layer 41 covering the diffusion barrier layer 30 and filling the word line trench 11 ; etching back the first metal layer 41 , wherein the retained first metal layer 41 covers the remaining sub-portion 32 .

[0104] like Figure 6As shown, a first metal layer 41 is deposited in the word line trench 11 formed with the gate dielectric layer 20 and the diffusion barrier layer 30, and the first metal layer 41 fills the remaining word line trench 11, and the first metal layer 41 can also cover the surface of the substrate 10. The first metal layer 41 is etched back, and the remaining first metal layer 41 covers the remaining sub-portion 32, so that at least a portion of the first sub-portion 31 is exposed. Figure 7 As shown, the retained first metal layer 41 may fill the bottom of the remaining word line trench 11. Alternatively, the retained first metal layer 41 conformally covers the surface of the remaining sub-portion 32, that is, the shape of the retained first metal layer 41 is adapted to the shape of the remaining sub-portion 32.

[0105] Accordingly, see Figures 8 to 10 , forming a metal layer 40 covering the diffusion barrier layer 30 in the word line trench 11, including: forming a second metal layer 42 covering the first sub-portion 31 and filling the word line trench 11; wherein the metal layer 40 includes the retained first metal layer 41 and the second metal layer 42.

[0106] like Figure 8 and Fig. 9 As shown, a second metal layer 42 is deposited in the word line trench 11 formed with the gate dielectric layer 20, the diffusion barrier layer 30 and the first metal layer 41, and the second metal layer 42 fills the word line trench 11. The second metal layer 42 covers the retained first metal layer 41 and the remaining first sub-portion 31 of the diffusion barrier layer 30. The second metal layer 42 and the retained first metal layer 41 form a metal layer 40. The material of the first metal layer 41 can be the same as that of the second metal layer 42, so that the first metal layer 41 and the second metal layer 42 form a whole, reducing the resistance of the metal layer 40. Fig.10 As shown, the diffusion barrier layer 30 and the metal layer 40 are etched back, and then a first isolation layer 60 is formed on the remaining diffusion barrier layer 30 and the remaining metal layer 40. The first isolation layer 60 fills the word line trench.

[0107] For other possible examples, see Fig.11 and Fig.12 , covering the remaining sub-portion 32 and exposing the first sub-portion 31 , including: forming a first sacrificial layer 51 covering the diffusion barrier layer 30 and filling the full word line trench 11 ; etching back the first sacrificial layer 51 , wherein the retained first sacrificial layer 51 covers the remaining sub-portion 32 .

[0108] like Fig.11 As shown, a first sacrificial layer 51 is deposited in the word line trench 11, the first sacrificial layer 51 covers the diffusion barrier layer 30, and at least fills the word line trench 11, that is, the gate dielectric layer 20, the diffusion barrier layer 30 and the first sacrificial layer 51 fill the word line trench 11. Fig.12As shown, the first sacrificial layer 51 is etched back, and the retained first sacrificial layer 51 covers the remaining sub-portion 32, so that at least a portion of the first sub-portion 31 is exposed. The retained first sacrificial layer 51 can fill the bottom of the remaining word line trench 11, or the retained first sacrificial layer 51 conformally covers the surface of the remaining sub-portion 32, that is, the shape of the retained first metal layer 41 is adapted to the shape of the remaining sub-portion 32.

[0109] Accordingly, see Figures 13 to 15 , forming a metal layer 40 covering the diffusion barrier layer 30 in the word line trench 11 , including: removing the first sacrificial layer 51 ; and forming a metal layer 40 covering the diffusion barrier layer 30 and filling the word line trench 11 .

[0110] like Fig.13 and Fig.14 As shown, after the exposed first sub-portion 31 is partially oxidized, the first sacrificial layer 51 is removed by etching to expose the remaining sub-portion 32. Fig.15 As shown, a metal layer 40 is deposited in the word line trench 11, and the metal layer 40 covers the diffusion barrier layer 30 and fills the word line trench 11. The metal layer 40 is formed in one step, and the manufacturing process is simple. Fig.16 As shown, the diffusion barrier layer 30 and the metal layer 40 are etched back, and then a first isolation layer 60 is formed on the remaining diffusion barrier layer 30 and the remaining metal layer 40 . The first isolation layer 60 fills the word line trench 11 .

[0111] See also Fig.17 In some examples, the remaining sub-portion 32 is located on the side of the first sub-portion 31 away from the bottom of the word line trench 11, that is, the first sub-portion 31 is close to the bottom of the word line trench 11, and the remaining sub-portion 32 is close to the opening of the word line trench 11, and the top surface of the remaining sub-portion 32 can be flush with the top surface of the substrate 10. The thickness of the first sub-portion 31 is equal to the thickness of the remaining sub-portion 32, so as to facilitate the formation of the first sub-portion 31 and the remaining sub-portion 32.

[0112] See also Figures 18 to 22 , covering the remaining sub-portion 32 and exposing the first sub-portion 31, including: forming a first sacrificial layer 51 covering the diffusion barrier layer 30 and filling the word line groove 11; etching back the first sacrificial layer 51, wherein the retained first sacrificial layer 51 covers the first sub-portion 31; forming a second sacrificial layer 52 conformally covering the remaining sub-portion 32 and the first sacrificial layer 51; etching back the second sacrificial layer 52, wherein the second sacrificial layer 52 retained in the word line groove 11 only covers the remaining sub-portion 32; and removing the retained first sacrificial layer 51.

[0113] like Fig.18 As shown, a first sacrificial layer 51 is deposited in the word line trench 11, and the first sacrificial layer 51 covers the diffusion barrier layer 30 and at least fills the word line trench 11. Fig.19As shown, the first sacrificial layer 51 is etched back, and the remaining first sacrificial layer 51 covers the first sub-portion 31, so that the remaining sub-portion 32 is exposed. The remaining first sacrificial layer 51 can fill the bottom of the remaining word line trench 11, or the remaining first sacrificial layer 51 can conformally cover the surface of the first sub-portion 31, that is, the shape of the retained first metal layer 41 is adapted to the shape of the remaining sub-portion 32.

[0114] like Fig. 20 As shown, a second sacrificial layer 52 is deposited on the remaining sub-portion 32 and the first sacrificial layer 51, and the second sacrificial layer 52 conformally covers the remaining sub-portion 32 and the first sacrificial layer 51, that is, the second sacrificial layer 52 does not fill the word line trench 11. Fig.21 As shown, the second sacrificial layer 52 is etched back to remove at least a portion of the second sacrificial layer 52 on the first sacrificial layer 51 to expose the first sacrificial layer 51, and the second sacrificial layer 52 on the remaining sub-portion 32 is retained to cover the remaining sub-portion 32. Fig. 22 As shown, the first sacrificial layer 51 is removed to expose the first sub-portion 31 .

[0115] Accordingly, see Figure 23 to Figure 26 , forming a metal layer 40 covering the diffusion barrier layer 30 in the word line trench 11 , including: removing the retained second sacrificial layer 52 ; and forming a metal layer 40 covering the diffusion barrier layer 30 and filling the word line trench 11 .

[0116] like Fig.23 and Fig.24 As shown, after the exposed first sub-portion 31 is partially oxidized, the retained second sacrificial layer 52 is etched to expose the remaining sub-portion 32, thereby exposing the remaining diffusion barrier layer 30. Fig.25 As shown, a metal layer 40 is deposited in the word line trench 11, and the metal layer 40 covers the diffusion barrier layer 30 and fills the word line trench 11. Fig.26 As shown, the diffusion barrier layer 30 and the metal layer 40 are etched back, and then a first isolation layer 60 is formed on the remaining diffusion barrier layer 30 and the remaining metal layer 40 . The first isolation layer 60 fills the word line trench 11 .

[0117] See also Fig. 27 In some examples, the remaining sub-portion 32 includes a second sub-portion 33 and a third sub-portion 34, and the second sub-portion 33 and the third sub-portion 34 are respectively located on both sides of the first sub-portion 31. The second sub-portion 33 is located on the side of the first sub-portion 31 close to the bottom of the word line groove 11, and the third sub-portion 34 is located on the side of the first sub-portion 31 away from the bottom of the word line groove 11. That is, along the direction away from the bottom of the word line groove 11, the second sub-portion 33, the first sub-portion 31 and the third sub-portion 34 are arranged in sequence.

[0118] For some possible implementations, see Figures 28 to 34, covering the remaining sub-portion 32 and exposing the first sub-portion 31, including: forming a first metal layer 41 covering the diffusion barrier layer 30 and filling the full word line groove 11; etching back the first metal layer 41, wherein the retained first metal layer 41 covers the second sub-portion 33; forming a first sacrificial layer 51 covering the first sub-portion 31 and the third sub-portion 34 and filling the full word line groove 11; etching back the first sacrificial layer 51, wherein the retained first sacrificial layer 51 covers the first sub-portion 31; forming a second sacrificial layer 52 conformally covering the third sub-portion 34 and the first sacrificial layer 51; etching back the second sacrificial layer 52, wherein the second sacrificial layer 52 retained in the word line groove 11 only covers the third sub-portion 34; and removing the retained first sacrificial layer 51.

[0119] like Fig.28 As shown, a first metal layer 41 is deposited in the word line trench 11, and the first metal layer 41 fills the word line trench 11 and covers the diffusion barrier layer 30, that is, the first metal layer 41, the diffusion barrier layer 30 and the gate dielectric layer 20 fill the word line trench 11. Fig.29 As shown, the first metal layer 41 is etched back to remove part of the first metal layer 41 , and the remaining first metal layer 41 covers the second sub-portion 33 , and the first sub-portion 31 and the third sub-portion 34 are exposed, that is, the remaining first metal layer 41 is close to the bottom of the word line trench 11 .

[0120] like Fig.30 As shown, a first sacrificial layer 51 is deposited in the word line trench 11, and the first sacrificial layer 51 fills the word line trench 11. The first sacrificial layer 51 is located on the first metal layer 41 and covers the first sub-portion 31 and the third sub-portion 34, that is, the first sacrificial layer 51, the first metal layer 41, the diffusion barrier layer 30 and the gate dielectric layer 20 fill the word line trench 11. Fig.31 As shown, the first sacrificial layer 51 is etched back to remove a portion of the first sacrificial layer 51, and the retained first sacrificial layer 51 covers the first sub-portion 31, that is, the retained first sacrificial layer 51 covers the surface of the first sub-portion 31, and the third sub-portion 34 is exposed. For example, the retained first sacrificial layer 51 is opposite to the first sub-portion 31 and is filled between the first sub-portions 31.

[0121] like Fig.32 As shown, a second sacrificial layer 52 is formed on the first sacrificial layer 51 and the third sub-portion 34, and the second sacrificial layer 52 conformally covers the surface of the first sacrificial layer 51 and the surface of the third sub-portion 34, that is, the second sacrificial layer 52 does not fill the word line trench 11. Fig.33 As shown, the second sacrificial layer 52 is etched back to remove the second sacrificial layer 52 on the first sacrificial layer 51. The remaining second sacrificial layer 52 only covers the third sub-portion 34, and the first sacrificial layer 51 is exposed. Fig.34As shown, the exposed first sacrificial layer 51 is then used to remove the retained first sacrificial layer 51 , so as to remove the entire first sacrificial layer 51 and expose the first sub-portion 31 .

[0122] Accordingly, see Figure 35 to Figure 37 , forming a metal layer 40 covering the diffusion barrier layer 30 in the word line groove 11, including: removing the retained second sacrificial layer 52; forming a second metal layer 42 covering the first sub-portion 31 and the third sub-portion 34 and filling the word line groove 11; wherein the metal layer 40 includes the retained first metal layer 41 and the second metal layer 42.

[0123] like Fig.35 and Fig.36 As shown, the second sacrificial layer 52 on the third sub-portion 34 is removed, that is, the retained second sacrificial layer 52 is removed to expose the third sub-portion 34. After removing the second sacrificial layer 52, both the first sub-portion 31 and the third sub-portion 34 are exposed. Fig.37 As shown, a second metal layer 42 is formed in the word line trench 11, and the second metal layer 42 fills the word line trench 11. The second metal layer 42 is located on the first metal layer 41 and covers the first sub-portion 31 and the third sub-portion 34. The second metal layer 42, the first metal layer 41, the diffusion barrier layer 30 and the gate dielectric layer 20 fill the word line trench 11. The metal layer 40 includes the retained first metal layer 41 and the second metal layer 42. Fig.38 As shown, the diffusion barrier layer 30 and the metal layer 40 are etched back, and then a first isolation layer 60 is formed on the remaining diffusion barrier layer 30 and the remaining metal layer 40 . The first isolation layer 60 fills the word line trench 11 .

[0124] For other possible implementations, see Figure 39 to Figure 45 , covering the remaining sub-portion 32 and exposing the first sub-portion 31, including: forming a first sacrificial layer 51 covering the diffusion barrier layer 30 and filling the full word line groove 11; etching back the first sacrificial layer 51, wherein the retained first sacrificial layer 51 covers the second sub-portion 33; forming a second sacrificial layer 52 covering the first sub-portion 31 and the third sub-portion 34 and filling the full word line groove 11; etching back the second sacrificial layer 52, wherein the retained second sacrificial layer 52 covers the first sub-portion 31; forming a third sacrificial layer 53 conformally covering the third sub-portion 34 and the second sacrificial layer 52; etching back the third sacrificial layer 53, wherein the third sacrificial layer 53 retained in the word line groove 11 only covers the third sub-portion 34; and removing the retained second sacrificial layer 52.

[0125] like Fig.39 As shown, a first sacrificial layer 51 is deposited in the word line trench 11, and the first sacrificial layer 51 fills the word line trench 11 and covers the diffusion barrier layer 30, that is, the first sacrificial layer 51, the diffusion barrier layer 30 and the gate dielectric layer 20 fill the word line trench 11. Fig.40As shown, the first sacrificial layer 51 is etched back to remove part of the first sacrificial layer 51 , and the remaining first sacrificial layer 51 covers the second sub-portion 33 , and the first sub-portion 31 and the third sub-portion 34 are exposed, that is, the remaining first sacrificial layer 51 is close to the bottom of the word line trench 11 .

[0126] like Fig.41 As shown, a second sacrificial layer 52 is deposited in the word line trench 11, and the second sacrificial layer 52 fills the word line trench 11. The second sacrificial layer 52 is located on the first sacrificial layer 51 and covers the first sub-portion 31 and the third sub-portion 34, that is, the first sacrificial layer 51, the second sacrificial layer 52, the diffusion barrier layer 30 and the gate dielectric layer 20 fill the word line trench 11. Fig.42 As shown, the second sacrificial layer 52 is etched back to remove part of the second sacrificial layer 52, and the remaining second sacrificial layer 52 covers the first sub-portion 31, that is, the remaining second sacrificial layer 52 covers the surface of the first sub-portion 31, and the third sub-portion 34 is exposed. For example, the remaining second sacrificial layer 52 is opposite to the first sub-portion 31 and fills between the first sub-portions 31.

[0127] like Fig.43 As shown, a third sacrificial layer 53 is formed on the second sacrificial layer 52 and the third sub-portion 34, and the third sacrificial layer 53 conformally covers the surface of the second sacrificial layer 52 and the surface of the third sub-portion 34, that is, the third sacrificial layer 53 does not fill the word line trench 11. Fig.44 As shown, the third sacrificial layer 53 is etched back to remove the third sacrificial layer 53 on the second sacrificial layer 52, and the remaining third sacrificial layer 53 only covers the third sub-portion 34, and the second sacrificial layer 52 is exposed. The exposed second sacrificial layer is then used to remove the remaining second sacrificial layer, so as to remove all the second sacrificial layers and expose the first sub-portion.

[0128] Accordingly, see Figure 46 to Figure 49 , forming a metal layer 40 covering the diffusion barrier layer 30 in the word line trench 11 , including: removing the retained third sacrificial layer 53 and the retained first sacrificial layer 51 ; forming a metal layer 40 covering the diffusion barrier layer 30 and filling the word line trench 11 .

[0129] like Fig.46 and Fig.47 As shown, the third sacrificial layer 53 on the third sub-portion 34 and the first sacrificial layer 51 on the second sub-portion 33 are removed, and the first sub-portion 31, the second sub-portion 33 and the third sub-portion 34 are all exposed. At this time, only the gate dielectric layer 20 and the partially thinned diffusion barrier layer 30 are present in the word line trench 11. Fig.48 As shown, a metal layer 40 is formed in the word line trench 11, and the metal layer 40 fills the word line trench 11, and the top surface of the metal layer 40 is flush with the top surface of the substrate 10. Fig.49As shown, the diffusion barrier layer 30 and the metal layer 40 are etched back, and then a first isolation layer 60 is formed on the remaining diffusion barrier layer 30 and the remaining metal layer 40 . The first isolation layer 60 fills the word line trench 11 .

[0130] See also Fig.50 , Fig.51 and Fig.52 The present disclosure also provides a semiconductor structure, which includes a substrate 10 and a word line structure, wherein a word line groove 11 is provided in the substrate 10, and a word line structure is provided in the word line groove 11. The substrate 10 includes a semiconductor substrate, which may be a silicon substrate, a germanium substrate, a silicon germanium substrate, a silicon-on-insulator substrate, a silicon carbide substrate, or a gallium nitride substrate.

[0131] In some examples, the semiconductor substrate includes an active region and a shallow trench isolation structure defining the active region, the active region includes a source region, a drain region, and a channel region. A word line structure passes through the active region and the shallow trench isolation structure, and the word line structure forms a buried word line structure, that is, the word line structure is a word line structure of a recessed channel transistor, so that the semiconductor structure is formed into a recessed channel transistor.

[0132] In other examples, the semiconductor substrate includes an active pillar, the active pillar includes a source region, a channel region and a drain region that are stacked together, the word line structure exposes the channel region, which is located on at least one side of the channel region or surrounds the channel region, and the word line structure is formed as a single-sided word line structure, a double-sided word line structure or a fully surrounding word line structure, that is, the word line structure is a word line structure of a vertical channel transistor, so that the semiconductor structure forms a vertical channel transistor.

[0133] The word line structure includes a gate dielectric layer 20, a diffusion barrier layer 30, a metal layer 40 and a first isolation layer 60, the gate dielectric layer 20 conformally covers the word line groove 11, the diffusion barrier layer 30 covers the gate dielectric layer 20, the metal layer 40 covers the diffusion barrier layer 30, the first isolation layer 60 covers the top surfaces of the diffusion barrier layer 30 and the metal layer 40, and fills the word line groove 11; the diffusion barrier layer 30 includes a first sub-portion 31 and a remaining sub-portion 32 except the first sub-portion 31, and the thickness of the first sub-portion 31 is less than the thickness of the remaining sub-portion 32.

[0134] The gate dielectric layer 20 conformally covers the wordline trench 11, and the shape of the gate dielectric layer 20 matches the shape of the wordline trench 11, that is, the gate dielectric layer 20 is groove-shaped. The material of the gate dielectric layer 20 can be an insulating material, such as silicon oxide, and the thickness of the gate dielectric layer 20 can be 2-6nm.

[0135] The diffusion barrier layer 30 covers one side of the gate dielectric layer 20 close to the bottom of the word line trench 11. The shape of the diffusion barrier layer 30 matches the shape of the gate dielectric layer 20 it covers, that is, the diffusion barrier layer 30 is also groove-shaped. The material of the diffusion barrier layer 30 can be titanium nitride, and the thickness of the diffusion barrier layer 30 can be 2nm to 5nm.

[0136] The diffusion barrier layer 30 includes a first sub-portion 31 and a remaining sub-portion 32 except the first sub-portion 31. The thickness of the first sub-portion 31 is less than that of the remaining sub-portion 32. The first sub-portion 31 is connected to the remaining sub-portion 32 to form a whole. By thinning the first sub-portion 31, the volume of the diffusion barrier layer 30 is reduced, so as to provide more remaining space for the word line groove 11 for the metal layer 40, increase the volume of the metal layer 40, and reduce the resistance of the word line structure.

[0137] In some examples, such as Fig.50 As shown, the first sub-portion 31 is located on the side of the remaining sub-portion 32 away from the bottom of the word line trench 11; or Fig.51 As shown, the remaining sub-portion 32 is located on the side of the first sub-portion 31 away from the bottom of the word line trench 11. When the first sub-portion 31 is located on the side of the remaining sub-portion 32 away from the bottom of the word line trench 11, since the first sub-portion 31 is thicker than the remaining sub-portion 32, the diffusion barrier layer 30 near the bottom of the word line trench 11 is thicker, and the gate-induced drain leakage (GIDL) can also be reduced.

[0138] For other examples, see Fig.52 The remaining sub-portions include a second sub-portion 33 and a third sub-portion 34. The second sub-portion 33 is located on a side of the first sub-portion 31 close to the bottom of the word line trench 11, and the third sub-portion 34 is located on a side of the first sub-portion 31 away from the bottom of the word line trench 11. In this way, the diffusion barrier layer 30 close to the bottom of the word line trench 11 is thicker, and the gate induced drain leakage current can also be reduced. The thickness of the third sub-portion 34 and the second sub-portion 33 can be equal.

[0139] The metal layer 40 covers the diffusion barrier layer 30 and fills the bottom of the word line trench 11. The material of the metal layer 40 can be tungsten, and the thickness of the metal layer 40 can be 10 to 50 nm. In some examples, the metal layer 40 can also extend outside the area enclosed by the diffusion barrier layer 30, that is, the top surface of the metal layer 40 can be higher than the top surface of the diffusion barrier layer 30, and the metal layer 40 is spaced from the gate dielectric layer 20. In this way, on the one hand, the volume of the metal layer 40 can be increased and the resistance of the metal layer 40 can be reduced. On the other hand, a portion of the first isolation layer 60 is filled between the metal layer 40 and the gate dielectric layer 20, which can reduce leakage.

[0140] The first isolation layer 60 is located on the diffusion barrier layer 30 and the metal layer 40 to cover the top surfaces of the diffusion barrier layer 30 and the metal layer 40. The first isolation layer 60 is also located in the region opposite to the gate dielectric layer 20 to fill the word line trench 11. The material of the first isolation layer 60 can be nitride, such as silicon nitride.

[0141] In summary, the semiconductor structure in the embodiment of the present disclosure includes a substrate 10 and a word line structure arranged in the substrate 10, and the diffusion barrier layer 30 in the word line structure includes a first sub-portion 31 and a remaining sub-portion 32 except the first sub-portion 31, and the thickness of the first sub-portion 31 is less than the thickness of the remaining sub-portion 32, so as to reduce the volume of the diffusion barrier layer 30, increase the volume of the metal layer 40 covering the diffusion barrier layer 30, and reduce the resistance of the word line structure.

[0142] In this specification, each embodiment or implementation is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the embodiments can be referenced to each other. The description of reference terms such as "one implementation", "some implementations", "illustrative implementations", "examples", "specific examples", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the implementation or example are included in at least one implementation or example of the present disclosure. In this specification, the schematic representation of the above terms does not necessarily refer to the same implementation or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more implementations or examples in a suitable manner.

[0143] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present disclosure, rather than to limit them. Although the present disclosure has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein by equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present disclosure.

Claims

1. A method for manufacturing a semiconductor structure, characterized in that: include: forming a word line trench in a substrate; forming a gate dielectric layer conformally covering the word line trench; forming a diffusion barrier layer conformally covering the gate dielectric layer, wherein the diffusion barrier layer located in the word line trench includes a first sub-portion and a remaining sub-portion except the first sub-portion; covering the remaining sub-portion and exposing the first sub-portion, and oxidizing a portion of the first sub-portion; A metal layer covering the diffusion barrier layer is formed in the word line trench, wherein during the formation of the metal layer, the oxidized first sub-portion reacts with a precursor for forming the metal layer and is removed.

2. The method according to claim 1, characterized in that: The first sub-portion is located at a side of the remaining sub-portion away from the bottom of the word line trench; Covering the remaining sub-portions and exposing the first sub-portion, comprising: forming a first metal layer covering the diffusion barrier layer and filling the word line trench; Etching back the first metal layer, wherein the retained first metal layer covers the remaining sub-portion; Forming the metal layer covering the diffusion barrier layer in the word line trench, comprising: A second metal layer is formed to cover the first sub-portion and fill the word line trench; wherein the metal layer includes the retained first metal layer and the second metal layer.

3. The method according to claim 1, characterized in that: The first sub-portion is located at a side of the remaining sub-portion away from the bottom of the word line trench; Covering the remaining sub-portions and exposing the first sub-portion, comprising: forming a first sacrificial layer covering the diffusion barrier layer and filling the word line trench; Etching back the first sacrificial layer, wherein the retained first sacrificial layer covers the remaining sub-portion; Forming the metal layer covering the diffusion barrier layer in the word line trench, comprising: removing the first sacrificial layer; The metal layer is formed to cover the diffusion barrier layer and fill the word line trench.

4. The method according to claim 1, characterized in that: The remaining sub-portion is located at a side of the first sub-portion away from the bottom of the word line trench; Covering the remaining sub-portions and exposing the first sub-portion, comprising: forming a first sacrificial layer covering the diffusion barrier layer and filling the word line trench; Etching back the first sacrificial layer, wherein the remaining first sacrificial layer covers the first sub-portion; forming a second sacrificial layer conformally covering the remaining sub-portion and the first sacrificial layer; Etching back the second sacrificial layer, wherein the second sacrificial layer retained in the word line trench only covers the remaining sub-portion; removing the retained first sacrificial layer; Forming the metal layer covering the diffusion barrier layer in the word line trench, comprising: removing the retained second sacrificial layer; The metal layer is formed to cover the diffusion barrier layer and fill the word line trench.

5. The method according to claim 1, characterized in that: The remaining sub-portions include a second sub-portion and a third sub-portion, wherein the second sub-portion is located on a side of the first sub-portion close to the bottom of the word line groove, and the third sub-portion is located on a side of the first sub-portion away from the bottom of the word line groove; Covering the remaining sub-portions and exposing the first sub-portion, comprising: forming a first metal layer covering the diffusion barrier layer and filling the word line trench; Etching back the first metal layer, wherein the remaining first metal layer covers the second sub-portion; forming a first sacrificial layer covering the first sub-portion and the third sub-portion and filling the word line trench; Etching back the first sacrificial layer, wherein the remaining first sacrificial layer covers the first sub-portion; forming a second sacrificial layer conformally covering the third sub-portion and the first sacrificial layer; Etching back the second sacrificial layer, wherein the second sacrificial layer retained in the word line trench only covers the third sub-portion; removing the retained first sacrificial layer; Forming the metal layer covering the diffusion barrier layer in the word line trench, comprising: removing the retained second sacrificial layer; A second metal layer is formed to cover the first sub-portion and the third sub-portion and to fill the word line trench; wherein the metal layer includes the retained first metal layer and the second metal layer.

6. The method according to claim 1, characterized in that: The remaining sub-portions include a second sub-portion and a third sub-portion, wherein the second sub-portion is located on a side of the first sub-portion close to the bottom of the word line groove, and the third sub-portion is located on a side of the first sub-portion away from the bottom of the word line groove; Covering the remaining sub-portions and exposing the first sub-portion, comprising: forming a first sacrificial layer covering the diffusion barrier layer and filling the word line trench; Etching back the first sacrificial layer, wherein the retained first sacrificial layer covers the second sub-portion; forming a second sacrificial layer covering the first sub-portion and the third sub-portion and filling the word line trench; Etching back the second sacrificial layer, wherein the remaining second sacrificial layer covers the first sub-portion; forming a third sacrificial layer conformally covering the third sub-portion and the second sacrificial layer; Etching back the third sacrificial layer, wherein the third sacrificial layer retained in the word line trench only covers the third sub-portion; removing the retained second sacrificial layer; Forming the metal layer covering the diffusion barrier layer in the word line trench, comprising: removing the retained third sacrificial layer and the retained first sacrificial layer; The metal layer is formed to cover the diffusion barrier layer and fill the word line trench.

7. The production method according to any one of claims 1 to 6, characterized in that: After forming the metal layer covering the diffusion barrier layer in the word line trench, the method further comprises: Etching back the diffusion barrier layer and the metal layer, wherein a top surface of the retained diffusion barrier layer is lower than a top surface of the retained metal layer; An isolation layer is formed, wherein the isolation layer covers the remaining diffusion barrier layer and the remaining metal layer and fully fills the word line trench.

8. The production method according to any one of claims 1 to 6, characterized in that: The material of the diffusion barrier layer includes titanium nitride, the material of the oxidized first sub-portion includes titanium oxynitride, the material of the metal layer includes tungsten, and the material of the precursor includes tungsten hexafluoride.

9. A semiconductor structure, characterized in that: include: a substrate and a wordline trench in the substrate; a word line structure located in the word line trench, the word line structure comprising a gate dielectric layer, a diffusion barrier layer, a metal layer and an isolation layer, the gate dielectric layer conformally covers the word line trench, the diffusion barrier layer covers the gate dielectric layer, the metal layer covers the diffusion barrier layer, the isolation layer covers the top surfaces of the diffusion barrier layer and the metal layer and fills the word line trench; The diffusion barrier layer includes a first sub-portion and a remaining sub-portion except the first sub-portion, and a thickness of the first sub-portion is smaller than a thickness of the remaining sub-portion.

10. The semiconductor structure according to claim 9, characterized in that: The first sub-portion is located at a side of the remaining sub-portion away from the bottom of the word line trench; Alternatively, the remaining sub-portion is located at a side of the first sub-portion away from the bottom of the word line trench.

11. The semiconductor structure according to claim 9, characterized in that: The remaining sub-portions include a second sub-portion and a third sub-portion. The second sub-portion is located on a side of the first sub-portion close to the bottom of the word line trench. The third sub-portion is located on a side of the first sub-portion away from the bottom of the word line trench.

12. The semiconductor structure according to any one of claims 9 to 11, characterized in that: The word line structure is used as a word line structure of a recessed channel transistor or a vertical channel transistor.

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