High electron mobility transistor and manufacturing method thereof

Abstract

A method of manufacturing a high electron mobility transistor (1), the method comprising the steps of:-providing a target wafer (10) comprising a target substrate (100); providing a donor wafer (20) comprising an epitaxial donor film (21); -bonding the donor film (21) to the target wafer (10); -separating the donor wafer (20) and the target wafer (10) along the first donor III-N layer (201), thereby forming a top surface layer (221) of 200 nm or less on the target wafer (10); -epitaxially growing an epitaxial III-N semiconductor layer stack (31, 32) on top of the top surface layer (221); forming a gate contact (41) in the gate region (401); and forming a substrate electrical contact (42) in contact with the target substrate (100).

Description

Technical Field

[0001] The present invention relates generally to semiconductor structures and methods of growing the same, among other things. More particularly, the present invention relates to high electron mobility transistors including nitride-based active layers and methods of making the same, wherein the high electron mobility transistors achieve excellent performance for high power and high frequency applications. Background Art

[0002] Semiconductor devices including, for example, gallium nitride (also known as GaN) and / or heterostructures based on group III nitrides (such as, for example, InAlGaN / GaN heterostructures) can carry large currents and support high voltages. This makes them increasingly suitable for power semiconductor devices. Typically, devices manufactured for high power / high frequency applications are based on device structures with high electron mobility and high critical electric fields, and are referred to as, for example, heterojunction field effect transistors (also known as HFETs), high electron mobility transistors (also known as HEMTs), or modulation doped field effect transistors (also known as MODFETs). For example, HEMTs are used in analog circuit applications, such as RF / microwave power amplifiers or power switches. These devices can typically withstand high voltages, such as up to 1000 volts, or operate at high frequencies, such as from 100 kHz to 100 GHz.

[0003] HEMTs comprising GaN are usually fabricated on top of conventional substrates, such as, for example, semi-insulating silicon carbide substrates (also known as SiC) or high-resistivity silicon substrates. For high-power and high-frequency applications, it is indeed essential to maximize the resistivity of the underlying substrate of the device. The growth of GaN HEMTs usually starts with the growth of an AlN nucleation layer on top of the substrate. Such an AlN nucleation layer usually has a high threading dislocation density. In order to obtain better crystal quality when growing the GaN HEMT on top of the AlN nucleation layer (i.e., to obtain a lower threading dislocation density when growing the GaN HEMT on top of the AlN nucleation layer), a GaN buffer layer, for example 1 μm thick, is usually grown on top of the AlN nucleation layer.

[0004] Such GaN HEMTs are susceptible to trapping effects from the surface of the HEMT and the GaN buffer or GaN bulk layer grown on top of the AlN nucleation layer. Traps in the GaN buffer / bulk layer are caused by impurities (such as, for example, carbon or iron) that are intentionally introduced into the GaN buffer / bulk layer to make the GaN buffer / bulk layer more resistive. Adding these intentional impurities enables the GaN HEMT to achieve higher breakdown voltages and lower leakage. In other words, the GaN buffer / bulk layer always has background impurities to increase confinement, thereby introducing trapping effects for the resulting GaN HEMT.

[0005] Furthermore, such GaN buffer layers create thermal impedance between the active GaN HEMT and the heat sink at the bottom of the substrate on which the active GaN HEMT is fabricated, resulting in performance degradation and jeopardizing the reliability of the GaN HEMT. Similarly, when growing GaN HEMTs on top of silicon substrates, in addition to the AlN nucleation layer, a strain management buffer layer must be grown outside the GaN buffer layer. This increases the overall thickness of the layer stack, for example up to 2 μm. These buffer layers constitute a large thermal impedance to the GaN HEMT.

[0006] As the demand for high power and high frequency solutions continues to increase, the telecommunications industry faces the challenge of making such III-nitride based active devices compatible with existing technologies. For example, III-nitride based active devices should enable the continued miniaturization and performance improvement of microelectronic devices. Summary of the invention

[0007] Therefore, the purpose of the embodiments of the present invention is to propose a high electron mobility transistor and a method for manufacturing the same that do not show the inherent disadvantages of the prior art. More specifically, the purpose of the embodiments of the present invention is to propose a high electron mobility transistor and a method for manufacturing the same that have improved performance and reliability at high power and high frequency.

[0008] The scope of protection claimed for the various embodiments of the invention is set by the independent claims.

[0009] The embodiments and features described in this specification that do not fall within the scope of the independent claims, if any, are interpreted as examples to aid in understanding the various embodiments of the present invention.

[0010] There is a need for a high electron mobility transistor that exhibits improved resistivity and reduced power losses and linearity issues. Furthermore, there is a need for a semiconductor structure that is compatible with existing technologies from a manufacturing perspective.

[0011] There is a need for a high electron mobility transistor that can be grown on any substrate and exhibits reduced thermal impedance. There is also a need for a high electron mobility transistor whose certain characteristics and parameters can be controlled or changed by the substrate on which the high electron mobility transistor is grown. Finally, there is a need for a high electron mobility transistor that minimizes or even eliminates trapping effects.

[0012] According to a first exemplary aspect of the present invention, this object is achieved by a method of manufacturing a high electron mobility transistor, the method comprising the following steps:

[0013] - providing a target wafer including a target substrate;

[0014] - providing a donor wafer, wherein providing the donor wafer comprises:

[0015] ○Providing a sacrificial substrate;

[0016] o forming a donor film on top of a sacrificial substrate; wherein the donor film comprises a first donor III-N layer;

[0017] -bonding the donor film to the target wafer;

[0018] - separating the donor wafer and the target wafer by slicing the first donor III-N layer, or separating the donor wafer and the target wafer at an interface between the first donor III-N layer and the sacrificial substrate, thereby forming a top surface layer on the target wafer that at least partially includes the first donor III-N layer bonded to the target wafer, wherein the thickness of the top surface layer is equal to or less than 200 nm;

[0019] - epitaxially growing an epitaxial III-N semiconductor layer stack on top of the top surface layer, wherein the epitaxial III-N semiconductor layer stack comprises:

[0020] ○ First active III-N layer;

[0021] o a second active III-N layer on top of the first active III-N layer;

[0022] a two-dimensional electron gas between the first active III-N layer and the second active III-N layer;

[0023] - forming a gate contact in the gate region in contact with the second active III-N layer; and

[0024] - Forming substrate electrical contacts to the target substrate.

[0025] The method according to the present invention allows the growth of high electron mobility transistors on any substrate (even, for example, a foreign substrate). The method according to the present invention allows the manufacture of high electron mobility transistors by an epitaxial III-N semiconductor layer stack grown on top of a top surface layer, the top surface layer being bonded to (i.e., transferred to by smart cutting) for example, a silicon substrate (such as, for example, a high-resistance silicon substrate), or a SiC substrate (such as, for example, a semi-insulating SiC substrate), or a silicon-on-insulator substrate, or a germanium substrate, or a germanium-on-insulator substrate, or a sapphire substrate, etc. In addition, the method according to the present invention allows the donor film to be bonded to the target wafer without providing a buffer layer on the target wafer between the substrate and the high electron mobility transistor before bonding. In other words, a buffer layer must not be grown on the target substrate before the donor film is bonded to the target substrate. Therefore, compared with prior art high electron mobility transistors grown, for example, on semi-insulating SiC substrates or high-resistance Si substrates, the high electron mobility transistor manufactured using the method according to the present invention is not susceptible to the trapping effect.

[0026] Another advantage of the method according to the present invention is the improved thermal impedance of the manufactured high electron mobility transistor. Since there is no buffer layer between the epitaxial III-N semiconductor layer stack and the target substrate, since the thickness of the transferred first donor III-N layer is kept as thin as possible, and since the thickness of the total layer stack formed on the target wafer is limited, the high electron mobility transistor can achieve low thermal resistivity. In other words, the thermal impedance between the heat sink at the bottom of the substrate and the active device (such as, for example, a high electron mobility transistor manufactured using the method according to the present invention) is small. The thickness of the first donor III-N layer transferred to the target substrate is kept as small as possible, with a maximum thickness of 200nm, preferably less than 100nm, and preferably less than 50nm.

[0027] Another advantage of the method according to the present invention is that the thin layer stack formed on the top of the target wafer enables the substrate to be used as the fourth terminal of the high electron mobility transistor. In this way, the substrate electrical contact in contact with the target substrate can indeed be used to apply a bottom side voltage bias on the target substrate relative to the source contact of the high electron mobility transistor. Due to the small thickness of the layer between the bottom side of the target substrate and the 2DEG, this substrate electrical contact can be used in turn to control or change certain characteristics or parameters of the high electron mobility transistor, such as, for example, the threshold voltage and / or cut-off state leakage of the high electron mobility transistor. The substrate electrical contact can also be used to adjust the charge state of the buffer trap or the main trap present in the target substrate, for example, so as to minimize or eliminate the capture effect of the high electron mobility transistor, and thereby reduce the memory effect of the high electron mobility transistor. After the combination and epitaxial growth of the epitaxial III-N semiconductor layer stack, the substrate electrical contact can be formed on the bottom side of the target substrate and is substantially located below the gate region of the high electron mobility transistor manufactured on the target wafer. Alternatively, after bonding and epitaxial growth of the epitaxial III-N semiconductor layer stack, a substrate electrical contact may be formed on the bottom side of the target substrate and substantially below the high electron mobility transistor fabricated on the target wafer.

[0028] With existing prior art solutions, when manufacturing high electron mobility transistors, for example, on SiC substrates, since SiC substrates in RF applications typically have very high resistance, for example, exhibiting a resistance higher than 1.10 5Ohm.cm resistivity, it is very challenging to have any impact on the performance of the active GaN HEMT device through the substrate. In existing prior art solutions, for example when manufacturing high electron mobility transistors on high resistivity substrates, very high bias voltages (e.g. greater than 100V) are required to have any impact on the active HEMT device due to the thick buffer stack between the active HEMT device and the substrate. In contrast to these prior art solutions, the method according to the present invention does not require very high voltages to be applied through the substrate electrical contacts in order to have an impact on the characteristics of the active device manufactured on top of the target substrate, as the total thickness of the layer stack between the substrate and the 2DEG is kept low.

[0029] In the context of the present invention, forming a donor film on top of a sacrificial substrate includes providing a first donor III-N layer, wherein the first donor III-N layer is epitaxially grown. For example, forming a donor film on top of a sacrificial substrate includes epitaxially growing the first donor III-N layer on top of the sacrificial substrate. In the context of the present invention, the first donor III-N layer comprises GaN. For example, the first donor III-N layer comprises GaN of N polarity epitaxially grown on a donor wafer by MOCVD or by MBE. The donor wafer is turned upside down and the first donor III-N layer is bonded to the top side of a target wafer. The donor wafer and the target wafer are then bonded together. In this way, the first donor III-N layer bonded to the top side of the target wafer is Ga polarity. Therefore, the density of screw dislocations in the epitaxial III-N semiconductor layer stack grown on top of the top surface layer is minimized. Alternatively, the first donor III-N layer comprises, for example, GaN as a layer of Ga polarity provided to the donor wafer after growth on a temporary wafer by MOCVD or by MBE and its upper side is bonded to the donor wafer by a smart cutting technique. The donor wafer and the target wafer are separated from each other by smart cutting of the first donor III-N layer of the donor film. In the context of the present invention, an interface is formed between the first donor III-N layer and the sacrificial substrate, wherein the first donor III-N layer is in contact with the sacrificial substrate. By performing a smart cut at the level of the first donor III-N layer, the separation of the donor wafer from the target wafer is achieved by breaking the first donor III-N layer at the interface between the first donor III-N layer and the sacrificial substrate. In other words, the first donor III-N layer is cut at the interface between the first donor III-N layer and the sacrificial substrate. This separation forms a top surface layer on the target wafer, which top surface layer comprises the first donor III-N layer originally grown on the sacrificial substrate and bonded to the target wafer, wherein the thickness of the top surface layer on the target wafer substantially corresponds to the thickness of the first donor III-N layer grown on the sacrificial substrate. According to the invention, on the target wafer, the thickness of said top surface layer is equal to or less than 200 nm. Alternatively, the separation of the donor wafer from the target wafer is achieved by segmenting the first donor III-N layer by performing a smart cut at the level of the first donor III-N layer, thereby leaving a first remaining portion of the first donor III-N layer separated from the target substrate on the sacrificial substrate (this portion will be referred to as the top surface layer hereinafter), and also leaving a second remaining portion of the first donor III-N layer on the target substrate (this portion will be referred to as the donor surface layer hereinafter), wherein the sum of the thickness of the first remaining portion and the thickness of the second remaining portion substantially corresponds to the total thickness of the first donor III-N layer grown on the sacrificial substrate before the bonding. In other words, the first donor III-N layer is segmented within its thickness.This separation forms a top surface layer on the target wafer, the top surface layer at least partially comprising the first donor III-N layer initially grown on the sacrificial substrate and bonded to the target wafer, wherein the thickness of the top surface layer on the target wafer is equal to or less than 200 nm.

[0030] In the context of the present invention, the donor wafer is, for example, a wafer having a diameter of 125 mm or 150 mm or 200 mm or 300 mm. Alternatively, in the context of the present invention, the donor wafer comprises, for example, a plurality of wafers having a diameter of several mm. 2 or a few cm 2 In the context of the present invention, the target wafer is, for example, a wafer with a diameter of 125 mm or 150 mm or 200 mm or 300 mm, wherein the diameter of the target wafer is larger than the diameter of the donor wafer. For example, one donor wafer can be bonded to one target wafer. Alternatively, for example, multiple donor wafers can be bonded to one target wafer, thereby increasing manufacturing yield.

[0031] In the context of the present invention, the sacrificial substrate is one of the following substrates: a silicon substrate, a silicon-on-insulator substrate, a silicon carbide substrate, a sapphire substrate, a germanium substrate, a germanium-on-insulator substrate, or any other suitable alternatives to the above substrates. Other alternatives to the sacrificial substrate are described below.

[0032] In the context of the present invention, the target substrate is one of the following substrates: a silicon substrate, a silicon-on-insulator substrate, a silicon carbide substrate, a sapphire substrate, a germanium substrate, a germanium-on-insulator substrate, or any other suitable alternative to the above substrates. In this way, the method for manufacturing a high electron mobility transistor according to the present invention is compatible with existing manufacturing technologies developed for complementary metal oxide semiconductor technology and processes. In other words, the manufacture of high electron mobility transistors is compatible with CMOS, because current features and current process steps can be integrated into it without much additional effort. This reduces the complexity and cost associated with manufacturing such transistors. For example, the target substrate is a silicon substrate, such as, for example <111> Si substrates, and combinations thereof, and substrates comprising initial layers, such as layer stacks. For example, when an epitaxial layer must be grown on top of a Si substrate, one can use <111> Si substrate. Alternatively, the target substrate is, for example, a silicon substrate, such as <100> Si substrate. For example, this can achieve GaN / CMOS integration. Alternatively, the target substrate of the high electron mobility transistor includes an independent GaN substrate, an independent AlN substrate.

[0033] In the context of the present invention, when the target substrate is a silicon-on-insulator substrate, the target substrate comprises a base layer comprising bulk silicon. The resistivity of the base layer of the silicon-on-insulator substrate is generally between 3 kOhm.cm and 5 kOhm.cm, preferably higher than 1 kOhm.cm. In this way, the resistivity of the target substrate under the epitaxial III-N semiconductor layer stack can meet the requirements of high power and high frequency applications to the greatest extent.

[0034] In the context of the present invention, silicon-on-insulator (also referred to as SOI) technology corresponds to the manufacture of semiconductor devices on a layered silicon-insulator-silicon substrate. The choice of insulator depends largely on the intended application of the semiconductor device. Several types of silicon-on-insulator substrates can be used in the context of the present invention.

[0035] Due to the isolation from the bulk silicon of the base layer of the silicon-on-insulator substrate, the parasitic capacitance within semiconductor devices fabricated from the III-nitride heterostructure is reduced, thereby improving their power consumption and performance. Semiconductor devices fabricated on silicon-on-insulator also exhibit higher resistance to latch-up and higher performance at equivalent VDD than semiconductor devices integrated on other types of substrates. Semiconductor devices fabricated on SOI have reduced temperature dependence compared to semiconductor devices integrated on other types of substrates. Due to the isolation, semiconductor devices fabricated on SOI exhibit lower leakage current and are therefore more power efficient.

[0036] RF silicon-on-insulator substrates (also known as RF-SOI substrates) enable high RF performance, high linearity RF isolation and power signal, low RF loss, digital processing and power management integration on a silicon film compatible with standard CMOS processes.

[0037] For example, an enhanced signal integrity substrate for RF applications includes a base layer containing high-resistance silicon, a well-rich layer formed on top of the base layer, a buried insulator formed on top of the well-rich layer, and a top layer formed on top of the buried insulator, wherein the top layer includes a single crystal. The resistivity of the base layer is typically more than 3kOhm.cm. The thickness of the top layer is typically between 50nm and 200nm. The addition of the well-rich layer provides excellent RF performance. This substrate is particularly suitable for devices with strict linear specifications. Applications are typically targeted at, for example, advanced LTE and 5G specifications and meet different performance requirements. Compared to high-resistance SOI substrates, enhanced signal integrity substrates exhibit better linearity, lower RF losses, lower crosstalk, improved passive quality factors, smaller die sizes, and higher thermal conductivity. Enhanced signal integrity substrates typically further exhibit harmonic quality factors below -80dBm.

[0038] Another example of RF-SOI includes a base layer including mid-resistance silicon, a well-rich layer formed on top of the base layer, a buried insulator formed on top of the well-rich layer, and a top layer including a thin single crystal. Such a substrate is particularly suitable for, for example, cost-sensitive, highly integrated devices, and is particularly suitable for, for example, Wi-Fi, Internet of Things, and other consumer application specifications.

[0039] Another example of RF-SOI called high-resistance SOI targets, for example, devices with lower linear specifications. Such a substrate includes a base layer containing high-resistance silicon, a buried insulator formed on top of the base layer, and a top layer including a thin single crystal.

[0040] Power silicon-on-insulator substrates meet the automotive and industrial market requirements for integration of intelligent, energy-efficient and high-reliability power IC devices, such as high voltage and analog functions. They provide excellent electrical isolation and are well suited for integrating devices operating at different voltages from a few volts to hundreds of volts, while reducing die area and improving reliability. These substrates are ideal for applications such as CAN / LIN transceivers, switch-mode power supplies, brushless motor drivers, LED drivers, and more. Power SOI includes a base layer containing silicon, a buried insulator formed on top including oxide, and a top layer including silicon. The thickness of the buried insulator is typically between 0.4μm and 1μm, and the thickness of the top layer is typically between 0.1μm and 1.5μm.

[0041] Optoelectronic silicon-on-insulator substrates meet the requirements of integrating optical functions into CMOS chips, for example, for low-cost and high-speed optical transceivers. Such substrates include a base layer containing silicon, a buried insulator formed on top of the base layer and including an oxide, and a top layer formed on top of the buried insulator and including single crystal silicon. The thickness of the buried insulator is typically between 0.7 μm and 2 μm, and the thickness of the top layer is typically between 0.1 μm and 0.5 μm. The crystalline silicon layer on the insulator can be used to manufacture, for example, optical waveguides and other passive or active optical devices, for example, by appropriate implantation. The buried insulator enables, for example, infrared light to propagate in the silicon layer on the basis of total internal reflection. The top surface of the waveguide can be uncovered and exposed to air (for example, for sensing applications), or covered with a cladding (for example, made of silicon dioxide).

[0042] From a manufacturing perspective, SOI substrates are compatible with most conventional manufacturing processes. Typically, SOI-based processes can be implemented without requiring special equipment or major modifications to existing factories. SOI faces unique challenges in that new metrology requirements are required to account for buried insulators, as well as concerns about stress differences in the top layers that include silicon.

[0043] A two-dimensional electron gas (also called 2DEG) is a gas in which electrons move freely in two dimensions but are strictly confined in the first dimension. This strict confinement results in quantized energy levels for movement in that direction. The electrons appear to be a 2D sheet embedded in a 3D world. Group III nitride-based heterostructures (such as, for example, AlGaN / GaN heterostructures) comprising a first active III-N layer and a second active III-N layer are very suitable for high-power and high-frequency applications due to their high electron speed and high critical electric field. In such a heterostructure, the spontaneous polarization and piezoelectric polarization between the first active III-N layer and the second active III-N layer (i.e., for example, between AlGaN and GaN) produce a two-dimensional electron gas (also called 2DEG).

[0044] In the context of the present invention, Group III nitrides refer to semiconductor compounds formed between Group III elements of the periodic table, such as boron (also known as B), aluminum (also known as Al), gallium (also known as Ga), indium (also known as In), and nitrogen (also known as N). Examples of binary Group III nitride compounds are GaN, AlN, BN, etc. Group III nitrides also refer to ternary and quaternary compounds, such as, for example, AlGaN and InAlGaN.

[0045] In the context of the present invention, the first active III-N layer comprises one or more of N, P, As, and one or more of B, Al, Ga, In, and Tl. The first active III-N layer comprises, for example, GaN. The second active III-N layer comprises one or more of N, P, As, and one or more of B, Al, Ga, In, and Tl. The second active III-N layer comprises, for example, AlGaN. The term AlGaN refers to a composition comprising Al, Ga, and N in any stoichiometric ratio (AlGaN). x Ga y N), wherein x is between 0 and 1 and y is between 0 and 1. Alternatively, the second active III-N layer comprises, for example, AlN. Alternatively, the second active III-N layer comprises InAlGaN. A composition such as InAlGaN comprises In in any suitable amount. Alternatively, the first active III-N layer and the second active III-N layer both comprise InAlGaN, and the bandgap of the second active III-N layer is greater than the bandgap of the first active III-N layer, wherein the polarization of the second active III-N layer is greater than the polarization of the first active III-N layer. Alternatively, the first active III-N layer and the second active III-N layer both comprise BInAlGaN, and the bandgap of the second active III-N layer is greater than the bandgap of the first active III-N layer, wherein the polarization of the second active III-N layer is greater than the polarization of the first active III-N layer. The composition of the active layer can be selected according to the characteristics to be obtained, and the composition can be varied accordingly.

[0046] In the context of the present invention, a gate contact, such as a gate electrode, is provided in the gate region of a high electron mobility transistor. The formation of the gate contact in the gate region includes a plurality of process steps. For example, the step includes depositing a photoresist and performing a photolithography step, such as defining the bottom of the gate contact by completely removing a potential passivation layer (such as, for example, an oxide or one or more dielectric layers) at the top of the second active III-N layer. Alternatively, the step includes depositing a photoresist and performing a photolithography step, such as defining the bottom of the gate contact by partially removing a potential passivation layer (such as, for example, an oxide or one or more dielectric layers) at the top of the second active III-N layer. In this way, some layers of the passivation layer will remain below the gate of the high electron mobility transistor and form a gate dielectric to further reduce the capture effect and leakage current. The gate electrode of the gate contact is, for example, a metal oxide semiconductor gate (also referred to as a MOS gate), and can be made by depositing a metal stack, such as, for example, including Ni, Pt, W, WN or TiN and covered by Al, Au or Cu. The metal pattern is continuously defined by stripping the metal on top of the photoresist. Alternatively, a gate metal stack is deposited, for example comprising Ni, Pt, W, WN or TiN and capped by Al, Au or Cu. A photoresist and photolithography step is then performed, whereby the defined photoresist pattern acts as a mask for dry etching the metal stack in the unwanted areas. The photoresist is then removed.

[0047] According to example embodiments, providing the target wafer further includes forming a target dielectric layer on top of the target substrate, wherein a thickness of the target dielectric layer is equal to or less than 50 nm.

[0048] In the context of the present invention, the donor film of the donor wafer is bonded by direct bonding to the target substrate of the target wafer. In other words, by direct bonding, the donor film of the donor wafer is in direct contact with the target substrate of the target wafer.

[0049] Alternatively, in the context of the present invention, a target dielectric layer is provided on top of the target substrate. The target dielectric layer, for example, comprises silicon dioxide (also referred to as SiO2). For example, the target dielectric layer is a buried oxide layer (also referred to as BOX). The thickness of the target dielectric layer, for example, is equal to or less than 50 nm, for example, 20 nm, 10 nm, 5 nm, etc. Therefore, the thickness of the target dielectric layer is kept as small as possible. The target dielectric layer is used to promote the bonding of the donor film to the target substrate. In other words, the donor film of the donor wafer is bonded to the target dielectric layer of the target wafer.

[0050] According to example embodiments, forming the donor film further includes forming a donor dielectric layer on top of the first donor III-N layer, wherein the thickness of the donor dielectric layer is equal to or less than 10 nm.

[0051] The donor dielectric layer is, for example, a silicon nitride layer, such as, for example, an amorphous silicon nitride layer. For example, the donor dielectric layer is epitaxially grown on top of the first donor III-N layer. The thickness of the donor dielectric layer is kept as thin as possible, such as, for example, 5 nm to 10 nm. The donor dielectric layer serves as a current blocking layer between the target substrate and the high electron mobility transistor manufactured using the method according to the present invention.

[0052] According to example embodiments, bonding the donor film to the target wafer corresponds to bonding the donor dielectric layer to the target dielectric layer, thereby forming a dielectric layer stack including the target dielectric layer and the donor dielectric layer.

[0053] The thickness of the target dielectric layer and the thickness of the donor dielectric layer are kept as small as possible, thereby ensuring that the thickness of the dielectric layer stack between the target substrate and the first donor III-N layer is minimized. For example, the thickness of the dielectric layer stack is equal to or less than 60 nm. This further improves the thermal impedance of the high electron mobility transistor manufactured using the method according to the present invention.

[0054] Alternatively, when the donor film does not include a donor dielectric layer located on top of the first donor III-N layer, bonding the donor film to the target wafer corresponds to directly bonding the first donor III-N layer to the target dielectric layer, thereby forming a dielectric layer stack including the target dielectric layer.

[0055] According to example embodiments, forming the donor film further includes disposing a second donor III-N epitaxial layer between the first donor III-N layer and the donor dielectric layer.

[0056] The second donor III-N epitaxial layer comprises, for example, aluminum nitride. For example, the second donor III-N epitaxial layer comprises epitaxially grown N-polar AlN. The second donor III-N epitaxial layer acts as a back barrier for a high electron mobility transistor fabricated after bonding the donor film to a target wafer, thereby confining electrons in the first active III-N layer of the epitaxial III-N semiconductor layer stack. In this way, there is no need to introduce impurities in the first active III-N layer, thereby further reducing the trapping effect.

[0057] According to example embodiments, the thickness of the second donor III-N epitaxial layer is equal to or less than 10 nm.

[0058] In this way, the thickness of the donor film on the donor wafer is kept as small as possible. This minimizes the thickness of the top surface layer on the target wafer after bonding, thereby improving the thermal impedance of the high electron mobility transistor manufactured using the method according to the present invention.

[0059] According to example embodiments, providing the second donor III-N epitaxial layer corresponds to forming a second donor III-N epitaxial layer as an epitaxially grown layer of N polarity on the donor wafer and between the first donor III-N layer and the donor dielectric layer.

[0060] Thus, when the donor wafer is flipped over and bonded to the target wafer, the second donor III-N epitaxial layer bonded to the target substrate is Ga-polar. Thus, the density of threading dislocations in the epitaxial III-N semiconductor layer stack grown on top of the top surface layer is minimized.

[0061] For example, providing the second donor III-N epitaxial layer corresponds to epitaxially growing the second donor III-N epitaxial layer as a layer of N polarity on top of the donor wafer and between the first donor III-N layer and the donor dielectric layer. Alternatively, providing the second donor III-N epitaxial layer corresponds to epitaxially growing the second donor III-N epitaxial layer as a Ga polarity layer on top of a temporary wafer and between the donor dielectric layer and the material layer of the first donor III-N layer, bonding the temporary wafer to the donor wafer and separating the temporary wafer and the donor wafer at the level of the material layer of the first donor III-N layer, thereby forming the first donor III-N layer on the donor wafer, wherein the second donor III-N epitaxial layer is located on top of the first donor III-N layer and the donor dielectric layer is located on top of the second donor III-N epitaxial layer.

[0062] According to an example embodiment, forming a donor film includes epitaxially growing a first donor III-N layer, and epitaxially growing the first donor III-N layer corresponds to epitaxially growing a first portion and a second portion of the first donor III-N layer and epitaxially growing a third donor III-N epitaxial layer between the first portion and the second portion of the first donor III-N layer; wherein the donor wafer and the target wafer are separated by dividing the first portion of the first donor III-N layer.

[0063] For example, forming the donor film includes epitaxially growing a first donor III-N layer, and epitaxially growing the first donor III-N layer corresponds to epitaxially growing a first portion and a second portion of the first donor III-N layer on top of a sacrificial substrate and epitaxially growing a third donor III-N epitaxial layer between the first portion and the second portion of the first donor III-N layer on top of the sacrificial substrate. In this embodiment, the first donor III-N layer is, for example, epitaxially grown as a layer of N polarity. Alternatively, providing the first donor III-N layer corresponds to epitaxially growing the first donor III-N layer as a Ga polarity layer on top of a temporary wafer, wherein the first donor III-N layer includes a first portion and a second portion located on top of the first portion, combining the temporary wafer with the donor wafer, and separating the temporary wafer and the donor wafer at the level of the first portion, thereby forming the first donor III-N layer on the donor wafer, wherein the second portion of the temporary wafer becomes the first portion of the first donor III-N layer on the donor wafer, and wherein the first portion of the temporary wafer becomes the second portion of the first donor III-N layer on the donor wafer.

[0064] In this way, the donor wafer and the target wafer are separated from each other by segmenting the first portion of the first donor III-N layer on the donor wafer by smart cutting, so that a first remaining portion of the first portion of the first donor III-N layer remains on the sacrificial substrate separated from the target substrate, and also a second remaining portion of the first portion of the first donor III-N layer remains on the target substrate, wherein the sum of the thickness of the first remaining portion and the thickness of the second remaining portion substantially corresponds to the total thickness of the first portion of the first donor III-N layer grown on the sacrificial substrate before bonding. In other words, the first portion of the first donor III-N layer is segmented within its thickness. Such separation forms a top surface layer on the target wafer, the top surface layer at least partially including the first portion of the first donor III-N layer originally grown on the sacrificial substrate and bonded to the target wafer, and including the third donor III-N epitaxial layer, and including the second portion of the first donor III-N layer originally grown on the sacrificial substrate, wherein the thickness of the top surface layer on the target wafer is equal to or less than 200 nm.

[0065] Furthermore, the third donor III-N epitaxial layer can be used as an etch stop for precisely and reliably controlling the thickness of the second portion of the first donor III-N layer. In practice, after bonding the donor film to the target wafer and separating the donor wafer from the target wafer at the level of the first portion of the first donor III-N layer, the first portion of the first donor III-N layer is thinned, for example by chemical mechanical polishing (also referred to as CMP). This first portion of the first donor III-N layer is thinned down to the third donor III-N epitaxial layer. The third donor III-N epitaxial layer can then be selectively etched relative to the second portion of the first donor III-N layer below. For example, wet etching using KOH can be used to selectively etch the AlN of the third donor III-N epitaxial layer without etching the GaN of the second portion of the first donor III-N layer. Thus, this chemical etching of the third donor III-N epitaxial layer can expose the second portion of the first donor III-N layer. In this way, the thickness of the second portion of the first donor III-N layer remaining on the target substrate can be very precisely and reliably controlled in a simple manner. This allows minimizing the thickness of the second portion of the first donor III-N layer on the target substrate by growing the desired thickness of the second portion of the first donor III-N layer on the donor wafer.

[0066] According to an example embodiment, the third donor III-N epitaxial layer includes aluminum nitride.

[0067] The third donor III-N epitaxial layer comprises, for example, AlN. For example, the third donor III-N epitaxial layer comprises AlN of N polarity epitaxially grown on top of a sacrificial substrate. Thus, when the donor wafer is turned upside down and the donor film is bonded to a target wafer, the third donor III-N epitaxial layer comprises AlN of Ga polarity. Thus, the density of threading dislocations in the epitaxial III-N semiconductor layer stack grown on top of the top surface layer is minimized.

[0068] According to example embodiments, providing the donor wafer further includes providing a III-N buffer layer formed between the sacrificial substrate and the donor film.

[0069] The III-N buffer layer formed between the sacrificial substrate and the donor film, for example, comprises an epitaxially grown buffer layer of Ga polarity. In this way, the quality of the epitaxial growth of the first donor III-N layer is improved. The thickness of the III-N buffer layer is, for example, several hundred nanometers or several micrometers. For example, the III-N buffer layer formed between the sacrificial substrate and the donor film, for example, comprises GaN of Ga polarity. In this way, the quality of the epitaxial growth of the first donor III-N layer (for example, the quality of the epitaxial growth of GaN of N polarity) is improved. Optionally, the donor wafer may further include a donor dielectric layer located on top of the first donor III-N layer, wherein the thickness of the donor dielectric layer is equal to or less than 10nm. Optionally, the donor film further includes a second donor III-N epitaxial layer epitaxially grown between the first donor III-N layer and the donor dielectric layer, wherein the second donor III-N epitaxial layer, for example, comprises a material of N polarity (such as, for example, AlN of N polarity), and wherein the thickness of the second donor III-N epitaxial layer is equal to or less than 10nm.

[0070] The properties of the III-N buffer layer may be different from those of the sacrificial substrate, for example, the band gaps of the sacrificial substrate and the III-N buffer layer are relatively far apart, for example, 1.1 eV and 6.2 eV, respectively, i.e., the III-N buffer layer has a high band gap, so as to provide the present characteristics, for example, a high breakdown voltage, for example, greater than 250 V, preferably greater than 500 V, even more preferably greater than 1000 V, for example, greater than 2000 V, or even greater. The III-N buffer layer is, for example, a III-N buffer layer with a high band gap. Wherein III refers to elements of group III, for example, B, Al, Ga, In, Tl, Sc, Y, and lanthanides and actinides. The III-N buffer layer may include a stack of layers, in one example, the first layer on the sacrificial substrate is typically, for example, a nucleation layer.

[0071] According to an example embodiment, the method further comprises the following steps:

[0072] - loading the target wafer including the top surface layer into the epitaxy chamber after separating the donor wafer from the target wafer along the first donor III-N layer and before epitaxially growing the epitaxial III-N semiconductor layer stack; and

[0073] - In-situ desorption of top surface layers in the epitaxy chamber.

[0074] A target wafer including a top surface layer is prepared for epitaxy, for example, the target wafer including the top surface layer is subjected to chemical mechanical polishing to prepare the top surface layer for epitaxy. The target wafer including the top surface layer is loaded into an epitaxial chamber for growing an epitaxial III-N semiconductor layer stack. The surface of the top surface layer is cleaned by an in-situ desorption step, thereby removing any surface or implant damage. In this way, the surface of the top surface layer is in a neat state for in-situ epitaxial growth of an epitaxial III-N semiconductor layer stack located on top of the top surface layer in the epitaxial chamber. This improves the quality of the epitaxial growth of the active layer of the high electron mobility transistor, thereby improving the electrical and thermal characteristics of the high electron mobility transistor. In the context of the present invention, epitaxial growth is performed by MOCVD or MBE or any other suitable epitaxial chamber. The epitaxial layer of the donor wafer can be formed in situ by epitaxial growth in an MOCVD or MBE epitaxial chamber. The first active III-N layer and the second active III-N layer can be formed in situ by epitaxial growth in an MOCVD or MBE epitaxial chamber.

[0075] According to example embodiments, forming the donor film includes epitaxially growing a first donor III-N layer on top of a sacrificial substrate, and epitaxially growing the first donor III-N layer corresponds to epitaxially growing the first donor III-N layer as a layer of N polarity.

[0076] For example, forming the donor film includes epitaxially growing a first donor III-N layer, and epitaxially growing the first donor III-N layer on top of the sacrificial substrate corresponds to epitaxially growing the first donor III-N layer on top of the sacrificial substrate as a layer of N polarity.

[0077] For example, the first donor III-N layer includes GaN of N polarity epitaxially grown on a donor wafer by MOCVD or by MBE. The donor wafer is turned upside down and the first donor III-N layer is bonded on the top side of the target wafer. The donor wafer and the target wafer are then bonded together. In this way, the first donor III-N layer bonded on the top side of the target wafer is of Ga polarity. Therefore, the density of screw dislocations in the epitaxial III-N semiconductor layer stack grown on top of the top surface layer is minimized.

[0078] According to an example embodiment, forming the donor film includes providing a first donor III-N layer. In this example embodiment, the material of the temporary first donor III-N layer is, for example, epitaxially grown on top of a temporary sacrificial substrate of a temporary wafer, and the material of the temporary first donor III-N layer is epitaxially grown as a Ga-polar layer on the temporary sacrificial substrate of the temporary wafer. For example, the temporary first donor III-N layer includes GaN of Ga polarity epitaxially grown on the temporary sacrificial substrate. In this example embodiment, the method further includes the following steps:

[0079] - providing a temporary wafer comprising a temporary first donor III-N layer;

[0080] - bonding a temporary first donor III-N layer to a donor wafer;

[0081] - separating the temporary wafer and the donor wafer by singulating the temporary first donor III-N layer, thereby forming a first donor III-N layer on the donor wafer, the first donor III-N layer at least partially comprising the temporary first donor III-N layer bonded to the donor wafer.

[0082] Thus, the temporary wafer corresponds to a temporary donor wafer further comprising a temporary sacrificial substrate and a temporary first donor III-N layer. Thus, by bonding, the temporary first donor III-N layer is bonded to the sacrificial substrate. In addition, separation can also be performed by separating the temporary wafer and the donor wafer at the interface between the temporary first donor III-N layer and the temporary sacrificial substrate.

[0083] In this way, two layer transfers are performed in sequence by smart cutting. The first transfer starts from a temporary first donor III-N layer grown, for example, as a layer of Ga polarity on a temporary wafer. This temporary first donor III-N layer grown as a layer of Ga polarity is transferred to a donor wafer to form a first donor III-N layer as a layer of N polarity on the donor wafer. A second smart cutting transfer is then performed from the donor wafer to the target wafer, thereby again inverting the material of the original temporary first donor III-N layer and thereby inverting the material of the first donor III-N layer so that the Ga polarity surface of the material of the first donor III-N layer forms the top surface layer on the target wafer. By these additional method steps corresponding to a double layer transfer, it is not necessary to epitaxially grow the first donor III-N layer as a layer of N polarity, for example on top of a sacrificial substrate of the donor wafer. When the first donor III-N layer on top of the sacrificial substrate is epitaxially grown as a layer of Ga polarity, its quality is improved compared to when it is grown as a layer of N polarity.

[0084] According to an example embodiment, providing a temporary wafer corresponds to:

[0085] - providing a temporary sacrificial substrate; and

[0086] - epitaxially growing a temporary first donor III-N layer on top of the temporary sacrificial substrate;

[0087] Alternatively, providing a temporary wafer corresponds to growing a temporary first donor III-N layer as a Ga-polarity host III-N layer, and bonding the temporary first donor III-N layer to the donor wafer corresponds to laying a sacrificial substrate onto one or more temporary wafers by bonding the temporary first donor III-N layer of the temporary wafer to the donor wafer.

[0088] Thus, the donor film is obtained by epitaxially growing a temporary first donor III-N layer on top of a temporary sacrificial substrate of a temporary wafer; or by laying an independent main III-N material on top of a sacrificial substrate. For example, the donor film is obtained by laying an independent main GaN material on top of a sacrificial substrate. The thickness of the independent main III-N material of the temporary first donor III-N layer is, for example, a few hundred microns, such as, for example, 500μm. In this exemplary embodiment, the temporary wafer used for laying is usually not epitaxially grown, but is manufactured using some main crystal growth method (although a temporary wafer including a substrate on which a III-N layer is epitaxially grown can also be envisaged). The simplest method may be to lay the main substrate on the sacrificial substrate of the donor wafer, with the N side facing up along the lateral direction 4 visible in the figure, and then smart cut them onto the target wafer. Since the thickness of the temporary first donor III-N layer is, for example, several hundred microns, the smart cutting process from the donor wafer incorporating the temporary first donor III-N layer to the target wafer can be repeated multiple times with a refresh CMP of the temporary first donor III-N layer in between, thereby reducing processing costs. The temporary first donor III-N layer can, for example, be formed on top of a set of small substrates, for example formed to be Ga-polar, and transferred to a larger donor wafer, thereby forming, for example, a layer of N-polarity. This enables the production of donor wafers from one or more III-N compatible substrates having a diameter smaller than the diameter of the donor wafer.

[0089] According to an example embodiment, the first active III-N layer includes gallium nitride, and wherein a thickness of the first active III-N layer is equal to or less than 50 nm.

[0090] Preferably, the first active III-N layer is epitaxially grown and comprises pure gallium nitride, preferably a single layer of gallium nitride.

[0091] According to an example embodiment, the first active III-N layer includes InAlGaN and the second active III-V layer includes InAlGaN, the bandgap of the second active III-N layer is greater than the bandgap of the first active III-N layer, and the polarization of the second active III-N layer is greater than the polarization of the first active III-N layer.

[0092] In this way, using different materials in the adjacent first active III-N layer and the second III-N layer can lead to polarization, thereby forming a conductive 2DEG region near the connection between the first active III-N layer and the second active III-N layer (especially in the first active III-N layer having a narrower band gap than the band gap of the second active III-N layer).

[0093] According to an example embodiment, the second active III-N layer includes indium gallium aluminum nitride.

[0094] The thickness of the second active III-N layer is, for example, between 10 nm and 100 nm, preferably between 20 nm and 50 nm. Such a thickness combination provides good properties for the active layer, for example in terms of the 2DEG obtained.

[0095] According to an example embodiment, the epitaxial III-N semiconductor layer stack is adapted to carry an electron channel between the source region and the drain region when a positive bias voltage is applied to the gate contact.

[0096] Thus, once a bias voltage greater than a threshold voltage of the high electron mobility transistor is applied to the gate contact, electrons flow in an electron channel under the gate between the source and drain of the high electron mobility transistor.

[0097] According to an example embodiment, the method further comprises the following steps:

[0098] - forming a source contact in the source region in contact with the second active III-N layer; and

[0099] - forming a drain contact in the drain region in contact with the second active III-N layer.

[0100] Preferably, the source contact and / or the drain contact is an ohmic contact formed in the source region and / or the drain region, respectively.

[0101] The source and drain contacts are ohmic contacts to the 2DEG and can be made by depositing a metal stack, such as, for example, Ti / Al / Ni / Au, Ti / Al / Mo / Au, Ti / Al / Ti / Au, Ti / Al / Ti / W, Ti / Al / W, Ti / Al / W / Cr, Ta / Al / Ta, V / Al / Ni / Au, etc., in contact with the second active III-N layer of the epitaxial III-N semiconductor layer stack. The second active III-N layer can be recessed before metal deposition. The contact performance can be further improved by thermal annealing, the temperature of the thermal annealing is typically between 800° C. and 900° C., such as, for example, 850° C., in a nitrogen atmosphere or a forming gas atmosphere. Alternatively, additional metal interconnect layers are defined using methods known to those skilled in the art to achieve low-resistivity current paths for gate, source and drain currents.

[0102] The formation of ohmic contacts in the source region and the formation of ohmic contacts in the drain region include multiple process steps. For example, this begins by depositing a photoresist and is completed by defining the respective regions of the respective ohmic contacts through a photolithography step. The potential passivation layer is then partially or completely removed in the source region and / or the drain region, respectively. Alternatively, the potential passivation layer is completely removed in the source region and / or the drain region. Once the region of the ohmic contacts is defined, that is, when the source region and the drain region are defined, a metal layer or a stack of metal layers can be deposited, for example, by thermal evaporation, by sputtering, or by electron beam evaporation. The metal pattern is continuously defined by stripping the metal on top of the photoresist and without contacting the second active III-N layer. Alternatively, the photoresist is first removed, a metal stack including, for example, Ti and Al is deposited, and then a second photoresist deposition and photoetching step are performed to allow the metal stack to be dry etched and the photoresist to be removed in the unwanted region. The defined ohmic contact may then be subjected to one or more alloying steps, for example a rapid thermal annealing step in a reducing or inert atmosphere such as for example hydrogen or a forming gas or nitrogen, for example at a temperature between 800° C. and 900° C. for one minute.

[0103] According to an example embodiment, the method further comprises the following steps:

[0104] - etching away the epitaxial III-N semiconductor layer stack in one or more regions;

[0105] - in one or more regions, forming one or more recesses extending through the top surface layer at least partially into the target substrate, wherein the one or more recesses are not located between the gate region and the source region or between the gate region and the drain region, thereby defining one or more electrical isolation regions;

[0106] - providing a dielectric layer in the one or more recesses; and

[0107] - forming contacts in one or more electrical isolation regions on top of the dielectric layer, thereby forming one or more electrical isolations.

[0108] One or more grooves extending through the top surface layer until at least partially into the target substrate may, for example, extend through the III-N buffer layer and at least partially through the target substrate. For example, this allows a combination between a SOI target substrate and the above-described electrically isolated deep trench etching to create electrically isolated islands with different substrate biases.

[0109] According to an example embodiment, the method further comprises the step of providing a passivation stack on top of the second active III-N layer.

[0110] Providing a passivation stack on top of the epitaxial III-N semiconductor layer stack corresponds to epitaxially growing the passivation stack on top of the epitaxial III-N semiconductor layer stack.

[0111] The passivation stack is, for example, formed in situ with the formation of the epitaxial III-N semiconductor layer stack. The passivation stack is, for example, formed on top of the second active III-N layer. In this way, a fully crystallized passivation stack is epitaxially grown on top of the epitaxial III-N semiconductor layer stack. Alternatively, a partially crystallized passivation stack is epitaxially grown on top of the epitaxial III-N semiconductor layer stack. The passivation stack can also be formed by ex situ deposition with the help of an epitaxial tool, such as atomic layer deposition (also known as ALD), chemical vapor deposition (also known as CVD), or physical vapor deposition (also known as PVD). Alternatively, the passivation stack can be formed by in situ deposition in a MOCVD or MBE chamber. Alternatively, the passivation stack can be formed by depositing an amorphous film of the same material and recrystallizing it using thermal annealing. The passivation stack located on top of the second active III-N layer, for example, includes silicon nitride. Alternatively, the passivation stack located on top of the second active III-N layer, for example, includes gallium nitride. Alternatively, the passivation stack on top of the second active III-N layer comprises gallium nitride and silicon nitride.

[0112] A passivation stack is formed between the epitaxial III-N semiconductor layer stack and, for example, the gate of a transistor. The passivation stack may be formed only under the gate and may additionally serve as a gate dielectric. Alternatively, the passivation stack may be formed on top of the epitaxial III-N semiconductor layer stack and may completely cover the epitaxial III-N semiconductor layer stack. Alternatively, the passivation stack may be formed on top of the epitaxial III-N semiconductor layer stack and partially cover the surface of the epitaxial III-N semiconductor layer stack, for example, it may be formed in a gate-free region between the source and drain of a high-mobility electron transistor, where it plays a passivation role and prevents depletion of the underlying 2DEG.

[0113] According to an example embodiment, the passivation stack further includes an oxide layer and / or silicon nitride.

[0114] Thus, the passivation stack includes silicon nitride and / or an oxide layer as a passivation layer. The oxide layer has an electrically clean interface with the second active III-N layer, has a high dielectric constant to maximize electrostatic coupling between electrical contacts formed with the semiconductor structure and the 2DEG, thereby increasing the transconductance of, for example, a high electron mobility transistor fabricated with the semiconductor structure, and has sufficient thickness to avoid dielectric breakdown and leakage through quantum tunneling.

[0115] The passivation stack includes, for example, high-density SiN deposited in-situ in a MOCVD reactor. The SiN can be stoichiometric or non-stoichiometric. The inventors have experimentally demonstrated that, for example, HEMT structures covered with in-situ SiN are not affected by processing steps, even those with a high-temperature budget. Alternatively, the passivation stack includes, for example, AlSiN. Al doping allows increasing the bandgap of the dielectric material. Alternatively, the electron-donating dielectric layer includes one or more of Si, Al, O, and N. The passivation stack has a thickness of, for example, 1 nm to 500 nm, preferably 30 nm to 400 nm, more preferably 50 nm to 300 nm, for example 100 nm to 200 nm. The in-situ SiN can be thickened externally, for example to a thickness exceeding 500 nm, by PECVD or LPCVD SiN or SiOx before any other processing. The thin passivation stack allows the formation of ohmic contacts with low resistance. In addition, the passivation stack includes, for example, Si, which can diffuse into AlGaN acting as a donor. Introducing a donor type in the AlGaN layer is beneficial for the formation of ohmic contacts, thereby reducing the contact resistance. The passivation stack is formed at a temperature between 700 °C and 1300 °C, between 700 °C and 1250 °C, between 700 °C and 1100 °C. It should be understood that when referring to SiN, it means a compound composed of Si and N. SiN can include Si3N4, but also other molecular formulas, such as (but not limited to) Si x N y , with different stoichiometric or non-stoichiometric ratios. In the molecular formula Si x N y , x and y can be defined as real numbers, where 0 < x ≤ 100 and 0 < y ≤ 100. When growing an epitaxial III-N semiconductor layer stack, NH3 flow is maintained in the reaction chamber and the SiH4 line is opened, allowing for the growth of SiN and high temperature. After SiN growth, the SiH4 flow is stopped and the structure is cooled to room temperature while maintaining NH3 flow to avoid desorption of the top layer.

[0116] According to an example embodiment, the passivation stack is grown epitaxially on top of the second active III-N layer.

[0117] Maintaining the crystallinity of the in-situ grown SiN by doping or adding species such as Al or B is an advantage. When grown on top of the second active III-N layer, the in-situ SiN deforms to accommodate the strain caused by the lattice mismatch between the materials. It is well known that large lattice mismatches trigger the epitaxial growth mode to change from a two-dimensional Franck-Van der Merwe layer-by-layer growth mode to a three-dimensional Volker-Weber growth mode, which in turn makes it easier to change to an amorphous growth mode. Therefore, atoms smaller than Si (such as Al or B) can be introduced into SiN to reduce the lattice constant of the β-phase SiN to make it more closely matched to the lattice constant of the second active III-N layer. Another advantage of including Al in the SiN lattice is that it has a stronger resistance to dry etching in fluorine-based plasmas due to the interaction between Al and F to produce highly non-volatile AlF. The passivation stack is fully crystalline. Alternatively, the passivation stack is partially crystalline and includes at least a few crystalline monolayers.

[0118] According to an example embodiment, the passivation stack is etched away at the source region and the drain region, respectively.

[0119] Thus, openings are defined in the electron-donating dielectric layer to uncover the source region and the drain region, respectively, in which the device terminals are formed. For example, a photolithography step may be performed and the electron-donating dielectric layer may be etched away in the source region and the drain region, respectively. For example, the passivation stack may be removed by wet etching in HF or buffered HF with fluorine chemistry or dry etching in a RIE or ICP plasma tool.

[0120] In fluorine chemistry, both dry and wet etching of the passivation stack will stop on the second active III-N layer, which acts as an etch stop with very high selectivity. For example, etching of the electron-donating dielectric layer is done in a dry etching system based on fluorine chemistry, such as, for example, in an inductively coupled plasma system, using SF6 or CF4 as etching gas, with RF or "platen" and ICP or "coil" etching powers of 10W to 150W respectively. This allows for complete removal of the remaining passivation stack without removing the second active III-N layer or any layers below. Alternatively, the second active III-N layer is partially etched with a wet etch, such as in an alkaline solution or resist developer, thereby allowing portions of the source and drain regions of the active layer to form respective ohmic contacts.

[0121] According to a second aspect of the present invention, there is provided a high electron mobility transistor, comprising:

[0122] - target substrate;

[0123] - a top surface layer located on top of the target substrate; wherein the thickness of the top surface layer is less than 200 nm;

[0124] - an epitaxial III-N semiconductor layer stack located on top of the top surface layer, wherein the epitaxial III-N semiconductor layer stack comprises:

[0125] ○ First active III-N layer;

[0126] o a second active III-N layer on top of the first active III-N layer;

[0127] a two-dimensional electron gas between the first active III-N layer and the second active III-N layer;

[0128] - a gate contact in contact with the second active III-N layer in the gate region; and

[0129] - Substrate electrical contacts in contact with the target substrate.

[0130] The high electron mobility transistor according to the present invention can be formed on any substrate, even for example a heterogeneous substrate. The high electron mobility transistor according to the present invention is formed by an epitaxial III-N semiconductor layer stack grown on top of a top surface layer, which is bonded to (i.e., transferred to by smart cutting) for example a silicon substrate (such as, for example, a high-resistance silicon substrate), or a SiC substrate (such as, for example, a semi-insulating SiC substrate), or a silicon-on-insulator substrate, or a germanium substrate, or a germanium-on-insulator substrate, or a sapphire substrate, etc. In addition, the donor film is bonded to the target wafer without providing a buffer layer on the target wafer between the substrate and the high electron mobility transistor before bonding. In other words, a buffer layer must not be grown on the target substrate before the donor film is bonded to the target substrate. Therefore, compared with the prior art high electron mobility transistor grown on, for example, a semi-insulating SiC substrate or a high-resistance Si substrate, the high electron mobility transistor according to the present invention is not susceptible to the trapping effect.

[0131] Another advantage of the high electron mobility transistor according to the present invention is that its thermal impedance is improved. Since there is no buffer layer between the epitaxial III-N semiconductor layer stack and the target substrate, since the thickness of the transferred first donor III-N layer forming the top surface layer is kept as thin as possible, and since the thickness of the total layer stack formed on the target substrate is limited, the high electron mobility transistor can achieve low thermal resistivity. In other words, the thermal impedance between the heat sink at the bottom of the target substrate and the active device (such as, for example, the high electron mobility transistor manufactured according to the present invention) is small. The thickness of the top surface layer is kept as small as possible, the thickness of the layer is a maximum of 200nm, preferably less than 100nm, and preferably less than 50nm.

[0132] Another advantage of the high electron mobility transistor according to the present invention is that the thin layer stack formed on the top of the target substrate enables the substrate to be used as the fourth terminal of the high electron mobility transistor. In this way, the substrate electrical contact in contact with the target substrate can indeed be used to apply a bottom side voltage bias to the target substrate relative to the source contact of the high electron mobility transistor. Due to the small thickness of the layer between the bottom side of the target substrate and the 2DEG, this substrate electrical contact can be used in turn to control or change certain characteristics or parameters of the high electron mobility transistor, such as, for example, the threshold voltage and / or cut-off state leakage of the high electron mobility transistor. The substrate electrical contact can also be used to adjust the charge state of the buffer trap or the main trap present in the target substrate, for example, so as to minimize or eliminate the capture effect of the high electron mobility transistor, and thereby reduce the memory effect of the high electron mobility transistor. After the combination and epitaxial growth of the epitaxial III-N semiconductor layer stack, the substrate electrical contact can be formed on the bottom side of the target substrate and is substantially located below the gate region of the high electron mobility transistor manufactured on the target wafer. Alternatively, after bonding and epitaxial growth of the epitaxial III-N semiconductor layer stack, a substrate electrical contact may be formed on the bottom side of the target substrate and substantially below the high electron mobility transistor fabricated on the target wafer.

[0133] According to an example embodiment, the HEMT further includes a dielectric layer stack formed between the target substrate and the top surface layer; and wherein a thickness of the dielectric layer stack is equal to or less than 60 nm.

[0134] According to an example embodiment, the HEMT further includes a second donor III-N epitaxial layer formed between the dielectric layer stack and the top surface layer; and wherein the second donor III-N epitaxial layer has a thickness equal to or less than 10 nm. BRIEF DESCRIPTION OF THE DRAWINGS

[0135] Some example embodiments will now be described with reference to the accompanying drawings. For clarity, the accompanying drawings depict cross-sections of wafers and high electron mobility transistors according to the present invention. Obviously, the wafers and high electron mobility transistors depicted in the accompanying drawings can have any shape and extend in any direction along the longitudinal direction 3 and / or the lateral direction 4, and / or a third direction 5 that is transverse to the longitudinal direction 3 and transverse to the lateral direction 4. In order to keep the drawings concise, the above directions are not repeated in all drawings.

[0136] Figures 1A to 1J An exemplary embodiment of the steps of a method for manufacturing a high electron mobility transistor according to the present invention is schematically depicted, wherein Figure 1J An example embodiment of a high electron mobility transistor according to the invention is schematically depicted. Figure 1K It shows that Figure 1F Alternative embodiments of the manufacturing steps are shown.

[0137] Figure 2 An exemplary embodiment of a target wafer according to the present invention is schematically depicted.

[0138] Figure 3A An example embodiment of a donor wafer according to the present invention is schematically depicted. Figure 3B Schematically depicts a method according to the present invention and Figure 3A An example embodiment of a target wafer according to the present invention after bonding of a donor wafer is depicted in FIG.

[0139] Figure 4 An example embodiment after target wafer bonding according to the present invention is schematically depicted.

[0140] Figure 5 An example embodiment of a donor wafer according to the present invention is schematically depicted.

[0141] Figure 6 An example embodiment of a donor wafer according to the present invention is schematically depicted.

[0142] Figure 7 An example embodiment of a donor wafer according to the present invention is schematically depicted.

[0143] FIG. 8A to FIG. 8H An exemplary embodiment of the steps of a method of manufacturing a high electron mobility transistor from a donor wafer according to the invention is schematically depicted. Figure 8I It shows that Figure 8F Alternative embodiments of the manufacturing steps are shown.

[0144] Fig. 9 An example embodiment of a high electron mobility transistor with source and drain contacts according to the present invention is schematically depicted.

[0145] Fig.10 An example embodiment of a high electron mobility transistor with electrical isolation according to the present invention is schematically depicted. DETAILED DESCRIPTION

[0146] Figures 1A to 1J An exemplary embodiment of the steps of the method for manufacturing a high electron mobility transistor 1 according to the present invention is schematically depicted. Figure 1A As shown, a donor wafer 20 is provided. The donor wafer 20 includes a sacrificial substrate 200. A donor film 21 is formed on top of the sacrificial substrate 200. The donor film 21 includes a first donor III-N layer 201. The first donor III-N layer 201 is, for example, epitaxially grown on top of the sacrificial substrate 200. A target wafer 10 including a target substrate 100 is also provided, as shown in FIG. Figure 1B As shown. Figure 1C In the embodiment of the present invention, the donor wafer 20 is turned upside down relative to its initial orientation and relative to the target wafer 10. Then, as shown in FIG. Figure 1D As shown, the inverted donor wafer 20 is lowered toward the target wafer 10 . Figure 1E The donor film 201 is shown bonded to the target wafer 10. Figure 1F The donor wafer 20 and the target wafer 10 are separated from each other by a plane 40 shown in FIG. The donor wafer 20 and the target wafer 10 are separated by slicing the first donor III-N layer 201 at the level of the plane 40, thereby forming a top surface layer 221 on the target wafer 10, the top surface layer 221 including at least a portion of the first donor III-N layer 201 bonded to the target wafer 10, and also forming a donor surface layer 222 on the donor wafer 20, the donor surface layer 222 including at least a portion of the first donor III-N layer 201 epitaxially grown on the donor wafer 20, as shown in FIG. Figure 1G As shown. The thickness of the top surface layer 221 is equal to or less than 200 nm. In addition, the sum of the thickness of the top surface layer 221 and the thickness of the donor surface layer 222 substantially corresponds to the thickness of the first donor III-N layer 201 epitaxially grown on the donor wafer 20. Figure 1K In the alternative embodiment shown, the donor wafer 20 and the target wafer 10 are separated at the interface 40 between the first donor III-N layer 201 and the sacrificial substrate 200, thereby forming a top surface layer 221 on the target wafer 10, the top surface layer 221 comprising the first donor III-N layer 201 bonded to the target wafer 10. In this alternative embodiment, the thickness of the top surface layer 221 is equal to or less than 200 nm and substantially corresponds to the thickness of the first donor III-N layer 201 epitaxially grown on the donor wafer 20. Thus, the method according to the present invention produces Figure 1H The semiconductor structure depicted forms a top surface layer 221 on a target substrate 100 of a target wafer 10 . Fig. 1I The following method steps are shown for epitaxially growing an epitaxial III-N semiconductor layer stack 300 on top of the top surface layer 221, wherein the epitaxial III-N semiconductor layer stack 300 comprises a first active III-N layer 31 and a second active III-N layer 32, wherein the first active III-N layer 31 and the second active III-N layer 32 have a two-dimensional electron gas 33 therebetween. Figure 1J As shown, the method further comprises the steps of forming a gate contact in the gate region 401 in contact with the second active III-N layer 32 and forming a substrate electrical contact 42 in contact with the back side of the target substrate 100 along the lateral direction 4. The high electron mobility transistor 1 has been manufactured.

[0147] Figure 2An exemplary embodiment of a target wafer 10 according to the present invention is schematically shown. Figures 1A to 1J Components with the same reference numerals perform the same functions. Providing the target wafer 10 may further include forming a target dielectric layer 101 on top of the target substrate 10. The thickness of the target dielectric layer 101 is equal to or less than 50 nm. Using the target wafer 10, the donor film 201 of the donor wafer 20 is combined with the target dielectric layer 101 of the target wafer 10.

[0148] Figure 3A An exemplary embodiment of a donor wafer 20 according to the present invention is schematically depicted. Figures 1A to 1J or Figure 2 Components with the same reference numerals perform the same functions. Forming the donor film 201 further includes forming a donor dielectric layer 202 on top of the first donor III-N layer 201. The thickness of the donor dielectric layer 202 is equal to or less than 10 nm. Then Figure 3A The donor wafer 20 is turned upside down and then combined with the target wafer 10. Figure 3B Schematically depicts a method according to the present invention and Figure 3A The donor wafer 20 depicted in FIG. Figure 1B An exemplary embodiment of a target wafer 10 according to the present invention after bonding of the target wafer 10 . Figure 3B 1 shows a target substrate 100 on which a donor dielectric layer 202 and a top surface layer 221 are combined. The top surface layer 221 is formed after the first donor III-N layer 201 is segmented to separate the donor wafer 20 and the target wafer 10. According to an alternative embodiment, according to the present invention and in Figure 3A The donor wafer 20 depicted in FIG. Figure 2 The target wafer 10 is bonded.

[0149] Figure 4 Schematically depicts an example embodiment after target wafer bonding according to the present invention. Figures 1A to 1J or Figure 2 or Figure 3A or Figure 3B Components with the same reference numerals perform the same functions. Forming the donor film further includes forming a donor dielectric layer 202 on top of the first donor III-N layer of the donor wafer. The thickness of the donor dielectric layer 202 is equal to or less than 10 nm. The donor wafer is then turned upside down and bonded to a target wafer including a target substrate 100 on which a target dielectric layer 101 is formed. The thickness of the target dielectric layer 101 is equal to or less than 50 nm. Figure 4The target wafer after the donor wafer is bonded to the target wafer is schematically depicted. The donor dielectric layer 202 and the top surface layer 221 are bonded to the target dielectric layer 101 to form a dielectric layer stack 22 including the target dielectric layer 101 and the donor dielectric layer 202. The thickness of the dielectric layer stack 22 is equal to or less than 60 nm. The top surface layer 221 is formed after the first donor III-N layer 201 is segmented to separate the donor wafer and the target wafer.

[0150] Figure 5 An exemplary embodiment of a donor wafer 20 according to the present invention is schematically depicted. Figures 1A to 1J or Figure 2 or Figure 3A or Figure 3B or Figure 4 Components with the same reference numerals perform the same functions. The target wafer 20 includes a sacrificial substrate 200 on which a donor film 21 is formed. The donor film 21 includes a first donor III-N layer 201 and a donor dielectric layer 202 located on top of the first donor III-N layer 201. The thickness of the donor dielectric layer 202 is equal to or less than 10 nm. The donor film 21 further includes a second donor epitaxial layer 203 disposed between the first donor III-N layer 201 and the donor dielectric layer 202. The second donor epitaxial layer 203 is epitaxially grown between the first donor III-N layer 201 and the donor dielectric layer 202. For example, the second donor epitaxial layer 203 is epitaxially grown between the first donor III-N layer 201 and the donor dielectric layer 202 as an N-polarity layer. The thickness of the second donor epitaxial layer 203 is equal to or less than 10 nm.

[0151] Figure 6 An exemplary embodiment of a donor wafer 20 according to the present invention is schematically depicted. Figures 1A to 1J or Figure 2 or Figure 3A or Figure 3B or Figure 4 or Figure 5 Components with the same reference numerals perform the same functions. Figure 6The donor wafer 20 includes a sacrificial substrate 200. A donor film 21 is formed on top of the sacrificial substrate 200 of the donor wafer 20. Forming the donor film 21 includes epitaxially growing a first donor III-N layer 201, wherein epitaxially growing the first donor III-N layer 201 corresponds to, for example, epitaxially growing a first portion 211 and a second portion 212 of the first donor III-N layer 201 on top of the sacrificial substrate 200 and epitaxially growing a third donor III-N epitaxial layer 205 between the first portion 211 and the second portion 212 of the first donor III-N layer 201. Then, the donor wafer 20 and the target wafer are separated by segmenting the first portion 211 of the first donor III-N layer 201, and the third donor III-N epitaxial layer 205 is used as an etch stop for the second portion 212 of the first donor III-N layer 201, thereby forming a top surface layer on top of the target wafer, wherein the top surface layer includes the second portion 212 of the first donor III-N layer 201 after removing the third donor III-N epitaxial layer 205. The third donor III-N epitaxial layer 205 includes, for example, AlN.

[0152] Figure 7 An exemplary embodiment of a donor wafer 20 according to the present invention is schematically depicted. Figures 1A to 1J or Figure 2 or Figure 3A or Figure 3B or Figure 4 or Figure 5 or Figure 6 Components with the same reference numerals perform the same functions. The donor wafer 20 includes a sacrificial substrate 200 on which a III-N buffer layer 204 is disposed. In other words, the III-N buffer layer 204 is formed between the sacrificial substrate 200 and a donor film 21 of the donor wafer 20. The donor film 21, for example, includes a first donor III-N layer 201. According to an alternative embodiment, the donor film 21, for example, includes a first donor III-N layer 201 and a donor dielectric layer 202. According to another alternative embodiment, the donor film 21, for example, includes a first donor III-N layer 201, a donor dielectric layer 202, and a second donor epitaxial layer 203 disposed between the first donor III-N layer 201 and the donor dielectric layer 202.

[0153] FIG. 8A to FIG. 8H An exemplary embodiment of the steps of a method of manufacturing a high electron mobility transistor from a donor wafer 20 according to the present invention is schematically depicted. Figures 1A to 1J or Figure 2 or Figure 3A or Figure 3B or Figure 4 or Figure 5 or Figure 6 or Figure 7Components with the same reference numerals perform the same functions. Fig. 8A As shown, a temporary donor wafer 30 is provided. In this exemplary embodiment, the temporary donor wafer 30 includes a temporary sacrificial substrate 400. Fig. 8A As shown, a temporary first donor III-N layer 401 is epitaxially grown on top of a temporary sacrificial substrate 400. A donor wafer 20 is provided, wherein the donor wafer 20, for example, includes a sacrificial substrate 200. According to an alternative embodiment, the donor wafer 20, for example, includes a sacrificial substrate 200 and further includes a dielectric layer located on top of the sacrificial layer, wherein the thickness of the dielectric layer is equal to or less than 50 nm and wherein the dielectric layer facilitates bonding. Figure 8C As shown, the temporary first donor III-N layer 401 is turned upside down relative to the donor wafer 20 and relative to its initial orientation. The temporary first donor III-N layer 401 is bonded to the donor wafer 20, for example, as Fig.8D As shown, the temporary donor wafer 30 and the donor wafer 20 are directly bonded to the sacrificial substrate 200, or alternatively bonded to a dielectric layer formed on the sacrificial substrate 200. The temporary donor wafer 30 and the donor wafer 20 are separated by slicing the temporary first donor III-N layer 401 at the level of the plane 410, thereby forming the first donor III-N layer 201 on the donor wafer 20, wherein the first donor III-N layer 201 at least partially includes the temporary first donor III-N layer 401 bonded to the donor wafer 20. Figure 8I In another embodiment shown, the temporary donor wafer 30 and the donor wafer 20 are separated at the interface 410 between the temporary first donor III-N layer 401 and the temporary sacrificial substrate 400, thereby forming the first donor III-N layer 201 on the donor wafer 20, wherein the first donor III-N layer 201 includes the temporary first donor III-N layer 401 bonded to the donor wafer 20. According to another alternative embodiment, the temporary donor wafer 30 corresponds to the temporary first donor III-N layer 401 grown, for example, as a Ga-polar bulk III-N layer. The temporary first donor III-N layer 401 is then bonded to the donor wafer 20. For example, one or more temporary donor wafers 30 are bonded to the donor wafer 20, wherein the diameter of the donor wafer 20 is greater than the diameter of the temporary donor wafer 30. The donor wafer 20, for example, includes the sacrificial substrate 200. According to an alternative embodiment, the donor wafer 20 comprises, for example, a sacrificial substrate 200 and further comprises a dielectric layer located on top of the sacrificial layer, wherein the thickness of the dielectric layer is equal to or less than 50 nm and wherein the dielectric layer facilitates bonding. Figure 8C As shown, the temporary first donor III-N layer 401 is turned upside down relative to the donor wafer 20 and relative to its initial orientation. The temporary first donor III-N layer 401 is bonded to the donor wafer 20, for example, as Fig.8DAs shown, the temporary donor wafer 30 and the donor wafer 20 are directly bonded to the sacrificial substrate 200, or alternatively bonded to a dielectric layer formed on the sacrificial substrate 200. The temporary donor wafer 30 and the donor wafer 20 are separated by slicing the temporary first donor III-N layer 401 at the level of the plane 410, thereby forming the first donor III-N layer 201 on the donor wafer 20, wherein the first donor III-N layer 201 at least partially includes the temporary first donor III-N layer 401 bonded to the donor wafer 20. Then, the donor film 21 including the first donor III-N layer 201 is bonded to a target wafer (e.g. Figure 1B and using the donor wafer 20 and the target wafer as Figure 1C to Figure 1J The method steps described in .

[0154] Fig. 9 An exemplary embodiment of a high electron mobility transistor 1 according to the invention having a source contact 43 and a drain contact 44 is schematically depicted. Figures 1A to 1J or Figure 2 or Figure 3A or Figure 3B or Figure 4 or Figure 5 or Figure 6 or Figure 7 Components with the same reference numerals perform the same functions. Figures 1A to 1J The method depicted in further comprises the steps of forming a source contact 43 in the source region 403 in contact with the second active III-N layer 32 , and forming a drain contact 44 in the drain region 404 in contact with the second active III-N layer 32 .

[0155] Fig.10 An exemplary embodiment of a high electron mobility transistor 1 with electrical isolation according to the present invention is schematically depicted. Figures 1A to 1J or Figure 2 or Figure 3A or Figure 3B or Figure 4 or Figure 5 or Figure 6 or Figure 7 Components with the same reference numerals perform the same functions. Figures 1A to 1JThe method depicted in further comprises the following steps: for a high electron mobility transistor 1 manufactured using the method according to the invention, forming a source contact 43 in the source region 403 in contact with the second active III-N layer 32, and forming a drain contact 44 in the drain region 404 in contact with the second active III-N layer 32. The method further comprises the following steps: etching away the epitaxial III-N semiconductor layer stack 300 in one or more electrically isolated regions. The method further comprises the following steps: forming one or more recesses 500 extending through the top surface layer 221 until at least partially into the target substrate 100, wherein one or more recesses 500 are not located between the gate region 401 and the source region 403 or between the gate region 401 and the drain region 404, thereby defining one or more electrically isolated regions. The method further comprises the following steps: providing a dielectric layer 501 along the sidewalls 505; 506 of the one or more recesses 500. The method further includes the following steps: forming a contact 502 in one or more electrical isolation regions, so that the contact 502 is in direct contact with the target wafer 100 along the lateral direction 4 at the bottom 504 of each groove 500, and the contact 502 is in contact with the dielectric layer 501 along the sidewalls 505; 506 of each groove 500, thereby forming one or more electrical isolations.

[0156] Although the present invention has been described with reference to specific embodiments, it will be apparent to those skilled in the art that the present invention is not limited to the details of the above illustrative embodiments, and that the present invention can be implemented through various changes and modifications without departing from its scope. Therefore, the embodiments of the present invention are considered in all aspects to be illustrative and not restrictive, and the scope of the present invention is indicated by the appended claims rather than by the above description, and therefore, all changes within the scope of the claims are intended to be included therein.

[0157] The reader of this patent application will further understand that the words "comprising" or "including" do not exclude other elements or steps, the words "one" or "an" do not exclude multiple, and a single element, such as a computer system, a processor or another integrated unit, can implement the functions of several devices described in the claims. Any figure mark in the claims should not be interpreted as a limitation on the relevant individual claims. When used in the specification or claims, the terms "first", "second", "third", "a", "b", "c", etc. are introduced to distinguish similar elements or steps, and are not necessarily to describe the order or time sequence. Similarly, the terms "top", "bottom", "upper", "lower", etc. are introduced for descriptive purposes and are not necessarily to indicate relative positions. It should be understood that the terms used in this way are interchangeable where appropriate, and embodiments of the present invention can be operated in other orders or directions different from those described or illustrated above according to the present invention.

Claims

1. A method for manufacturing a high electron mobility transistor (1), the method comprising: The following steps are involved: - providing a target wafer (10) comprising a target substrate (100); - providing a donor wafer (20), wherein providing the donor wafer (20) comprises: ○Providing a sacrificial substrate (200); o forming a donor film (21) on top of the sacrificial substrate (200); wherein the donor film (21) comprises a first donor III-N layer (201); - combining the donor film (21) with the target wafer (10); - separating the donor wafer (20) and the target wafer (10) by slicing the first donor III-N layer (201), or separating the donor wafer (20) and the target wafer (10) at an interface between the first donor III-N layer (201) and a sacrificial substrate (200), thereby forming a top surface layer (221) on the target wafer (10), the top surface layer at least partially comprising the first donor III-N layer (201) bonded to the target wafer (10), wherein the thickness of the top surface layer (221) is equal to or less than 200 nm; - epitaxially growing an epitaxial III-N semiconductor layer stack (300) on top of the top surface layer (221), wherein the epitaxial III-N semiconductor layer stack (300) comprises: ○ A first active III-N layer (31); ○ a second active III-N layer (32) located on top of the first active III-N layer (31); a two-dimensional electron gas (33) between the first active III-N layer (31) and the second active III-N layer (32); - forming a gate contact (41) in the gate region (401) in contact with the second active III-N layer (32); and - forming a substrate electrical contact (42) in contact with said target substrate (100).

2. The method according to claim 1, in, Providing the target wafer (10) further includes forming a target dielectric layer (101) on top of the target substrate (100), wherein the thickness of the target dielectric layer (101) is equal to or less than 50 nm.

3. The method according to any one of the preceding claims, in, Forming the donor film (21) further includes forming a donor dielectric layer (202) on top of the first donor III-N layer (201), wherein the thickness of the donor dielectric layer (202) is equal to or less than 10 nm.

4. The method according to claims 2 and 3, in, Combining the donor film (21) with the target wafer (10) corresponds to combining the donor dielectric layer (202) with the target dielectric layer (101), thereby forming a dielectric layer stack (22) including the target dielectric layer (101) and the donor dielectric layer (202).

5. The method according to claim 3 or 4, in, Forming the donor film (21) further includes providing a second donor III-N epitaxial layer (203) between the first donor III-N layer (201) and the donor dielectric layer (202); and wherein the thickness of the second donor III-N epitaxial layer (203) is equal to or less than 10 nm.

6. The method according to claim 5, in, Providing the second donor III-N epitaxial layer (203) corresponds to forming a second donor III-N epitaxial layer (203) epitaxially grown as an N-polarity layer between the first donor III-N layer (201) and the donor dielectric layer (202).

7. The method according to any one of the preceding claims, in, Forming the donor film (21) includes epitaxially growing the first donor III-N layer (201), and wherein epitaxially growing the first donor III-N layer (201) corresponds to epitaxially growing a first portion (211) and a second portion (212) of the first donor III-N layer (201) and epitaxially growing a third donor III-N epitaxial layer (205) between the first portion (211) and the second portion (212) of the first donor III-N layer (201); and wherein the donor wafer (20) and the target wafer (10) are separated by dividing the first portion (211) of the first donor III-N layer (201).

8. The method according to claim 7, in, The third donor III-N epitaxial layer (205) includes aluminum nitride.

9. The method according to any one of the preceding claims, in, Forming the donor film (21) includes epitaxially growing the first donor III-N layer (201), and wherein epitaxially growing the first donor III-N layer (201) corresponds to epitaxially growing the first donor III-N layer (201) as an N-polar layer.

10. The method according to any one of claims 1 to 8, further comprising: The following steps are involved: - providing a temporary donor wafer (30), said temporary donor wafer comprising a temporary sacrificial substrate (400) and a temporary first donor III-N layer (401); - bonding the temporary first donor III-N layer (401) to the sacrificial substrate (200); - separating the temporary donor wafer (30) and the donor wafer (20) by splitting the temporary first donor III-N layer (401), or separating the temporary wafer (30) and the donor wafer (20) at the interface between the temporary first donor III-N layer (401) and the temporary sacrificial substrate (400), thereby forming the first donor III-N layer (201) on the donor wafer (20), wherein the first donor III-N layer at least partially includes the temporary first donor III-N layer (401) bonded to the donor wafer (20).

11. The method according to claim 10, in, Providing a temporary donor wafer (30) corresponds to: - providing a temporary sacrificial substrate (400); and - epitaxially growing the temporary first donor III-N layer (401) on top of the temporary sacrificial substrate (400); Alternatively, providing the temporary donor wafer (30) corresponds to growing the temporary first donor III-N layer (401) into a Ga-polar main III-N layer, and combining the temporary first donor III-N layer (401) with the sacrificial substrate (200) corresponds to paving the sacrificial substrate (200) with one or more temporary donor wafers (30) by combining the temporary first donor III-N layer (401) of the temporary donor wafer (30) with the sacrificial substrate (200).

12. The method according to any one of the preceding claims, in, The method further comprises the following steps: - forming a source contact (43) in the source region (403) in contact with the second active III-N layer (32); and - forming a drain contact (44) in the drain region (404) in contact with the second active III-N layer (32).

13. The method according to claim 12, in, The method further comprises the following steps: - etching away the epitaxial III-N semiconductor layer stack (300) in one or more regions; - forming one or more recesses (500) extending through the top surface layer (221) until at least partially entering the target substrate (100) in the one or more regions, wherein the one or more recesses (500) are not located between the gate region (401) and the source region (403) or between the gate region (401) and the drain region (404), thereby defining one or more electrical isolation regions; - providing a dielectric layer (501) in one or more of said recesses (500); and - forming contacts (502) in said one or more electrical isolation regions on top of said dielectric layer (501), thereby forming one or more electrical isolations.

14. A high electron mobility transistor (1), wherein include: - a target substrate (100); - a top surface layer (221) located on top of the target substrate (100); wherein the thickness of the top surface layer (221) is less than 200 nm; - an epitaxial III-N semiconductor layer stack (300) located on top of the top surface layer (221), wherein the epitaxial III-N semiconductor layer stack (300) comprises: ○ A first active III-N layer (31); o a second active III-N layer (32) located on top of the first active III-N layer (31); a two-dimensional electron gas (33) between the first active III-N layer (31) and the second active III-N layer (32); - a gate contact (41) in contact with said second active III-N layer in the gate region (401); and - a substrate electrical contact (42) in contact with said target substrate (100).

15. The high electron mobility transistor according to claim 14, in, The high electron mobility transistor (1) further comprises at least two dielectric layers (101, 202) between the target substrate (100) and the top surface layer (221); and wherein the thickness of the at least two dielectric layers (101, 202) is equal to or less than 60 nm.

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