System and method for expanding number of IO ports based on 3-8 decoders

Abstract

The invention discloses a system and method for expanding the number of IO ports based on a 3-8 decoder, and relates to the technical field of automation control, and the system comprises a microcontroller IO interface, an enabling module, an output module, a filter capacitor, a state indication module and a current limiting resistor. Wherein the first pin, the second pin and the third pin of the microcontroller IO interface are all connected with the input pins of the output modules, the fourth pin, the fifth pin and the sixth pin of the microcontroller IO interface are connected with the input pin of the enabling module, the output pin of the enabling module is connected with the effective enabling pins of the output modules, the output pins of the output modules are connected with the input end of the state indicating module, and the state indicating module is connected with the output end of the microcontroller IO interface. A high-level enabling pin of the output module is connected with the filter capacitor, and the output end of the state indication module is connected with the current-limiting resistor. According to the invention, the 3-8 decoders are adopted as core components of the enabling module and the output module, so that the system cost can be remarkably reduced, and the occupied space is reduced to the greatest extent.

Description

Technical Field

[0001] The present invention relates to the field of automation control technology, and in particular to a system and method for expanding the number of IO ports based on a 3-8 decoder. Background Art

[0002] In the field of automation control, DSP (digital signal processor) is a high-performance processing chip that is widely used in power electronic control systems due to its fast computing power and rich interface functions. Especially in power electronic systems, DSP can perform complex algorithm processing to achieve precise control, stable operation and efficient energy conversion of power electronic devices. By using DSP, the system can complete the real-time acquisition and processing of key parameters such as voltage and current, and then realize closed-loop feedback control to improve the stability and response speed of the system. In addition, DSP, with its fast floating-point computing power, can support advanced algorithms, such as space vector pulse width modulation (SVPWM) and predictive control algorithms, which are particularly important for the optimized control of inverters, rectifiers and other equipment in power electronic systems.

[0003] However, as the scale and complexity of power electronic control systems continue to increase, the limitations of DSP have begun to emerge. Modern power electronic systems usually contain a large number of sensors, execution units, display modules, etc., which has led to a sharp increase in the system's demand for IO (input and output) interfaces. Although the number of DSP IO ports is relatively large, as the scale of the system expands, these IO ports are often difficult to cover all devices. Especially in large-scale power systems, such as the power system of electric vehicles and multi-level energy conversion equipment in smart grids, the number of control objects is huge, and the IO resources of the DSP are quickly exhausted, resulting in the system being unable to effectively control all devices.

[0004] Faced with this situation, the traditional IO expansion method is usually to increase the input and output capabilities of the system by adding additional MCUs (microcontrollers) or using external expansion chips. However, this method brings new challenges. First, the additional hardware devices not only increase the material cost of the system, but also increase the complexity of the PCB (printed circuit board), making the circuit design more cumbersome. In addition, external expansion devices often require additional power and signal lines, further increasing the system's footprint and making the system layout more difficult.

[0005] Therefore, an efficient, low-cost and easy-to-implement IO port expansion solution is needed. Summary of the invention

[0006] Based on this, it is necessary to provide a system and method for expanding the number of IO ports based on a 3-8 decoder to address the above technical problems.

[0007] In the first aspect, the present invention provides a system for expanding the number of IO ports based on a 3-8 decoder, comprising a microcontroller IO interface, an enable module, an output module, a filter capacitor, a status indication module and a current limiting resistor; wherein the 1st, 2nd and 3rd pins of the microcontroller IO interface are connected to the input pins of several output modules, the 4th, 5th and 6th pins of the microcontroller IO interface are connected to the input pins of the enable module, the output pins of the enable module are respectively connected to the effective enable pins of several output modules, the output pins of the output module are connected to the input end of the status indication module, the high-level enable pin of the output module is connected to the filter capacitor, and the output end of the status indication module is connected to the current limiting resistor.

[0008] Further, the enabling module includes a 3-8 decoder U1;

[0009] Among them, pin 1 of the 3-8 decoder U1 is connected to pin 4 of the microcontroller IO interface, pin 2 of the 3-8 decoder U1 is connected to pin 5 of the microcontroller IO interface, pin 3 of the 3-8 decoder U1 is connected to pin 6 of the microcontroller IO interface, pin 4 of the 3-8 decoder U1 is connected to pin 5 and grounded, pin 6 of the 3-8 decoder U1 is connected to pin 16 and connected to a +5V signal, and pin 8 of the 3-8 decoder U1 is grounded.

[0010] Furthermore, the microcontroller IO interface is a multiplexed general-purpose input and output pin of the microcontroller that can be individually programmed, and the microcontroller IO interface is used as an address input.

[0011] Further, the output module includes 3-8 decoder U2, 3-8 decoder U3, 3-8 decoder U4, 3-8 decoder U5, 3-8 decoder U6, 3-8 decoder U7, 3-8 decoder U8 and 3-8 decoder U9;

[0012] Among them, 3-8 decoder U2, 3-8 decoder U3, 3-8 decoder U4, 3-8 decoder U5, 3-8 decoder U6, 3-8 decoder U7, 3-8 decoder U8 and 3-8 decoder U9 are kept in parallel, and the pin relationship and connection method are the same;

[0013] The first pin of the microcontroller IO interface is connected to the first pin of the 3-8 decoder U2, 3-8 decoder U3, 3-8 decoder U4, 3-8 decoder U5, 3-8 decoder U6, 3-8 decoder U7, 3-8 decoder U8 and 3-8 decoder U9; the second pin of the microcontroller IO interface is connected to the second pin of the 3-8 decoder U2, 3-8 decoder U3, 3-8 decoder U4, 3-8 decoder U5, 3-8 decoder U6, 3-8 decoder U7, 3-8 decoder U8 and 3-8 decoder U9; the third pin of the microcontroller IO interface is connected to the third pin of the 3-8 decoder U2, 3-8 decoder U3, 3-8 decoder U4, 3-8 decoder U5, 3-8 decoder U6 The 3-8 decoder U6, the 3-8 decoder U7, the 3-8 decoder U8 and the 3-8 decoder U9 are connected to the 3rd pin; the output ends of the filter capacitors are connected to the 16th pin of the 3-8 decoder U2, the 3-8 decoder U3, the 3-8 decoder U4, the 3-8 decoder U5, the 3-8 decoder U6, the 3-8 decoder U7, the 3-8 decoder U8 and the 3-8 decoder U9; the 15th, 14th, 13th, 12th, 11th, 10th, 9th and 7th pins of the 3-8 decoder U1 are connected to the 6th pin of the 3-8 decoder U2, the 3-8 decoder U3, the 3-8 decoder U4, the 3-8 decoder U5, the 3-8 decoder U6, the 3-8 decoder U7, the 3-8 decoder U8 and the 3-8 decoder U9 respectively.

[0014] Further, the filter capacitor includes capacitor C1, capacitor C2, capacitor C3, capacitor C4, capacitor C5, capacitor C6, capacitor C7, capacitor C8 and capacitor C9;

[0015] Among them, capacitor C1, capacitor C2, capacitor C3, capacitor C4, capacitor C5, capacitor C6, capacitor C7, capacitor C8 and capacitor C9 are connected in parallel, and the output end of the parallel structure is connected to a +5V signal.

[0016] Furthermore, the number of the status indication modules, the current limiting resistors and the output modules is the same, and each output module is connected to a status indication module, and the composition structure and position relationship of each status indication module are the same;

[0017] The current limiting resistors include a resistor R1 , a resistor R2 , a resistor R3 , a resistor R4 , a resistor R5 , a resistor R6 , a resistor R7 and a resistor R8 .

[0018] Further, one of the status indication modules includes a light emitting diode HL1, a light emitting diode HL2, a light emitting diode HL3, a light emitting diode HL4, a light emitting diode HL5, a light emitting diode HL6, a light emitting diode HL7 and a light emitting diode HL8;

[0019] Among them, the 15th pin of the 3-8 decoder U2 is connected to one end of the light-emitting diode HL1, the 14th pin of the 3-8 decoder U2 is connected to one end of the light-emitting diode HL2, the 13th pin of the 3-8 decoder U2 is connected to one end of the light-emitting diode HL3, the 12th pin of the 3-8 decoder U2 is connected to one end of the light-emitting diode HL4, the 11th pin of the 3-8 decoder U2 is connected to one end of the light-emitting diode HL5, the 10th pin of the 3-8 decoder U2 is connected to one end of the light-emitting diode HL6, the 9th pin of the 3-8 decoder U2 is connected to one end of the light-emitting diode HL7, and the 7th pin of the 3-8 decoder U2 is connected to one end of the light-emitting diode HL8; the other ends of the light-emitting diodes HL1, HL2, HL3, HL4, HL5, HL6, HL7 and HL8 are all connected to one end of the resistor R1.

[0020] Further, if the microcontroller IO interface is used to perform high-level input conversion to high-level output, the anodes of the light-emitting diodes HL1, HL2, HL3, HL4, HL5, HL6, HL7 and HL8 are connected to the output pin of the 3-8 decoder U2, and the cathodes of the light-emitting diodes HL1, HL2, HL3, HL4, HL5, HL6, HL7 and HL8 are connected to one end of the resistor R1, and the other end of the resistor R1 is grounded.

[0021] Further, if the microcontroller IO interface is used to perform low-level input conversion to high-level output, the cathodes of light-emitting diodes HL1, HL2, HL3, HL4, HL5, HL6, HL7 and HL8 are connected to the output pin of the 3-8 decoder U2, and the anodes of light-emitting diodes HL1, HL2, HL3, HL4, HL5, HL6, HL7 and HL8 are connected to one end of the resistor R1, and the other end of the resistor R1 is connected to the +5V signal.

[0022] In a second aspect, the present invention further provides a method for expanding the number of IO ports based on a 3-8 decoder, the method comprising the following steps:

[0023] S1. Select any six individually programmable multiplexed general-purpose input and output pins of the microcontroller as the microcontroller IO interface, and connect the enable module and the output module respectively;

[0024] S2, connect the output pin of the enable module as the enable signal to the valid enable pin of the output module, so that the output module enters the working state;

[0025] S3, using the microcontroller to send different address signals to the input pins of the output module to control the states of all output pins in the output module;

[0026] S4. Connect the external devices that need to be expanded to the output pins of the output module respectively, use the microcontroller IO interface to control the external devices, and intuitively display the connection status of the external devices through the status indication module connected to the output module.

[0027] The beneficial effects of the present invention are:

[0028] 1. By using the 3-8 decoder as the core component of the enabling module and the output module, compared with other IO port expansion solutions, the system cost can be significantly reduced, which has very high economic benefits; at the same time, the 3-8 decoder is small in size and will not take up too much circuit board space. It is particularly suitable for use in devices with limited space. Its compact design can minimize space occupation during PCB layout, providing more layout space for other important modules.

[0029] 2. Through simple circuit connection and basic programming, the expansion can be completed. Developers do not need to invest a lot of time and energy to design complex hardware circuits or write complex software logic, which greatly reduces the development cycle and is very efficient in design and application. At the same time, it is also highly flexible. According to actual needs, the number of IO ports can be further expanded by cascading multiple 3-8 decoders, which can adapt to the needs of various systems of different sizes. Whether it is a small expansion of a small system or a large system with multiple IO requirements, it can be achieved by flexibly adjusting the number of decoders. In addition, the 3-8 decoder has good compatibility with microcontrollers, sensors, actuators and other modules, and can be widely used in a variety of electronic systems that need to expand IO ports, with extremely high versatility and practicality. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:

[0031] Figure 1 is a principle block diagram of a system for expanding the number of IO ports based on a 3-8 decoder according to an embodiment of the present invention;

[0032] Figure 2 is one of the 6→64 low level effective output principle diagrams according to an embodiment of the present invention;

[0033] Figure 3 This is the second schematic diagram of the 6→64 low-level effective output according to an embodiment of the present invention;

[0034] Figure 4 is one of the 6→64 high level effective output principle diagrams according to an embodiment of the present invention;

[0035] Figure 5 This is the second schematic diagram of the 6→64 high-level effective output according to an embodiment of the present invention;

[0036] Figure 6 is one of the 6→32 high + 32 low output principle diagrams according to an embodiment of the present invention;

[0037] Figure 7 This is the second schematic diagram of the 6→32 high + 32 low output according to an embodiment of the present invention;

[0038] Figure 8 This is one of the 9→128 low-level output principle diagrams according to an embodiment of the present invention;

[0039] Fig. 9 This is the second schematic diagram of the 9→128 low-level output principle according to an embodiment of the present invention;

[0040] Fig.10 This is the third schematic diagram of the 9→128 low-level output principle according to an embodiment of the present invention;

[0041] Fig.11 This is the fourth schematic diagram of the 9→128 low-level output principle according to an embodiment of the present invention;

[0042] Fig.12 The present invention is a flowchart of a method for expanding the number of IO ports based on a 3-8 decoder according to an embodiment of the present invention. DETAILED DESCRIPTION

[0043] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0044] See also Figure 1, provides a system for expanding the number of IO ports based on a 3-8 decoder, including a microcontroller IO interface, an enable module, an output module, a filter capacitor, a status indication module and a current limiting resistor; wherein, the 1st, 2nd and 3rd pins of the microcontroller IO interface are connected to the input pins of several output modules, the 4th, 5th and 6th pins of the microcontroller IO interface are connected to the input pins of the enable module, the output pins of the enable module are respectively connected to the effective enable pins of several output modules, the output pins of the output module are connected to the input end of the status indication module, the high-level enable pin of the output module is connected to the filter capacitor, and the output end of the status indication module is connected to the current limiting resistor.

[0045] In the description of the present invention, Figure 2-Figure 3 As shown ( Figure 2 a, b, and c are respectively Figure 3 a, b, and c are connected, and a complete circuit structure is formed by combining and connecting the upper and lower parts), and the enabling module includes a 3-8 decoder U1;

[0046] Among them, pin 1 of the 3-8 decoder U1 is connected to pin 4 of the microcontroller IO interface, pin 2 of the 3-8 decoder U1 is connected to pin 5 of the microcontroller IO interface, pin 3 of the 3-8 decoder U1 is connected to pin 6 of the microcontroller IO interface, pin 4 of the 3-8 decoder U1 is connected to pin 5 and grounded, pin 6 of the 3-8 decoder U1 is connected to pin 16 and connected to a +5V signal, and pin 8 of the 3-8 decoder U1 is grounded.

[0047] In the description of the present invention, the microcontroller IO interface is a multiplexed general-purpose input and output pin of the microcontroller that can be individually programmed, and the microcontroller IO interface is used as an address input.

[0048] In the description of the present invention, Figure 2-Figure 3 As shown, the output module includes 3-8 decoder U2, 3-8 decoder U3, 3-8 decoder U4, 3-8 decoder U5, 3-8 decoder U6, 3-8 decoder U7, 3-8 decoder U8 and 3-8 decoder U9;

[0049] Among them, 3-8 decoder U2, 3-8 decoder U3, 3-8 decoder U4, 3-8 decoder U5, 3-8 decoder U6, 3-8 decoder U7, 3-8 decoder U8 and 3-8 decoder U9 are kept in parallel, and the pin relationship and connection method are the same;

[0050] The first pin of the microcontroller IO interface is connected to the first pin of the 3-8 decoder U2, 3-8 decoder U3, 3-8 decoder U4, 3-8 decoder U5, 3-8 decoder U6, 3-8 decoder U7, 3-8 decoder U8 and 3-8 decoder U9; the second pin of the microcontroller IO interface is connected to the second pin of the 3-8 decoder U2, 3-8 decoder U3, 3-8 decoder U4, 3-8 decoder U5, 3-8 decoder U6, 3-8 decoder U7, 3-8 decoder U8 and 3-8 decoder U9; the third pin of the microcontroller IO interface is connected to the third pin of the 3-8 decoder U2, 3-8 decoder U3, 3-8 decoder U4, 3-8 decoder U5, 3-8 decoder U6 The 3-8 decoder U6, the 3-8 decoder U7, the 3-8 decoder U8 and the 3-8 decoder U9 are connected to the 3rd pin; the output ends of the filter capacitors are connected to the 16th pin of the 3-8 decoder U2, the 3-8 decoder U3, the 3-8 decoder U4, the 3-8 decoder U5, the 3-8 decoder U6, the 3-8 decoder U7, the 3-8 decoder U8 and the 3-8 decoder U9; the 15th, 14th, 13th, 12th, 11th, 10th, 9th and 7th pins of the 3-8 decoder U1 are connected to the 6th pin of the 3-8 decoder U2, the 3-8 decoder U3, the 3-8 decoder U4, the 3-8 decoder U5, the 3-8 decoder U6, the 3-8 decoder U7, the 3-8 decoder U8 and the 3-8 decoder U9 respectively.

[0051] In the description of the present invention, Figure 2-Figure 3 As shown, the filter capacitor includes capacitor C1, capacitor C2, capacitor C3, capacitor C4, capacitor C5, capacitor C6, capacitor C7, capacitor C8 and capacitor C9;

[0052] Among them, capacitor C1, capacitor C2, capacitor C3, capacitor C4, capacitor C5, capacitor C6, capacitor C7, capacitor C8 and capacitor C9 are connected in parallel, and the output end of the parallel structure is connected to a +5V signal.

[0053] In the description of the present invention, the number of status indication modules, current limiting resistors and output modules is the same, and each output module is connected to a status indication module, and the composition structure and position relationship of each status indication module are the same;

[0054] The current limiting resistors include a resistor R1 , a resistor R2 , a resistor R3 , a resistor R4 , a resistor R5 , a resistor R6 , a resistor R7 and a resistor R8 .

[0055] In the description of the present invention, Figure 2-Figure 3 As shown, one of the status indication modules includes a light emitting diode HL1, a light emitting diode HL2, a light emitting diode HL3, a light emitting diode HL4, a light emitting diode HL5, a light emitting diode HL6, a light emitting diode HL7 and a light emitting diode HL8;

[0056] Among them, the 15th pin of the 3-8 decoder U2 is connected to one end of the light-emitting diode HL1, the 14th pin of the 3-8 decoder U2 is connected to one end of the light-emitting diode HL2, the 13th pin of the 3-8 decoder U2 is connected to one end of the light-emitting diode HL3, the 12th pin of the 3-8 decoder U2 is connected to one end of the light-emitting diode HL4, the 11th pin of the 3-8 decoder U2 is connected to one end of the light-emitting diode HL5, the 10th pin of the 3-8 decoder U2 is connected to one end of the light-emitting diode HL6, the 9th pin of the 3-8 decoder U2 is connected to one end of the light-emitting diode HL7, and the 7th pin of the 3-8 decoder U2 is connected to one end of the light-emitting diode HL8; the other ends of the light-emitting diodes HL1, HL2, HL3, HL4, HL5, HL6, HL7 and HL8 are all connected to one end of the resistor R1.

[0057] In the description of the present invention, Figure 2-Figure 3 As shown, if the microcontroller IO interface is used to perform a high-level input conversion to a high-level output, the anodes of the light-emitting diodes HL1, HL2, HL3, HL4, HL5, HL6, HL7 and HL8 are connected to the output pin of the 3-8 decoder U2, and the cathodes of the light-emitting diodes HL1, HL2, HL3, HL4, HL5, HL6, HL7 and HL8 are connected to one end of the resistor R1, and the other end of the resistor R1 is grounded.

[0058] In the description of the present invention, Figure 4-Figure 5 As shown ( Figure 4 In the figure, d, e, and f are respectively Figure 5 d, e, and f in the figure are connected, and a complete circuit structure is formed by combining and connecting the upper and lower parts). If the microcontroller IO interface is used to perform a low-level input conversion to a high-level output, the cathodes of the light-emitting diodes HL1, HL2, HL3, HL4, HL5, HL6, HL7, and HL8 are connected to the output pin of the 3-8 decoder U2, and the anodes of the light-emitting diodes HL1, HL2, HL3, HL4, HL5, HL6, HL7, and HL8 are connected to one end of the resistor R1, and the other end of the resistor R1 is connected to the +5V signal.

[0059] See also Fig.12The present invention also provides a method for expanding the number of IO ports based on a 3-8 decoder, the method comprising the following steps:

[0060] S1. Select any six individually programmable multiplexed general-purpose input and output pins of the microcontroller as the microcontroller IO interface, and connect the enable module and the output module respectively;

[0061] S2, connect the output pin of the enable module as the enable signal to the valid enable pin of the output module, so that the output module enters the working state;

[0062] S3, using the microcontroller to send different address signals to the input pins of the output module to control the states of all output pins in the output module;

[0063] S4. Connect the external devices that need to be expanded to the output pins of the output module respectively, use the microcontroller IO interface to control the external devices, and intuitively display the connection status of the external devices through the status indication module connected to the output module.

[0064] Embodiment 1

[0065] The specific connection method of the present invention is as follows Figure 2-Figure 3 . Connect any 6 individually programmable multiplexed general-purpose input / output (GPIO) pins of the microcontroller to the address input terminals A0-A2 of U1-U9. The output pins (Y0-Y7) of U1 (74HC138) are used as a low-level enable signal and connected to the low-level active enable terminals (CS2 / CS3) of the output modules U2-U9 (74HC138) to make any of them in working state.

[0066] The power supply and GND pins of U1~U9 use +5V power supply and are filtered by C1~C9 filter capacitors. The high-level enable terminal CS1 of U1~U9 is directly connected to the +5V filtered by capacitors C1~C9. The low-level enable terminals CS2 and CS3 of U1 are directly connected to GND. The low-level enable terminal CS3 of U2~U9 is directly connected to GND, and CS2 is connected to the output pin (Y0~Y7) of the enable module U1. All output pins of the output modules U2~U9 are connected to the negative poles of HL1~HL64, and the positive poles are connected to +5V after passing through current limiting resistors R1~R8.

[0067] The implementation principle of the present invention is to use the microcontroller IO interface 4-6 as the address input, control the output pin of the enable module as a low-level enable signal, and enable a certain decoder of the output module. The microcontroller IO interface 1-3 is used as the address input to control a certain enabled decoder of the output module, and which specific output pin performs a low-level effective output. The microcontroller IO interface 1-6 is used as the address input as a whole, and is configured as a binary 6-bit to control the conversion of the number of IO ports with 64-bit low-level effective outputs, completing the expansion of the IO port 6 to 64 low-level outputs.

[0068] In this embodiment, regarding the method for expanding the capacity from 6 to 64 low-level effective outputs, the corresponding truth tables are shown in Tables 1 to 3.

[0069] Table 1: Output module input pin control truth table

[0070]

[0071] Table 2: Enable module pin control truth table

[0072]

[0073] Table 3: Output module pin output control truth table

[0074]

[0075] As can be seen from the above, Tables 1-3 only select one of the output modules, namely the control truth table of the 3-8 decoder U2. Different control methods need to be used for different 3-8 decoders to make them work normally, but the pin output status of the output module is the same.

[0076] Embodiment 2

[0077] In many application scenarios, the external devices or execution units that need to be controlled are not only controlled by low level. Therefore, the present invention proposes a method that can expand the capacity from 6 IO ports to 64 IO ports that can output low level. The hardware part is as follows Figure 4-Figure 5 shown.

[0078] The specific connection method is as follows Figure 4-Figure 5. Connect any 6 individually programmable multiplexed general-purpose input / output (GPIO) pins of the microcontroller to the address input terminals A0~A2 of U1-U9. The output pins (Y0~Y7) of U1 (74HC238) are used as a high-level enable signal and connected to the high-level effective enable terminal (E3) of the output modules U2~U9 (74HC238) to make any of them in working state. The power supply and GND pins of U1~U9 use +5V power supply and are filtered by C1~C9 filter capacitors. The high-level enable terminal E3 of U1~U9 is directly connected to the +5V filtered by capacitors C1~C9. The low-level enable terminals E1 and E2 of U1 are directly connected to GND. The low-level enable terminals E1 and E2 of U2~U9 are directly connected to GND, and E3 is connected to the output pins (Y0~Y7) of the enable module U1. All output pins of output modules U2 to U9 are connected to the positive poles of HL1 to HL64, and the negative poles are connected to GND after passing through current limiting resistors R1 to R8.

[0079] The implementation principle is to use the microcontroller IO interface 4 to 6 as the address input, control the output pin of the enable module as a high-level enable signal, and enable a certain decoder of the output module. The microcontroller IO interface 1 to 3 is used as the address input to control a certain enabled decoder of the output module, and which specific output pin performs high-level effective output. The overall microcontroller IO interface 1 to 6 is used as the address input, and is configured as a binary 6-bit to control the conversion of the number of IO ports with 64-bit high-level effective outputs, completing the expansion of IO port 6 to 64 high-level outputs.

[0080] In the extended use method of the invention, regarding the expansion of 6 to 64 bits of high-level valid output, the corresponding truth tables are shown in Table 4, Table 5 and Table 6.

[0081] Table 4: Output module input pin control truth table

[0082]

[0083]

[0084] Table 5: Enable module pin control truth table

[0085]

[0086] Table 6: Output module pin output control truth table

[0087]

[0088] As can be seen from the above, Tables 4 to 6 only select one of the output modules, namely the control truth table of the 3-8 decoder U2. Different control methods need to be used for different 3-8 decoders to make them work normally, but the pin output status of the output module is the same.

[0089] According to the first and second embodiments, the high-level output circuit structure and the low-level output circuit structure in the present invention are two independent circuits, which can realize the high / low-level output after expansion. However, the present invention is not limited to this. If you want to have both high-level output and low-level output in a control system, you can add the two independent circuits mentioned in the present invention to the entire control system together, or you can choose to arbitrarily piece together the decoder models and quantities of the output modules in the two independent circuits mentioned in the present invention to achieve the effect of high-level + low-level comprehensive output. As shown in the third and fourth embodiments.

[0090] Embodiment 3

[0091] like Figure 6-Figure 7 As shown ( Figure 6 In which g, h, and i are respectively Figure 7 The g, h, and i in the figure are connected, and a complete circuit structure is formed by combining the upper and lower parts). The decoder models and quantities of the output modules can be arbitrarily pieced together to achieve the effect of converting the microcontroller's 6 IO interfaces to 8 high + 56 low, 16 high + 48 low, 24 high + 40 low, 40 high + 24 low, 48 high + 16 low, and 56 high + 8 low outputs.

[0092] In order to further improve the linkage controllability of more complex systems, the increase in the number of expansion interfaces is not limited to 64 interfaces, and a larger number of expansions can also be achieved.

[0093] Embodiment 4

[0094] like Figure 8-Figure 11 As shown ( Figure 8 In which j, k, and l are respectively Fig.10 The j, k, and l connections in Figure 8 Where p, q, and u are Fig. 9 The p, q, and u connections in Fig. 9 In which m, n, and o are Fig.11 The m, n, and o in the circuit are connected to form a complete circuit structure through the combination of the four parts). By adding a microcontroller IO interface as an address input and increasing the number of enable modules and output module decoders, the capacity expansion effect from 12 to 192, 15 to 256, etc. can also be achieved.

[0095] The present invention proposes a system and method for expanding the number of IO ports based on a 3-8 decoder, and provides multiple use methods of the present invention through two examples, so that the present invention has certain versatility, practicality and diversity. The present invention realizes the expansion of IO ports by multiple levels through hardware construction and coordination with the controller, increases the wider applicability of the DSP control system, and increases the flexibility of component use.

[0096] To sum up, with the help of the above technical scheme of the present invention, by adopting the 3-8 decoder as the core component of the enabling module and the output module, compared with other IO port expansion schemes, the system cost can be significantly reduced, and it has very high economic benefits; at the same time, the 3-8 decoder is small in size and will not take up too much circuit board space. It is particularly suitable for use in devices with limited space. Its compact design can minimize space occupancy during PCB layout, providing more layout space for other important modules.

[0097] The expansion can be completed through simple circuit connection and basic programming. Developers do not need to invest a lot of time and energy to design complex hardware circuits or write complex software logic, which greatly reduces the development cycle and is very efficient in design and application. At the same time, it is highly flexible and can further expand the number of IO ports by cascading multiple 3-8 decoders according to actual needs. It can adapt to system requirements of various sizes. Whether it is a small amount of expansion of a small system or a large system with multiple IO requirements, it can be achieved by flexibly adjusting the number of decoders. In addition, the 3-8 decoder has good compatibility with microcontrollers, sensors, actuators and other modules, and can be widely used in a variety of electronic systems that require expanded IO ports, with extremely high versatility and practicality.

[0098] It should be understood that, although the steps in the flowchart of the accompanying drawings are displayed in sequence as indicated by the arrows, these steps are not necessarily executed in sequence in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least a part of the steps in the flowchart of the accompanying drawings may include multiple sub-steps or multiple stages, and these sub-steps or stages are not necessarily executed at the same time, but can be executed at different times, and their execution order is not necessarily sequential, but can be executed in turn or alternately with other steps or at least a part of the sub-steps or stages of other steps.

Claims

1. A system based on 3-8 decoder to expand the number of IO ports, It is characterized in that It includes a microcontroller IO interface, an enabling module, an output module, a filter capacitor, a status indication module and a current limiting resistor; Among them, the 1st, 2nd and 3rd pins of the microcontroller IO interface are connected to the input pins of several output modules, the 4th, 5th and 6th pins of the microcontroller IO interface are connected to the input pins of the enable module, the output pins of the enable module are respectively connected to the effective enable pins of several output modules, the output pins of the output module are connected to the input end of the status indication module, the high level enable pin of the output module is connected to the filter capacitor, and the output end of the status indication module is connected to the current limiting resistor.

2. A system based on 3-8 decoder to expand the number of IO ports according to claim 1, It is characterized in that The enabling module includes a 3-8 decoder U1; Among them, the 1st pin of the 3-8 decoder U1 is connected to the 4th pin of the microcontroller IO interface, the 2nd pin of the 3-8 decoder U1 is connected to the 5th pin of the microcontroller IO interface, the 3rd pin of the 3-8 decoder U1 is connected to the 6th pin of the microcontroller IO interface, the 4th pin of the 3-8 decoder U1 is connected to the 5th pin and grounded, the 6th pin of the 3-8 decoder U1 is connected to the 16th pin and connected to the +5V signal, and the 8th pin of the 3-8 decoder U1 is grounded.

3. A system based on 3-8 decoder to expand the number of IO ports according to claim 1, It is characterized in that The microcontroller IO interface is a multiplexed general-purpose input and output pin of the microcontroller that can be individually programmed, and the microcontroller IO interface is used as an address input.

4. A system for expanding the number of IO ports based on 3-8 decoders according to claim 2, It is characterized in that The output module includes 3-8 decoder U2, 3-8 decoder U3, 3-8 decoder U4, 3-8 decoder U5, 3-8 decoder U6, 3-8 decoder U7, 3-8 decoder U8 and 3-8 decoder U9; Among them, the 3-8 decoder U2, the 3-8 decoder U3, the 3-8 decoder U4, the 3-8 decoder U5, the 3-8 decoder U6, the 3-8 decoder U7, the 3-8 decoder U8 and the 3-8 decoder U9 are kept in parallel, and the pin relationship and connection method are the same; The first pins of the microcontroller IO interface are all connected to the first pins of the 3-8 decoder U2, the 3-8 decoder U3, the 3-8 decoder U4, the 3-8 decoder U5, the 3-8 decoder U6, the 3-8 decoder U7, the 3-8 decoder U8 and the 3-8 decoder U9; the second pins of the microcontroller IO interface are all connected to the 3-8 decoder U2, the 3-8 decoder U3, the 3-8 decoder U4, the 3-8 decoder U5, the 3-8 decoder U6, the 3-8 decoder U7, the 3-8 decoder U8 and the 3-8 decoder U9; The third pins of the microcontroller IO interface are all connected to the third pins of the 3-8 decoder U2, the 3-8 decoder U3, the 3-8 decoder U4, the 3-8 decoder U5, the 3-8 decoder U6, the 3-8 decoder U7, the 3-8 decoder U8 and the 3-8 decoder U9; The output ends of the filter capacitors are all connected to the 16th pins of the 3-8 decoder U2, the 3-8 decoder U3, the 3-8 decoder U4, the 3-8 decoder U5, the 3-8 decoder U6, the 3-8 decoder U7, the 3-8 decoder U8 and the 3-8 decoder U9; The 15th, 14th, 13th, 12th, 11th, 10th, 9th and 7th pins of the 3-8 decoder U1 are respectively connected to the 6th pin of the 3-8 decoder U2, the 3-8 decoder U3, the 3-8 decoder U4, the 3-8 decoder U5, the 3-8 decoder U6, the 3-8 decoder U7, the 3-8 decoder U8 and the 3-8 decoder U9.

5. A system based on 3-8 decoder to expand the number of IO ports according to claim 2, It is characterized in that The filter capacitors include capacitor C1, capacitor C2, capacitor C3, capacitor C4, capacitor C5, capacitor C6, capacitor C7, capacitor C8 and capacitor C9; The capacitor C1, the capacitor C2, the capacitor C3, the capacitor C4, the capacitor C5, the capacitor C6, the capacitor C7, the capacitor C8 and the capacitor C9 are connected in parallel, and the output end of the parallel structure is connected to a +5V signal.

6. A system for expanding the number of IO ports based on 3-8 decoders according to claim 4, It is characterized in that The number of the state indicating modules, the current limiting resistors and the output modules is the same, and each output module is connected to one state indicating module, and the composition structure and position relationship of each state indicating module are the same; The current limiting resistors include a resistor R1, a resistor R2, a resistor R3, a resistor R4, a resistor R5, a resistor R6, a resistor R7 and a resistor R8.

7. A system for expanding the number of IO ports based on 3-8 decoders according to claim 6, It is characterized in that One of the status indication modules includes a light emitting diode HL1, a light emitting diode HL2, a light emitting diode HL3, a light emitting diode HL4, a light emitting diode HL5, a light emitting diode HL6, a light emitting diode HL7 and a light emitting diode HL8; Wherein, the 15th pin of the 3-8 decoder U2 is connected to one end of the light-emitting diode HL1, the 14th pin of the 3-8 decoder U2 is connected to one end of the light-emitting diode HL2, the 13th pin of the 3-8 decoder U2 is connected to one end of the light-emitting diode HL3, the 12th pin of the 3-8 decoder U2 is connected to one end of the light-emitting diode HL4, the 11th pin of the 3-8 decoder U2 is connected to one end of the light-emitting diode HL5, the 10th pin of the 3-8 decoder U2 is connected to one end of the light-emitting diode HL6, the 9th pin of the 3-8 decoder U2 is connected to one end of the light-emitting diode HL7, and the 7th pin of the 3-8 decoder U2 is connected to one end of the light-emitting diode HL8; The other ends of the light emitting diode HL1 , the light emitting diode HL2 , the light emitting diode HL3 , the light emitting diode HL4 , the light emitting diode HL5 , the light emitting diode HL6 , the light emitting diode HL7 and the light emitting diode HL8 are all connected to one end of the resistor R1 .

8. A system for expanding the number of IO ports based on 3-8 decoders according to claim 7, It is characterized in that If the microcontroller IO interface is used to perform high-level input conversion to high-level output, the anodes of the light-emitting diode HL1, the light-emitting diode HL2, the light-emitting diode HL3, the light-emitting diode HL4, the light-emitting diode HL5, the light-emitting diode HL6, the light-emitting diode HL7 and the light-emitting diode HL8 are connected to the output pin of the 3-8 decoder U2, the cathodes of the light-emitting diode HL1, the light-emitting diode HL2, the light-emitting diode HL3, the light-emitting diode HL4, the light-emitting diode HL5, the light-emitting diode HL6, the light-emitting diode HL7 and the light-emitting diode HL8 are connected to one end of the resistor R1, and the other end of the resistor R1 is grounded.

9. A system based on 3-8 decoder to expand the number of IO ports according to claim 7, It is characterized in that If the microcontroller IO interface is used to perform low-level input conversion to high-level output, the cathodes of the light-emitting diodes HL1, HL2, HL3, HL4, HL5, HL6, HL7 and HL8 are connected to the output pin of the 3-8 decoder U2, and the anodes of the light-emitting diodes HL1, HL2, HL3, HL4, HL5, HL6, HL7 and HL8 are connected to one end of the resistor R1, and the other end of the resistor R1 is connected to the +5V signal.

10. A method for expanding the number of IO ports based on a 3-8 decoder, used in a system for expanding the number of IO ports based on a 3-8 decoder according to any one of claims 1 to 9, It is characterized in that The method comprises the following steps: S1. Select any six individually programmable multiplexed general-purpose input and output pins of the microcontroller as the microcontroller IO interface, and connect the enable module and the output module respectively; S2, connecting the output pin of the enabling module as an enabling signal to the effective enabling pin of the output module, so that the output module enters a working state; S3, using the microcontroller to send different address signals to the input pins of the output module to control the states of all output pins in the output module; S4. Connect the external devices that need to be expanded to the output pins of the output module respectively, use the microcontroller IO interface to control the external devices, and intuitively display the connection status of the external devices through the status indication module connected to the output module.

Images