UVM-based ADC sensor controller verification system and method

Abstract

The invention relates to a UVM-based ADC sensor controller verification system and a UVM-based ADC sensor controller verification method, a new UVM verification platform is established based on SystemVerilog language for verification of an ADC sensor controller based on UVM verification methodology, and software implementation, data collection and comparison of the ADC sensor controller are realized. The verification environment ensures random to-be-tested data and random register configuration, thereby ensuring completeness and accuracy of verification of the ADC sensor controller. In addition, the simulation environment is more reliable through the ADC model extracted by the digital-analog hybrid simulation platform. Compared with the prior art, the synchronization of the ADC sensor controller to be tested and the verification environment is realized with low configuration cost, and the verification efficiency is improved.

Description

Technical Field

[0001] The present invention belongs to the technical field of vehicle-regulatory chip verification, and relates to a UVM-based ADC sensor controller verification system and method. Background Art

[0002] With the continuous advancement of automotive electronic technology, modern cars integrate more and more electronic control units (ECUs). These ECUs not only improve vehicle performance and comfort, but also put forward higher requirements for vehicle safety. As the core component of automotive electronic systems, automotive chips must have high reliability and safety. Among them, functional safety has become a key indicator in the design of automotive chips to ensure that the system can operate safely or shut down safely under fault conditions. In automotive electronic systems, ADC (analog-to-digital converter) sensors are an important component. They are mainly used to convert various analog signals (such as voltage, current and temperature) in the vehicle into digital signals for further processing and monitoring. Especially in functional safety design, ADC sensors need to provide not only accurate signal conversion functions, but also be able to monitor system voltage in real time and generate high and low alarm signals when the voltage exceeds the set threshold. This function can prevent potential system failures and improve the safety of vehicle operation.

[0003] In order to ensure the reliability and safety of ADC sensors in complex automotive environments, traditional verification methods rarely fully cover various boundary conditions of the digital control part and cannot meet the increasingly complex verification requirements of automotive chips. How to build a reliable verification platform, accurately simulate the behavior model of the ADC sensor, and ensure the correct logical function of the ADC sensor controller through a large number of stimuli and complete coverage is an urgent problem that verification personnel need to solve. Summary of the invention

[0004] In view of the problems existing in the above-mentioned traditional methods, the present invention proposes an ADC sensor controller verification system based on UVM and an ADC sensor controller verification method based on UVM, builds a complete verification platform with a clear system structure, and can fully verify the basic functions of the ADC sensor controller.

[0005] In order to achieve the above objectives, the embodiments of the present invention adopt the following technical solutions:

[0006] On the one hand, a UVM-based ADC sensor controller verification system is provided, including a top-level simulation file based on UVM verification methodology, which is used to initialize the verification system, start test cases and bind the ADC sensor controller to be tested; the top-level simulation file includes a platform environment created based on a test case base class and an APB system environment component, a register model, an adapter, an ADC slave agent, an ADC sensor agent, an output agent, a reference model, a comparator and an environment configuration file component created based on the platform environment;

[0007] The platform environment is used to provide a verification environment. The APB system environment component is used to simulate the APB bus function and pass the configuration information required by the ADC sensor controller to the ADC sensor controller. The register model is used to deploy all registers of the ADC sensor controller in the platform environment. The adapter is used to convert the register data types in the verification environment and the ADC sensor controller.

[0008] The ADC slave agent is used to simulate the real behavior of the ADC sensor. The ADC slave agent includes the ADC slave driver, ADC slave monitor, ADC slave excitation and ADC slave interface. The ADC slave driver is based on the real behavior of the ADC extracted from the VCS and XA digital-analog hybrid simulation platforms. The ADC sensor agent is used to feed the top-level signal to the ADC sensor controller. The output agent is used to receive the output signal of the ADC sensor controller.

[0009] The reference model is used to simulate the internal logic of the ADC sensor controller and send the generated expected results to the comparator through the TLM. The comparator is used to compare the expected results with the actual results. The environment profile component is used to encapsulate all interfaces in the ADC sensor controller except the APB bus and is instantiated in the platform environment, reference model and comparator.

[0010] On the other hand, a UVM-based ADC sensor controller verification method is also provided, which is applied to the above-mentioned UVM-based ADC sensor controller verification system. The ADC sensor controller verification method comprises the steps of:

[0011] Create test cases for ADC sensor controller;

[0012] Initialize the ADC sensor controller verification system through the top-level simulation file and connect the components in the verification environment;

[0013] While sending the ADC slave data, the reference model uses the configuration information of the ADC sensor controller to anticipate the behavior of the ADC sensor controller and transmits the expected result to the comparator through the TLM port;

[0014] The output agent obtains the actual output data of the ADC sensor controller and transmits it to the comparator through the TLM port;

[0015] The expected result is compared with the actual output data in the comparator to complete the simulation verification of the ADC sensor controller; the result comparison includes real-time comparison of the data returned by the analog ADC stored in the register, interrupt and alarm status, as well as comparison of the number of socs and the number of high and low threshold alarms before the end of the simulation.

[0016] One of the above technical solutions has the following advantages and beneficial effects:

[0017] The above-mentioned UVM-based ADC sensor controller verification system and method builds a new UVM verification platform based on the SystemVerilog language for the verification of the ADC sensor controller based on the UVM verification methodology, and realizes the software implementation, data collection and comparison of the ADC sensor controller. The verification environment ensures random test data and random register configuration, thereby ensuring the completeness and accuracy of the verification of the ADC sensor controller. In addition, the ADC model extracted by the digital-analog hybrid simulation platform makes the simulation environment more reliable.

[0018] Compared with traditional technologies, the above solution verifies the ADC sensor controller by simulating the ADC sensor behavior, which improves the flexibility of verification, realizes the synchronization between the ADC sensor controller to be tested and the verification environment with low configuration cost, and improves the efficiency of verification; at the same time, the high degree of freedom of configuration options also improves the randomness of verification, making the verification more complete. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0020] Figure 1 A schematic diagram of a module architecture of an ADC sensor controller verification system based on UVM in one embodiment;

[0021] Figure 2 A schematic diagram of a digital-analog hybrid simulation platform based on VCS and XA in one embodiment;

[0022] Figure 3 A schematic diagram of a verification process of an ADC sensor controller verification system based on UVM in one embodiment;

[0023] Figure 4 A schematic diagram of a workflow of a reference model in an embodiment;

[0024] Figure 5 A schematic diagram of the workflow of a monitor in one embodiment;

[0025] Figure 6 A schematic diagram of a working process of a comparator in one embodiment;

[0026] Figure 7 The figure is a flow chart of a UVM-based ADC sensor controller verification method in one embodiment. DETAILED DESCRIPTION

[0027] In order to make the purpose, technical scheme and advantages of the present invention clearer, the present invention is further described in detail below in conjunction with the accompanying drawings and Examples. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those generally understood by those skilled in the art of the present invention. The terms used in the specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention.

[0028] It should be noted that the reference to "embodiment" in this article means that the specific features, structures or characteristics described in conjunction with the embodiment may be included in at least one embodiment of the present invention. The presentation of this phrase at various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It will be appreciated by those skilled in the art that the embodiments described herein may be combined with other embodiments. The term "and / or" used in the specification of the present invention and the appended claims refers to any combination of one or more of the associated listed items and all possible combinations, and includes these combinations.

[0029] The following will describe the implementation of the present invention in detail with reference to the accompanying drawings in the embodiment diagram of the present invention.

[0030] First, it should be briefly explained that the key feature of UVM verification methodology is reusable components and standardized hierarchical structure on the one hand, and its SystemVerilog class library on the other hand. About the component functions and effects in UVM verification methodology: the structure of UVM workbench comprises three parts such as top-level (simulation) file testbench, interface layer interface and part to be tested DUT from top to bottom, wherein, interface is used to connect top-level file and DUT, and DUT can be all kinds of products that need test verification, such as module to be tested in the present invention, i.e. ADC sensor controller (adcsensorctrl). Mainly relate to improvement in the present invention is to construct a more practical ADC sensor model in conjunction with digital-analog hybrid simulation platform, build an ADC sensor controller verification system (platform) based on UVM.

[0031] In one embodiment, Figure 1 As shown, a UVM-based ADC sensor controller verification system is provided, including a top-level simulation file based on UVM verification methodology, which is used to initialize the verification system, start the test case and bind the ADC sensor controller to be tested; the top-level simulation file includes a platform environment created based on the test case base class and an APB system environment component, a register model, an adapter, an ADC slave agent, an ADC sensor agent, an output agent, a reference model, a comparator and an environment configuration file component created based on the platform environment. The platform environment is used to provide a verification environment, and the APB system environment component is used to simulate the APB bus function and pass the configuration information required by the ADC sensor controller to the ADC sensor controller. The register model is used to deploy all registers of the ADC sensor controller in the platform environment, and the adapter is used to convert the register data types in the verification environment and the ADC sensor controller.

[0032] The ADC slave agent is used to simulate the real behavior of the ADC sensor. The ADC slave agent includes the ADC slave driver, ADC slave monitor, ADC slave excitation and ADC slave interface. The ADC slave driver is based on the real behavior of the ADC extracted from the VCS and XA digital-analog hybrid simulation platform. The ADC sensor agent is used to input the top-level signal to the ADC sensor controller, and the output agent is used to receive the output signal of the ADC sensor controller. The reference model is used to simulate the internal logic of the ADC sensor controller and send the expected expected result to the comparator through the TLM. The comparator is used to compare the expected result with the actual result. The environment profile component is used to encapsulate all interfaces in the ADC sensor controller except the APB bus, and is instantiated in the platform environment, reference model and comparator.

[0033] It can be understood that in the system of the present embodiment, the top-level simulation file based on UVM verification methodology is used to initialize the verification system testbench (top-level file) and start the test case and bind (binding) DUT module, asserting DUT important signals. The platform environment (adcsensor env) created based on the test case base class (base test) is included in the top-level simulation file, and the test case base class is also used to declare environment variables, configuration information, and create the mounting conditions of various use cases, and do the final check before the simulation ends.

[0034] In the system, an Advanced Peripheral Bus (APB) system environment component (apb system env) is created based on the platform environment (adcsensor env). The APB system environment component includes the component system environment configuration apb_sys_cfg and a complete set of APB hosts, which are used to implement the simulated APB bus function and pass the configuration information required by the ADC sensor controller to the ADC sensor controller.

[0035] A register model (reg model) and an adapter (adapter) are created based on the platform environment (adcsensor env). The register model is used to deploy all registers of the ADC sensor controller through the APB component (such as the APB bus) in the platform environment; the adapter is responsible for converting the register data types in the verification environment and the ADC sensor controller to facilitate data intercommunication.

[0036] Based on the platform environment (adcsensor env), three agent components, namely, ADC slave agent (adc_slave_agent), ADC sensor agent adcsensor_agent and output agent (output_agent), are created. Among them, the ADC slave agent contains ADC slave driver (adc slave driver), ADC slave monitor (adc slave monitor), ADC slave stimulus (adc slave sequencer) and ADC slave interface (adc slave if) to simulate the real behavior of the ADC sensor. Among them, the ADC slave driver is based on the digital-analog hybrid simulation platform (such as VCS (a digital circuit simulation tool provided by Synopsys for verifying digital design) and XA (HSPICE XA provided by Synopsys, which is a mixed-signal (digital and analog) simulation tool specially used for analog simulation of high-performance and complex systems) Figure 2As shown, eoc (End of Converter) is used to indicate the end indication signal of the ADC transmission process, data represents data information, and soc (start of Converter) represents the start signal of ADC transmission, which extracts the real behavior of ADC. Specifically, by simulating on the VCS and XA digital-analog hybrid simulation platform, the real behavior of ADC sensor is simulated and extracted. This process includes realistic simulation of the analog part of the ADC sensor to obtain the real conversion characteristics, accuracy and delay of the ADC sensor. These extracted behaviors can be used to create an accurate ADC model, which can be used in subsequent digital simulation environments for higher-level system verification. In addition, the ADC sensor agent is used to infuse the top-level signal into the DUT, and the output agent is used to receive the output signal of the DUT.

[0037] A reference model (RFM) and a comparator (SCB) are created based on the platform environment (adcsensor env). The reference model is used to simulate the internal logic of the ADC sensor controller and generate the expected expected results to the comparator (SCB) through TLM (Transaction-Level Modeling) to compare the expected results with the actual results of the DUT output.

[0038] Based on the platform environment (adcsensor env), an environment configuration file component (env_cfg) is created. This component is mainly used to encapsulate all interfaces in the ADC sensor controller except the APB bus. It is instantiated in the platform environment, reference model and comparator. The main functions of the environment configuration file component are as follows: 1. It can conveniently drive each interface in a virtual sequence, so that each interface can be decoupled and combined randomly; 2. It is convenient to synchronize the excitation of each interface between the reference model and the DUT, and simplifies the code of the UVM verification platform without destroying the modularity of the UVM verification platform.

[0039] The above-mentioned UVM-based ADC sensor controller verification system builds a new UVM verification platform based on the SystemVerilog language for the verification of the ADC sensor controller based on the UVM verification methodology, realizing the software implementation, data collection and comparison of the ADC sensor controller. The verification environment ensures random test data and random register configuration, thereby ensuring the completeness and accuracy of the ADC sensor controller verification. In addition, the ADC model extracted by the digital-analog hybrid simulation platform makes the simulation environment more reliable.

[0040] Compared with traditional technologies, the above solution verifies the ADC sensor controller by simulating the ADC sensor behavior, which improves the flexibility of verification, realizes the synchronization between the ADC sensor controller to be tested and the verification environment with low configuration cost, and improves the efficiency of verification; at the same time, the high degree of freedom of configuration options also improves the randomness of verification, making the verification more complete.

[0041] It should be noted that the above-mentioned UVM-based ADC sensor controller verification system includes a top-level simulation file (TB), a platform environment (adcsensor env) and an ADC sensor controller to be tested (i.e., DUT), and the interface bus connecting the ADC sensor controller to be tested and the platform environment can be represented by an arrow. Register model (regmodel) and adapter (adapter), APB bus access verification environment simulates the behavior model of ADC sensor (i.e., ADC slave agent adc slave agent), and uses a virtual scheduler (i.e., virtual sequencer, for coordinating multiple sequencers (sequencers) or driving multiple parallel sequences (sequences), so that the entire UVM verification platform can more effectively perform multi-level, complex transaction-driven simulation) in vseq (i.e., virtual sequence (virtual sequence), which is a high-level sequence, used to coordinate the operation between multiple subsequences or multiple agents (agents)) to schedule the operation of the platform. The register function is configured through the register model of the virtual scheduler; the simulated return data is infused through the ADC slave virtual sequence (adc slavevseq); the ADC sensor controller agent (adcsensor ctrl agent) encapsulates the ADC sensor controller module-level input; the output agent (output_agent) encapsulates the module-level output signal; the interface is encapsulated together in the environment configuration file component (env_cfg) for easy calling.

[0042] Connect the components in the verification environment, and transmit the data of each component in the verification environment through TLM ports. Each component interacts with the actual data and expected data through ports and export ports (port types used for inter-module communication, which help different components (such as sequencer, driver and monitor) to transfer data and synchronization signals).

[0043] In one embodiment, the above-mentioned UVM-based ADC sensor controller verification system also includes a coverage component for configuring all channel selections and working modes of the ADC sensor controller; the working mode includes whether to turn on the soc width configuration, whether to configure the polling interval, whether to terminate under infinite polling conditions, simulate the ADC's working clock configuration, two interrupt mode configurations, and whether to bypass the path.

[0044] It can be understood that the coverage component (cov) can also be set for all channel selections and working modes of the ADC sensor controller. Full coverage requires that all channels of the ADC sensor can work normally in polling and single modes; it is optional to enable the soc width configuration, configure the polling interval, terminate (stop) under infinite polling conditions, simulate the ADC working clock configuration, configure two interrupt modes, and bypass the path, etc.

[0045] Create a test case for the ADC sensor controller. When selecting the test function, different functions can be implemented by changing the register configuration. For example, if the ADC sensor channel needs to be configured to work in the polling state, and the high and low thresholds are configurable, the polling ends and the interrupt is generated, and the polling interval is configurable, the test case that inherits the test case base class mounts the ADC slave (adcslave) seq on the corresponding sequencer through start, that is, in the UVM verification environment, the test case mounts the ADC slave sequence (sequence) on the corresponding sequencer by calling the start() method, thereby starting the execution of the sequence to simulate the operation of the ADC slave. In the fork join any process block (a statement block used to execute multiple threads in parallel in SystemVerilog), a random trigger signal is issued at the same time, that is, in multiple threads executed in parallel, each thread can issue a random trigger signal (trigger signal) at any time, and then the program performs corresponding operations based on the triggering of these signals.

[0046] Afterwards Figure 3 As shown in the figure, the platform starts running. While sending the ADC slave data (i.e., the control signal and return data of the ADC sensor), the configuration information of the DUT is obtained in the reference model to predict the behavior, and the data is transmitted to the comparator (scb, also known as the scoreboard) through the TLM port (as shown in the figure). Figure 4 The output agent (output_agent) gets the actual output data of the DUT and transmits it to the comparator (scb) through the TLM port (as shown in Figure 5As shown, int represents integer data, and post_main_phase is the stage after the main operation stage (main phase) in the UVM verification stage). In the comparator (scb), the data returned by the analog ADC stored in the register, the interrupt and the alarm status are compared in real time, and the number of socs and the number of high and low threshold alarms are compared before the end of the simulation.

[0047] In one embodiment, if the configuration selected by the test case is to configure the high and low thresholds of the ADC sensor through the external Flash interface and the configuration of the high and low thresholds is invalid, the reference model obtains the value configuration of the Flash for prediction.

[0048] It can be understood that if the configuration selected in the test case is to configure the high and low thresholds of the ADC sensor through the external Flash interface and lock the internal registers of the module (configuration of high and low thresholds is invalid), the reference model (rfm) gets the value of the flash interface configuration (through Figure 1 The flash interface in the adc global agent is configured to the ADC sensor controller, and the data is sent to the reference model for expected configuration. The workflow is as follows Figure 4 As shown in the figure, “od alarm” and “ud alarm” represent two types of alarm signals, which are usually used to monitor some abnormal situations in the system.

[0049] In one embodiment, if the working mode selected by the test case is the bypass mode, due to the particularity of this mode (such as the control signal of the ADC sensor is not given through the register configuration, but the data is given through the chip pad port of the DUT), the control signal is configured through the chip pad port of the DUT in the verification environment, and the correctness comparison is performed on the input and output of the ADC sensor controller in the comparator (scb), such as Figure 6 described.

[0050] In one embodiment, the UVM-based ADC sensor controller verification system further includes a makefile file for connecting a file list of the ADC sensor controller and a file list of the verification environment, and adding compilation macros and coverage collection items.

[0051] It can be understood that you can also write a makefile file (write an automated build script for building and managing the project compilation process), select the compilation tool, connect the file list (filelist) of the ADC sensor controller and the file list (filelist) of the verification environment, add compilation macros and coverage collection items, etc. Through the makefile file, you can also realize the automatic running of the test case for a specified number of times.

[0052] The above components are constructed using SystemVerilog language and follow the UVM verification methodology. They can be constructed using components in the UVM verification methodology according to the test interaction functions they need to provide.

[0053] Each module in the above-mentioned UVM-based ADC sensor controller verification system can be implemented in whole or in part by software, hardware and a combination thereof. Each of the above-mentioned modules can be embedded in or independent of a device having a data processing function in the form of hardware, or can be stored in the memory of the aforementioned device in the form of software, so that the processor can call and execute the operations corresponding to each of the above modules. The aforementioned device can be, but is not limited to, various types of verification computer devices already available in the art.

[0054] In one embodiment, Figure 7 As shown, a UVM-based ADC sensor controller verification method is provided, which is applied to the above-mentioned UVM-based ADC sensor controller verification system. The ADC sensor controller verification method may include the following processing steps S10 to S18:

[0055] S10, creating a test case for the ADC sensor controller;

[0056] S12, initializing the ADC sensor controller verification system through the top-level simulation file, and connecting the components in the verification environment;

[0057] S14, while sending the ADC slave data, the reference model uses the configuration information of the ADC sensor controller to anticipate the behavior of the ADC sensor controller and then transmits the expected result to the comparator through the TLM port;

[0058] S16, the output agent obtains the actual output data of the ADC sensor controller and transmits it to the comparator through the TLM port;

[0059] S18, compare the expected result with the actual output data in the comparator to complete the simulation verification of the ADC sensor controller; the result comparison includes real-time comparison of the data returned by the analog ADC stored in the register, interrupt and alarm status, as well as comparison of the number of socs and the number of high and low threshold alarms before the end of the simulation.

[0060] The above-mentioned UVM-based ADC sensor controller verification method builds a new UVM verification platform based on the SystemVerilog language for the verification of the ADC sensor controller based on the UVM verification methodology, and realizes the software implementation, data collection and comparison of the ADC sensor controller. The verification environment ensures random test data and random register configuration, thereby ensuring the completeness and accuracy of the ADC sensor controller verification. In addition, the ADC model extracted by the digital-analog hybrid simulation platform makes the simulation environment more reliable.

[0061] Compared with traditional technologies, the above solution verifies the ADC sensor controller by simulating the ADC sensor behavior, which improves the flexibility of verification, realizes the synchronization between the ADC sensor controller to be tested and the verification environment with low configuration cost, and improves the efficiency of verification; at the same time, the high degree of freedom of configuration options also improves the randomness of verification, making the verification more complete.

[0062] In one embodiment, the above-mentioned UVM-based ADC sensor controller verification method further includes the steps of:

[0063] If the working mode selected by the test case is bypass mode, the control signal is configured through the chip pad port of the ADC sensor controller in the verification environment, and the correctness of the input and output of the ADC sensor controller is compared in the comparator.

[0064] It can be understood that for the specific limitations of the UVM-based ADC sensor controller verification method, reference can be made to the corresponding limitations of the UVM-based ADC sensor controller verification system described above, which will not be repeated here.

[0065] It should be understood that although Figure 7 The steps in the method are shown in sequence as indicated by the arrows, but the steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of the steps, and the steps can be executed in other orders. Figure 7 At least part of the steps may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily executed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequentially, but can be executed in turn or alternately with other steps or at least part of the sub-steps or stages of other steps.

[0066] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiments can be completed by instructing the relevant hardware through a computer program. The computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to memory, storage, database or other media used in the embodiments provided by the present invention can include non-volatile and / or volatile memory. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM) or flash memory. Volatile memory can include random access memory (RAM) or external cache memory. As an illustration and not limitation, RAM is available in many forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link (Synchlink) DRAM (SLDRAM), memory bus dynamic random access memory (RambusDRAM, referred to as RDRAM) and interface dynamic random access memory (DRDRAM).

[0067] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0068] The above embodiments only express several implementation methods of the present invention, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of protection of the invention. It should be pointed out that, for those of ordinary skill in the art, several modifications and improvements can be made without departing from the concept of the present invention, which all belong to the scope of protection of the present invention. Therefore, the scope of protection of the present invention shall be subject to the attached claims.

Claims

1. A UVM-based ADC sensor controller verification system, characterized in that: Includes top-level simulation files based on UVM verification methodology, which are used to initialize the verification system, start test cases, and bind the ADC sensor controller to be tested; The top-level simulation file includes a platform environment created based on a test case base class and an APB system environment component, a register model, an adapter, an ADC slave agent, an ADC sensor agent, an output agent, a reference model, a comparator, and an environment configuration file component created based on the platform environment; The platform environment is used to provide a verification environment, the APB system environment component is used to simulate the APB bus function, and pass the configuration information required by the ADC sensor controller to the ADC sensor controller; the register model is used to deploy all registers of the ADC sensor controller in the platform environment, and the adapter is used to convert the register data types in the verification environment and the ADC sensor controller; The ADC slave agent is used to simulate the real behavior of the ADC sensor. The ADC slave agent includes an ADC slave driver, an ADC slave monitor, an ADC slave excitation and an ADC slave interface. The ADC slave driver is driven based on the real behavior of the ADC extracted from the digital-analog hybrid simulation platform of VCS and XA. The ADC sensor agent is used to infuse the top-level signal to the ADC sensor controller. The output agent is used to receive the output signal of the ADC sensor controller. The reference model is used to simulate the internal logic of the ADC sensor controller, and generates an expected result and sends it to the comparator through the TLM. The comparator is used to compare the expected result with the actual result. The environment profile component is used to encapsulate all interfaces in the ADC sensor controller except the APB bus, and is instantiated in the platform environment, the reference model and the comparator.

2. The UVM-based ADC sensor controller verification system according to claim 1, characterized in that, It also includes a coverage component for configuring all channel selections and working modes of the ADC sensor controller; the working mode includes whether to turn on the soc width configuration, whether to configure the polling interval, whether to terminate under infinite polling conditions, the working clock configuration of the analog ADC, two interrupt mode configurations, and whether to bypass the path.

3. The ADC sensor controller verification system based on UVM according to claim 1, characterized in that, It also includes a makefile, a list of files for connecting to the ADC sensor controller, and a list of files for the verification environment, as well as adding compilation macros and coverage collection items.

4. The UVM-based ADC sensor controller verification system according to any one of claims 1 to 3, characterized in that: If the configuration selected by the test case is to configure the high and low thresholds of the ADC sensor through the external Flash interface and the configuration of the high and low thresholds is invalid, the reference model obtains the value configuration of the Flash for prediction.

5. A UVM-based ADC sensor controller verification method, characterized in that: Applied to the UVM-based ADC sensor controller verification system according to any one of claims 1 to 4, the ADC sensor controller verification method comprises the steps of: Create test cases for ADC sensor controller; Initialize the ADC sensor controller verification system through the top-level simulation file and connect the components in the verification environment; While sending the ADC slave data, the reference model uses the configuration information of the ADC sensor controller to anticipate the behavior of the ADC sensor controller and transmits the expected result to the comparator through the TLM port; The output agent obtains the actual output data of the ADC sensor controller and transmits it to the comparator through the TLM port; A comparison is performed in the comparator between the expected result and the actual output data to complete the simulation verification of the ADC sensor controller; the result comparison includes a real-time comparison of the data returned by the analog ADC stored in the register, the interrupt and the alarm status, as well as a comparison of the number of socs and the number of high and low threshold alarms before the end of the simulation.

6. The UVM-based ADC sensor controller verification method according to claim 5, characterized in that, Also includes the steps: If the working mode selected by the test case is the bypass mode, a control signal is configured through the chip pad port of the ADC sensor controller in the verification environment, and a correctness comparison is performed on the input and output of the ADC sensor controller in the comparator.

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