FPGA prototype verification platform based on RISC-V chip

Abstract

The invention discloses an FPGA prototype verification platform based on an RISC-V chip. The FPGA prototype verification platform comprises the RISC-V chip, an RISC-V processor core is instantiated in FPGA logic resources, and the RISC-V processor core realizes a standard RISC-V instruction set, supports an RV32I / RV64I basic integer instruction set, M standard multiplication and division extension, A atom operation extension and F single precision floating point extension; the off-chip memory is used for providing code and data storage for the RISC-V chip by using FPGA off-chip storage resources; the RISC-V chip is connected with the off-chip memory through the memory controller and the bus interface; the external interface circuit realizes that an I / O interface is externally connected with a sensor and an actuator, and the application range of the RISC-V chip is expanded; the programmable logic circuit constructs various hardware acceleration units according to needs by utilizing programmable logic resources of the FPGA and is interconnected with the RISC-V chip through a standard AXI bus or a custom bus, and the hardware acceleration units cooperate with the RISC-V chip to work, so that the system performance is improved; and the software and hardware collaboration system provides a software development environment and a hardware development suite.

Description

Technical Field

[0001] The present invention relates to a prototype verification system, and in particular to an FPGA prototype verification platform based on a RISC-V chip. Background Art

[0002] RISC-V is an open source instruction set architecture (ISA) that has attracted widespread attention from academia and industry for its simplicity, modularity, and scalability. More and more RISC-V chips are being designed and put into use. In order to verify the functions and performance of RISC-V chips, it is usually necessary to build a prototype verification platform. Traditional verification platforms are mostly based on ASIC or FPGA, but they have problems such as high cost and long development cycle.

[0003] FPGA is very suitable for building prototype verification systems due to its programmable and flexible features. Transplanting RISC-V chips to the FPGA platform can significantly reduce verification costs and shorten development cycles. In addition, FPGA can also provide rich hardware resources such as DSP, BRAM, etc. Users can flexibly build custom circuits according to their needs, thereby expanding the functions of RISC-V chips and optimizing system performance. Summary of the invention

[0004] The purpose of the present invention is to provide an FPGA prototype verification platform based on a RISC-V chip to overcome the limitations of existing verification platforms.

[0005] The technical solution of the present invention is: A RISC-V chip-based FPGA prototype verification platform, including: RISC-V chip, instantiates the RISC-V processor core in the FPGA logic resources. The RISC-V processor core implements the standard RISC-V instruction set, supports the RV32I / RV64I basic integer instruction set, M standard multiplication and division extension, A atomic operation extension, and F single-precision floating point extension; Off-chip memory: Use FPGA off-chip storage resources to provide code and data storage for RISC-V chips; connect RISC-V chips to off-chip memory through storage controllers and bus interfaces; The peripheral interface circuit realizes the I / O interface to connect external sensors and actuators, expanding the application scope of the RISC-V chip; Programmable logic circuits use the programmable logic resources of FPGA to build various hardware acceleration units as needed, which are interconnected with RISC-V chips through standard AXI buses or custom buses. The hardware acceleration units work in conjunction with RISC-V chips to improve system performance. The software and hardware collaborative system provides software development environment and hardware development kit.

[0006] Preferably, the software-hardware collaborative system, in terms of software, transplants RISC-V's standard compilation tool chain, operating system and common libraries, and supports C / C++ development; in terms of hardware, provides reference designs and IP cores, based on which users can quickly build and customize the system.

[0007] Preferably, the peripheral interface circuit also supports PCIe to meet high-bandwidth data transmission requirements.

[0008] Preferably, the RISC-V processor core also supports custom instruction set extensions to meet different application requirements.

[0009] Preferably, the platform is based on FPGA devices, uses HDL to instantiate RISC-V processor cores, off-chip memory controllers, peripheral interface controllers, and user-defined acceleration units in programmable logic, and uses FPGA tools to complete synthesis, layout and routing, and generate bitstream files.

[0010] Preferably, after the bitstream file is generated, the bitstream file is downloaded to the FPGA device, the RISC-V chip and various modules are built in the FPGA, the startup mode is selected through the device configuration pins, and the system is powered on.

[0011] Preferably, after starting the system, the RISC-V chip reads instructions and data from the off-chip memory and starts executing the program; the program configures and accesses the peripheral interface circuit to achieve interaction with external devices.

[0012] Preferably, for computationally intensive tasks, a customized acceleration unit is built in the programmable logic and interconnected with the RISC-V chip through a bus; the RISC-V chip sends the task data to the acceleration unit for processing, and after the processing is completed, the result is returned to the RISC-V chip, thereby achieving performance improvement.

[0013] Preferably, through hardware-software collaborative design, users can quickly build a prototype system according to application requirements, verify the functions and performance of the RISC-V chip, and evaluate its feasibility in actual scenarios.

[0014] The advantages of the present invention are: 1. The present invention is based on the open source RISC-V architecture, with flexible chip design, avoiding royalty and licensing issues, and reducing the cost of building a verification platform.

[0015] 2. The present invention is implemented using FPGA, which makes full use of the programmable characteristics of FPGA. Users can flexibly configure the number of cores, frequency, cache and other parameters of the RISC-V chip, and can add custom instruction sets to build a personalized verification platform.

[0016] 3. The present invention utilizes programmable logic circuits to achieve hardware acceleration, and fully utilizes the parallel computing capability of FPGA through hardware and software collaboration, thereby improving system performance.

[0017] 4. The present invention provides a complete software and hardware development environment, reduces the development difficulty of users, and shortens the development cycle of the prototype system.

[0018] 5. The present invention can adapt to a variety of RISC-V chips and has wide applicability. It can be used in chip research and development, teaching and scientific research, and other scenarios. DETAILED DESCRIPTION

[0019] The embodiment of the present invention provides an FPGA prototype verification platform based on a RISC-V chip, comprising: RISC-V chip: Instantiates the RISC-V processor core in the FPGA logic resources. The processor core implements the standard RISC-V instruction set, supports the RV32I / RV64I basic integer instruction set, M standard multiplication and division extension, A atomic operation extension, F single-precision floating point extension, etc. It also supports custom instruction set extensions to meet different application requirements.

[0020] Off-chip memory: Use FPGA off-chip memory resources such as DDR, SRAM, etc. to provide code and data storage for RISC-V chips. Through the storage controller and bus interface, the RISC-V chip and the off-chip memory can be efficiently connected.

[0021] Peripheral interface circuit: It realizes commonly used I / O interfaces such as UART, I2C, SPI, etc., and can be connected to various sensors, actuators, etc., to expand the application scope of RISC-V chips. At the same time, the present invention also supports high-speed interfaces such as PCIe, etc., to meet the needs of high-bandwidth data transmission.

[0022] Programmable logic circuit: Using the programmable logic resources of FPGA, users can build various hardware acceleration units according to their needs, such as neural network accelerators, signal processing units, etc., and interconnect them with RISC-V chips through standard AXI buses or custom buses. The hardware acceleration units can work with RISC-V chips to greatly improve system performance.

[0023] The software and hardware collaborative system provides a software development environment and a hardware development kit. In terms of software, the standard compilation tool chain, operating system and common libraries of RISC-V are ported to support C / C++ development; in terms of hardware, reference designs and IP cores are provided, based on which users can quickly build and customize the system.

[0024] The workflow of the present invention is as follows: 1. The platform is based on FPGA devices. It uses HDL to instantiate RISC-V processor cores, off-chip memory controllers, peripheral interface controllers, and user-defined acceleration units in programmable logic, and uses FPGA tools to complete synthesis, layout and routing, and generate bitstream files.

[0025] 2. After the bitstream file is generated, it is downloaded to the FPGA device. The RISC-V chip and various modules are built in the FPGA. The startup mode is selected through the device configuration pins, and the system is powered on.

[0026] 3. After starting the system, the RISC-V chip reads instructions and data from the off-chip memory and starts executing the program; the program configures and accesses the peripheral interface circuit to realize interaction with external devices.

[0027] 4. For computationally intensive tasks, a customized acceleration unit is built in the programmable logic and interconnected with the RISC-V chip through a bus; the RISC-V chip sends the task data to the acceleration unit for processing, and after processing, the results are returned to the RISC-V chip, thereby achieving performance improvement.

[0028] 5. Through software and hardware collaborative design, users can quickly build prototype systems according to application requirements, verify the functions and performance of RISC-V chips, and evaluate their feasibility in actual scenarios.

[0029] The present invention is based on the open source RISC-V architecture, has flexible chip design, avoids royalty and licensing issues, and reduces the cost of building a verification platform.

[0030] The present invention is implemented using FPGA, which makes full use of the programmable characteristics of FPGA. Users can flexibly configure the number of cores, frequency, cache and other parameters of the RISC-V chip, and can add custom instruction sets to build a personalized verification platform.

[0031] The present invention utilizes programmable logic circuits to achieve hardware acceleration, and fully utilizes the parallel computing capability of FPGA through hardware and software collaboration, thereby improving system performance.

[0032] The present invention provides a complete software and hardware development environment, reduces the development difficulty of users, and shortens the development cycle of the prototype system.

[0033] The present invention can adapt to a variety of RISC-V chips and has wide applicability, and can be applied in chip research and development, teaching and scientific research, and other scenarios.

[0034] The above embodiments are only for illustrating the technical concept and features of the present invention, and their purpose is to enable people familiar with the technology to understand the content of the present invention and implement it accordingly, and they cannot be used to limit the protection scope of the present invention. Any modifications made according to the spirit of the main technical solution of the present invention should be included in the protection scope of the present invention.

Claims

1. An FPGA prototype verification platform based on RISC-V chip, It is characterized in that include: RISC-V chip, instantiates the RISC-V processor core in the FPGA logic resources. The RISC-V processor core implements the standard RISC-V instruction set, supports the RV32I / RV64I basic integer instruction set, M standard multiplication and division extension, A atomic operation extension, and F single-precision floating point extension; Off-chip memory: Use FPGA off-chip storage resources to provide code and data storage for RISC-V chips; connect RISC-V chips to off-chip memory through storage controllers and bus interfaces; The peripheral interface circuit realizes the I / O interface to connect external sensors and actuators, expanding the application scope of the RISC-V chip; Programmable logic circuits use the programmable logic resources of FPGA to build various hardware acceleration units as needed, which are interconnected with RISC-V chips through standard AXI buses or custom buses. The hardware acceleration units work with RISC-V chips to improve system performance. The software and hardware collaborative system provides software development environment and hardware development kit.

2. The RISC-V chip-based FPGA prototype verification platform according to claim 1, It is characterized in that The software-hardware collaborative system, in terms of software, transplants RISC-V's standard compilation tool chain, operating system and common libraries, and supports C / C++ development; in terms of hardware, it provides reference designs and IP cores, based on which users can quickly build and customize systems.

3. The RISC-V chip-based FPGA prototype verification platform according to claim 1, It is characterized in that The peripheral interface circuit also supports PCIe to meet the needs of high-bandwidth data transmission.

4. The RISC-V chip-based FPGA prototype verification platform according to claim 1, It is characterized in that The RISC-V processor core also supports custom instruction set extensions to meet different application requirements.

5. The RISC-V chip-based FPGA prototype verification platform according to claim 1, It is characterized in that The platform is based on FPGA devices and uses HDL to instantiate RISC-V processor cores, off-chip memory controllers, peripheral interface controllers, and user-defined acceleration units in programmable logic. It also uses FPGA tools to complete synthesis, layout and routing, and generate bitstream files.

6. The RISC-V chip-based FPGA prototype verification platform according to claim 5, It is characterized in that After the bitstream file is generated, it is downloaded to the FPGA device. The RISC-V chip and various modules are built in the FPGA. The startup mode is selected through the device configuration pins, and the system is powered on.

7. The RISC-V chip-based FPGA prototype verification platform according to claim 6, It is characterized in that After starting the system, the RISC-V chip reads instructions and data from the off-chip memory and starts executing the program; the program configures and accesses the peripheral interface circuit to achieve interaction with external devices.

8. The RISC-V chip-based FPGA prototype verification platform according to claim 7, It is characterized in that For compute-intensive tasks, a customized acceleration unit is built in the programmable logic and interconnected with the RISC-V chip through a bus; the RISC-V chip sends the task data to the acceleration unit for processing, and after processing, the results are returned to the RISC-V chip, thereby achieving performance improvement.

9. The RISC-V chip-based FPGA prototype verification platform according to claim 8, It is characterized in that Through hardware-software collaborative design, users can quickly build prototype systems based on application requirements, verify the functions and performance of RISC-V chips, and evaluate their feasibility in actual scenarios.