Design method, system and medium for improving integrated circuit performance based on transistor level design

Abstract

The present invention discloses a design method, system and medium for improving the performance of integrated circuits based on transistor layer design. The method includes obtaining a first integrated circuit based on EDA design, wherein the first integrated circuit includes a plurality of functional blocks of subcircuits for realizing a target function; determining a target functional block in the first integrated circuit and determining that the input and output ends of the target functional block are respectively electrically connected to the target output and target input; matching the target functional block with an optimized functional block having the same function as the target functional block, and determining the input and output ends of the optimized functional block; deleting the target functional block; electrically connecting the input end of the optimized functional block to the target output end, and electrically connecting the output end of the optimized functional block to the target input end; and obtaining a target integrated circuit that meets the design target according to a second integrated circuit design. The present invention can design an integrated circuit with better performance on the basis of complying with the existing EDA design process.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit design, and in particular to a design method, system and medium for improving integrated circuit performance based on transistor layer design. Background Art

[0002] An Application Specific Integrated Circuit (ASIC) is a special type of carefully designed integrated circuit (IC) that can perform specific functions in electronic systems. Its design process includes: determining product specifications, generating register-transfer level (RTL) files, pre-simulation, circuit synthesis, generating logic gate netlists, placement, routing, and outputting GDS files for Fab tape-out.

[0003] Currently, the design of integrated circuits can be completed through electronic design automation (EDA). Many EDA tools / software based on EDA design have also been developed, electronic design automation has gradually begun to be commercialized, and the design of digital integrated circuits has gradually become modularized. The EDA tools provide generation, optimization, and verification of standard cell layout designs for integrated circuits, while ensuring compliance with standard cell layout design and manufacturing specifications.

[0004] With the rapid development of automation and AI technologies, in terms of integrated circuit design, EDA tools are increasingly relied on to shorten design time and improve design accuracy. However, EDA tools provide designs in a way that is least restricted by process technology or design methods under commercial considerations. Therefore, the possibility of optimizing some designs is also sacrificed.

[0005] The disclosure of the above background technology content is only used to assist in understanding the inventive concept and technical solution of the present invention. It does not necessarily belong to the prior art of the present application, nor does it necessarily provide technical guidance. In the absence of clear evidence that the above content has been disclosed before the filing date of the present application, the above background technology should not be used to evaluate the novelty and creativity of the present application. Summary of the invention

[0006] The purpose of the present invention is to provide a design method, system and medium for improving integrated circuit performance based on transistor level design, which can design integrated circuits with better performance based on existing EDA design processes.

[0007] To achieve the above object, the technical solution adopted by the present invention is as follows:

[0008] A design method for improving integrated circuit performance based on transistor layer design is applied to designing integrated circuits, and the method comprises the following steps:

[0009] According to the design target of the integrated circuit, a first integrated circuit is obtained based on EDA design, wherein the first integrated circuit includes a plurality of functional blocks, and the functional blocks include at least a subcircuit for realizing a target function; this step is usually performed by a processor capable of running an EDA tool;

[0010] In response to one or more of the functional blocks being determined as target functional blocks, the processor determines that the objects to which the input terminal and the output terminal of the target functional block are electrically connected are the target output terminal and the target input terminal respectively;

[0011] Matching a corresponding optimized functional block to the target functional block, wherein the subcircuit included in the optimized functional block has the same function as the subcircuit included in the target functional block, and determining the input and output ends of the optimized functional block;

[0012] Replacing the target functional block in the first integrated circuit with the optimized functional block to obtain a second integrated circuit includes: deleting the target functional block; electrically connecting the input end of the optimized functional block to the target output end, and electrically connecting the output end of the optimized functional block to the target input end;

[0013] A target integrated circuit that meets the design goal is obtained according to the second integrated circuit design.

[0014] Furthermore, any one of the above-mentioned technical solutions or a combination of multiple technical solutions further includes determining the target functional block by:

[0015] In response to one or more of the functional blocks in the first integrated circuit being marked, the marked functional blocks are determined to be the target functional blocks; the functional blocks may be marked manually or automatically.

[0016] Furthermore, any one of the above-mentioned technical solutions or a combination of multiple technical solutions further includes determining the target functional block by:

[0017] Pre-establishing an optimized functional block library, wherein the optimized functional block library stores a plurality of the optimized functional blocks;

[0018] For each of the functional blocks in the first integrated circuit, determining whether the functional block is a target functional block is performed in the following manner:

[0019] By means of preset rules, it is determined whether the optimized functional block corresponding to the functional block exists in the optimized functional block library. If so, it is determined that the functional block is the target functional block; if not, it is determined that the functional block is not the target functional block.

[0020] Further, based on any one of the above-mentioned technical solutions or a combination of multiple technical solutions, judging whether there is the optimized functional block corresponding to the functional block in the optimized functional block library by a preset rule includes:

[0021] Each of the optimization function blocks is configured with a unique first label, and the first label corresponds to the function of the optimization function block;

[0022] Each of the functional blocks is configured with a unique second label, and the second label corresponds to the function of the functional block;

[0023] If the second label corresponding to one of the functional blocks is one of the multiple first labels, it is determined that the optimized functional block corresponding to the functional block exists in the optimized functional block library, and the functional block corresponding to the second label is determined to be the target functional block, and the optimized functional block corresponding to the second label is determined to be the optimized functional block corresponding to the target functional block.

[0024] Further, in accordance with any one of the above technical solutions or a combination of multiple technical solutions, in response to one or more of the functional blocks being determined as target functional blocks, the method includes:

[0025] Manually select and determine one or more functional blocks in the first integrated circuit as the target functional blocks; or,

[0026] One or more of the functional blocks are determined as the target functional blocks based on preset rules, including: for each functional module, the number of transistor levels in its circuit structure is determined; if the number of transistor levels exceeds a preset threshold, it is further determined whether the functional module can be replaced by a circuit with a smaller number of transistor levels; if so, the functional module is determined to be the target functional block.

[0027] Furthermore, any one of the above-mentioned technical solutions or a combination of multiple technical solutions further includes the following steps:

[0028] If the target functional block has a plurality of input terminals and / or output terminals, a unique first code is configured for each input terminal of the target functional block and a unique second code is configured for each output terminal of the target functional block, and the first code is configured for the target output terminal electrically connected to the input terminal and the second code is configured for the target input terminal electrically connected to the output terminal;

[0029] According to the correspondence between the optimized functional block and the target functional block, the first code is configured for the input end of the optimized functional block, and the second code is configured for the output end of the optimized functional block;

[0030] After deleting the target functional block, the input end of the optimized functional block having the same first code is electrically connected to the target output end, and the output end of the optimized functional block having the same first code is electrically connected to the target input end.

[0031] Further, based on any one of the above technical solutions or a combination of multiple technical solutions, the optimization function block further includes a clock balancing circuit, and the clock balancing circuit is configured to synchronize the optimization function block with a system clock;

[0032] The optimization functional block includes a front-stage isolation circuit, an optimization circuit and a rear-stage isolation circuit which are electrically connected in sequence, wherein the front-stage isolation circuit and the rear-stage isolation circuit constitute the clock balancing circuit.

[0033] Further, based on any one of the above technical solutions or a combination of multiple technical solutions, the front-stage isolation circuit includes a first data latch module and a jitter emulator, the input end of the first data latch module is configured as the input end of the optimization function block, and the jitter emulator is electrically connected to the first data latch module and the system clock respectively;

[0034] The first data latch module is used to lock the previous stage signal and the system clock signal to obtain a first input signal and output it to the optimization circuit, wherein the previous stage signal is the input signal of the optimization function block;

[0035] The jitter simulator is used to obtain the previous stage signal and the system clock signal and generate a first clock signal of a corresponding phase according to an output time node of the first input signal and output the first clock signal to the optimization circuit.

[0036] Further, based on any one of the above-mentioned technical solutions or a combination of multiple technical solutions, the optimization circuit is a domino circuit structure, which includes a plurality of domino sub-circuits electrically connected in sequence;

[0037] The front-stage isolation circuit generates a corresponding phase clock signal for each of the domino sub-circuit and outputs the phase clock signal to the corresponding domino sub-circuit.

[0038] Further, based on any one of the technical solutions or a combination of multiple technical solutions described above, the post-stage isolation circuit includes a second data latch module, the input signal of the second data latch module includes a post-stage signal and a system clock signal, the post-stage signal is the output signal of the optimization circuit, and the output signal of the second data latch module is the post-stage signal synchronized with the system clock signal.

[0039] Furthermore, any one of the above-mentioned technical solutions or a combination of multiple technical solutions also includes performing APR timing balancing on the second integrated circuit.

[0040] According to another aspect of the present invention, the present invention provides a design system for improving integrated circuit performance based on transistor level design, wherein the system is configured to obtain a first integrated circuit based on EDA design, and to optimize the first integrated circuit to obtain a second integrated circuit using a design method for improving integrated circuit performance based on transistor level design as described above.

[0041] According to another aspect of the present invention, the present invention provides a computer-readable storage medium for storing program instructions, wherein the program instructions are configured to be called to execute the steps of any of the above methods.

[0042] The beneficial effects brought by the technical solution provided by the present invention are as follows:

[0043] a. The present invention can introduce optimized circuit design in an integrated circuit design environment that is highly dependent on EDA tools, and replace some functional blocks, namely, target functional blocks, in the integrated circuit generated by the EDA tool with more optimized functional blocks, thereby improving the quality of the integrated circuit design and the performance of its products. It can not only utilize the functions of existing EDA tools, but also meet the requirements of timeliness. In today's highly competitive industrial structure, this method can be used to design higher-quality integrated circuit products;

[0044] b. The present invention provides a variety of methods for determining whether a functional block of a first integrated circuit is a target functional block, including a manual method and an automatic method, and provides specific rules and implementation methods for determining whether a functional block is a target functional block, which has high compatibility and can be matched with different EDA tools for application;

[0045] c. The design method for improving integrated circuit performance based on transistor-level design proposed in the present invention also takes into account the adaptability of the system clock. By designing a front-stage isolation circuit and a rear-stage isolation circuit in the optimized functional block, the second integrated circuit obtained by replacing the target functional block with the optimized functional block satisfies the adaptability of the system clock and will not cause errors due to the optimized functional block not matching the system clock. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0047] Figure 1 A schematic diagram of the structure of a first integrated circuit designed based on EDA provided by an exemplary embodiment of the present invention;

[0048] Figure 2 A schematic diagram of a module of an optimization functional block provided for an exemplary embodiment of the present invention;

[0049] Figure 3 A schematic diagram of the structure and working principle of a pre-stage isolation circuit provided for an exemplary embodiment of the present invention;

[0050] Figure 4 A schematic diagram of the working principle of a jitter simulator provided for an exemplary embodiment of the present invention;

[0051] Figure 5 A schematic diagram of a structure of an optimized functional block with a domino circuit structure provided for an exemplary embodiment of the present invention;

[0052] Figure 6 A schematic diagram of the structure and working principle of a post-stage isolation circuit provided by an exemplary embodiment of the present invention;

[0053] Figure 7 A flow chart of a design method for improving integrated circuit performance based on transistor level design provided for an exemplary embodiment of the present invention;

[0054] Figure 8 A flowchart of timing balance design of an integrated circuit is provided for an exemplary embodiment of the present invention. DETAILED DESCRIPTION

[0055] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0056] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, device, product or equipment that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or equipment.

[0057] In view of the deficiencies in the prior art, the present invention aims to provide an integrated circuit design method based on transistor layer design, which method not only complies with the process of EDA integrated circuit design and can therefore utilize the original functions of EDA tools / software, but can also replace a certain functional module in the integrated circuit designed based on the EDA tool with a better circuit, thereby completing the performance optimization design of the integrated circuit, and can achieve the technical effect of both development timeliness and improved performance for the integrated circuit design method.

[0058] In one embodiment of the present invention, a design method for improving integrated circuit performance based on transistor level design is provided. The method is applied to designing integrated circuits. Figure 7 , the method comprises the following steps:

[0059] According to the design target of the integrated circuit, a first integrated circuit is obtained based on EDA design, wherein the first integrated circuit includes a plurality of functional blocks, and the functional blocks include at least a subcircuit for realizing a target function; this step is usually completed by a processor running an EDA tool;

[0060] In response to one or more of the functional blocks being determined as target functional blocks, the processor determines that the input terminal and the output terminal of the target functional block are electrically connected to the target output terminal and the target input terminal respectively;

[0061] Matching a corresponding optimized functional block to the target functional block, wherein the subcircuit included in the optimized functional block has the same function as the subcircuit included in the target functional block, and determining the input and output ends of the optimized functional block;

[0062] Replacing the target functional block in the first integrated circuit with the optimized functional block to obtain a second integrated circuit includes: deleting the target functional block; electrically connecting the input end of the optimized functional block to the target output end, and electrically connecting the output end of the optimized functional block to the target input end;

[0063] A target integrated circuit that meets the design goal is obtained according to the second integrated circuit design.

[0064] The integrated circuit is composed of a plurality of sub-circuits and is used to provide various functions. The present application regards the sub-circuit used to implement each function as a functional block, and in order to smoothly transmit data between functional blocks, each functional block is operated according to the system clock signal. Based on the existing EDA design technology, the EDA tool can be used to automatically generate the first integrated circuit including a plurality of cascaded functional blocks according to the design goal of the integrated circuit. Figure 1 The first integrated circuit designed based on EDA is shown, wherein the first functional block to the Nth functional block can be regarded as multiple stages, and each stage is based on the system clock signal (Clock signal Figure 1 CKsys) to synchronize data processing and data transmission. Figure 1 Din and Dout shown in the figure represent the input signal and output signal of each functional block respectively.

[0065] Although designing integrated circuits based on EDA can shorten design time and improve design accuracy, EDA tools provide designs in a way that is least restricted by process technology or design methods for commercial considerations, thus sacrificing the possibility of optimizing some designs. Based on this, the present application proposes to improve and optimize the design of integrated circuits based on improvements in transistor-level characteristics, which can obtain integrated circuits with better performance. By determining Figure 1 Whether there is room for further improvement in the functional blocks shown in the figure, if so, the design scheme proposed in the present invention that can be applied to EDA tools is used to obtain a better second integrated circuit that can replace the first integrated circuit, and the final target integrated circuit is designed based on the second integrated circuit.

[0066] In the present application, there are multiple methods for determining whether the functional block is the target functional block, which are described below respectively.

[0067] In one embodiment of the present invention, in response to one or more of the functional blocks in the first integrated circuit being marked, the EDA tool determines the marked functional blocks as the target functional blocks.

[0068] In this embodiment, there are multiple ways to mark the functional blocks. One way is to manually select and determine one or more functional blocks in the first integrated circuit as the target functional blocks; that is, in actual applications, a designer checks and determines whether a functional block is a functional block that can be further optimized.

[0069] Another way is to use a system / software to automatically determine one or more of the functional blocks as the target functional blocks based on preset rules. For example, a preset rule includes the following steps: for each functional module, determine the number of transistor levels in its circuit structure, if the number of transistor levels exceeds a preset number threshold, further determine whether the functional module can be replaced by a circuit with a smaller number of transistor levels, if so, determine the functional module as the target functional block.

[0070] In one embodiment of the present invention, whether the functional block is the target functional block is determined in the following manner:

[0071] Pre-establishing an optimized functional block library, wherein the optimized functional block library stores a plurality of the optimized functional blocks;

[0072] For each of the functional blocks in the first integrated circuit, determining whether the functional block is a target functional block is performed in the following manner:

[0073] By means of preset rules, it is determined whether the optimized functional block corresponding to the functional block exists in the optimized functional block library. If so, it is determined that the functional block is the target functional block; if not, it is determined that the functional block is not the target functional block.

[0074] Specifically, for example, each of the optimized functional blocks in the optimized functional block library is configured with a unique first label, and the first label corresponds to the function of the optimized functional block; each of the functional blocks is configured with a unique second label, and the second label corresponds to the function of the functional block;

[0075] If the second label corresponding to one of the functional blocks is one of the multiple first labels, it is determined that the optimized functional block corresponding to the functional block exists in the optimized functional block library, and the functional block corresponding to the second label is determined to be the target functional block, and the optimized functional block corresponding to the second label is determined to be the optimized functional block corresponding to the target functional block.

[0076] It should be noted that the above-mentioned methods for determining whether the functional block is the target functional block can be used in combination, and the present invention is not limited to applying only one of the above-mentioned methods for determining whether the functional block is the target functional block.

[0077] Most commercial EDA tools first use static logic level design to synthesize circuits, and then transfer to integrated circuit layout. Using static logic (static logic) for design has a high tolerance for differences between various semiconductor processes and will not be affected by parameter differences in semiconductor factories (fabs). On the contrary, although there are indeed optimized designs for transistor deposition for certain specific designs, for example, in more advanced processes, as transistors become smaller and smaller, the driving capability generated by the current that can pass through is increasingly limited. A 24-input demultiplexer requires three to four levels of circuits using static circuit logic gates, but if the wire-or characteristics of NMOS are used, the design can be completed in one level, which not only reduces delays but also reduces chip area, and has advantages in terms of area occupied, power consumption and speed, but increases design uncertainty for EDA tools. Therefore, the integrated circuit optimization method proposed in this application can further optimize the circuit from the level of transistor level characteristics. Using one of the above-mentioned methods, the 24-input demultiplexer module designed using EDA tools is determined as the target functional block and replaced with a better NMOS-based first-level transistor circuit.

[0078] For another example, the general-purpose register file (GFR) in the central processing unit is usually implemented by a fast static random read / write memory (SRAM). This general register file has dedicated read ports and write ports, which can access different registers concurrently in multiple ways. However, if the static circuit generated by EDA is manually adjusted and optimized, it has been proven that the area can be reduced by 2 / 3 and the speed can be increased by 2 times in a specific process technology of a specific foundry. The disadvantage is that the design needs to be adjusted for different foundries or process technologies. Therefore, it increases the uncertainty in design for EDA tools. Similarly, the mathematical operation unit (ALU) in the GPU also has a design that manually optimizes the static circuit generated by EDA. Therefore, the design method compatible with the EDA integrated circuit design method proposed by the present invention based on the optimization design level of transistor-level characteristics is very meaningful.

[0079] In one embodiment of the present invention, if the target functional block has a plurality of input terminals and / or output terminals, a unique first code is configured for each input terminal and a unique second code is configured for each output terminal, and the first code is configured for the target output terminal electrically connected to the input terminal and the second code is configured for the target input terminal electrically connected to the output terminal;

[0080] According to the correspondence between the optimized functional block and the target functional block, the first code is configured for the input end of the optimized functional block, and the second code is configured for the output end of the optimized functional block;

[0081] After deleting the target functional block, the input end of the optimized functional block having the same first code is electrically connected to the target output end, and the output end of the optimized functional block having the same first code is electrically connected to the target input end.

[0082] In the design process of integrated circuits, whether based on EDA design or other methods, the adaptability of the system clock needs to be considered. For example, when using EDA tools to design integrated circuits, if there is no EDA tool to help with timing checks, errors are likely to occur in complex systems. Therefore, the design method for improving the performance of integrated circuits based on transistor-level design proposed in the present invention must also consider the adaptability of the system clock.

[0083] In one embodiment of the present invention, the design flow of timing balance in the integrated circuit performance design process based on transistor level optimization is as follows: Figure 8 The optimization function block further includes a clock balancing circuit, and the clock balancing circuit is configured to synchronize the optimization function block with the system clock. Figure 2 As shown, the optimized functional block includes a front-stage isolation circuit, an optimization circuit and a rear-stage isolation circuit which are electrically connected in sequence, wherein the front-stage isolation circuit and the rear-stage isolation circuit constitute the clock balancing circuit, so that the second integrated circuit obtained by replacing the target functional block with the optimized functional block satisfies the adaptability of the system clock and will not cause errors due to the optimization functional block not matching the system clock.

[0084] like Figure 3 As shown, the front-stage isolation circuit at least includes a first data latch module (Data latch) and a jitter emulator (Jitter emulator), the input end of the first data latch module is configured as the input end of the optimization function block, and the jitter emulator is electrically connected to the first data latch module and the system clock respectively.

[0085] The first data latch module may be composed of a plurality of buffers, not gates or latches. The first data latch module uses a system clock to lock a previous stage signal, and is used to lock the previous stage signal ( Figure 3 Din) and the system clock signal (CKsys) to obtain the first input signal ( Figure 3 Dα shown in FIG. 1 ) and outputs it to the optimization circuit, and the front-stage signal is the input signal of the optimization function block.

[0086] The jitter simulator is used to obtain the front-stage signal ( Figure 3 Din) and the system clock signal (CKsys) and according to the first input signal ( Figure 3 The jitter simulator is used to generate a delayed clock generated by a system clock signal through a plurality of transistors, such as Figure 4 As shown, the jitter simulator passes the system clock signal through multiple NOT gates, and there will be multiple signal output points (F1, F2, ..., Fn-1, Fn). After calculation, an appropriate phase difference can be selected as the output clock signal CKF of the jitter simulator. Since the functional blocks are already fixed in the routing stage of APR (Auto Placement & Route), multiple groups of signal output points (F1, F2, ..., Fn-1, Fn) are for once the simulation results need to adjust the internal clock, different signal output points can be selected without changing the layout (placement) to obtain clock signals of different phases. APR can be roughly divided into 4 steps: floorplan, unit placement, clock tree synthesis (CTS) and routing (route).

[0087] In one embodiment of the present invention, if the transistor circuit requires multiple clock signals with different phases, a jitter simulator is used to output multiple clock signals with corresponding phases. Figure 5 As shown, the optimization circuit is a domino circuit structure, which includes a plurality of domino sub-circuits electrically connected in sequence, domino sub-circuit 1 to domino sub-circuit p; the front-stage isolation circuit generates a corresponding phase clock signal (Fn, Fn+1, ..., Fn+p-1, Fn+p) matching its output signal for each domino sub-circuit and outputs it to the corresponding domino sub-circuit (domino sub-circuit 1, domino sub-circuit 2, ..., domino sub-circuit p-1, domino sub-circuit p).

[0088] The post-stage isolation circuit uses the system clock to lock the data transmitted to the next stage ( Figure 6 The circuit function is to ensure that the output data Dout is consistent with the system clock. Figure 6 As shown, the rear stage isolation circuit includes a second data latch module, and the input signal of the second data latch module includes a rear stage signal ( Figure 6 The output signal of the optimization circuit is determined as the second input signal and input into the second data latch module. The output signal Dout of the second data latch module is the output signal of the optimization circuit after synchronizing the second input signal with the system clock signal.

[0089] When the data in the functional area reaches the expected delay of the transistor circuit, the appropriate jitter simulator output is selected as the clock inside the functional block. Since the jitter simulator has multiple outputs, each output represents a clock signal with a different degree of phase difference with the system clock. After replacing the target functional block with the transistor circuit, it is necessary to perform timing balance again, that is, perform timing balance of APR on the second integrated circuit. If the timing cannot be balanced, adjust the selection of the jitter simulator output until the timing is balanced and the best performance is obtained.

[0090] The design method for improving integrated circuit performance based on transistor layer design proposed in the present invention can introduce optimized circuit design in an integrated circuit design environment that is highly dependent on EDA tools, and replace some functional blocks, namely target functional blocks, in the integrated circuit generated by the EDA tool with more optimal optimized functional blocks, thereby improving the quality of integrated circuit design and the performance of its products. It can not only utilize the functions of existing EDA tools, but also meet the requirements of timeliness. In today's highly competitive industrial structure, this method can be used to design higher quality integrated circuit products.

[0091] In one embodiment of the present invention, a design system for improving integrated circuit performance based on transistor-level design is provided, wherein the system is configured to obtain a first integrated circuit based on EDA design, and to optimize the first integrated circuit to obtain a second integrated circuit using a design method for improving integrated circuit performance based on transistor-level design as described in any of the above embodiments, and to obtain a target integrated circuit using the second integrated circuit, or the second integrated circuit is the target integrated circuit.

[0092] In one embodiment of the present invention, a computer-readable storage medium is provided for storing program instructions, wherein the program instructions are configured to call and execute the steps of any of the above-mentioned design methods for improving integrated circuit performance based on transistor-level design.

[0093] It should be noted that the design system and computer-readable storage medium embodiments for improving integrated circuit performance based on transistor-level design provided by the present invention have the same inventive concept as the above-mentioned design method embodiment for improving integrated circuit performance based on transistor-level design, and all the contents of the design method embodiment for improving integrated circuit performance based on transistor-level design are incorporated into the design system and computer-readable storage medium embodiments for improving integrated circuit performance based on transistor-level design by introduction.

[0094] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0095] The above is only a specific implementation of the present application. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present application. These improvements and modifications should also be regarded as the scope of protection of the present application.

Claims

1. A design method for improving integrated circuit performance based on transistor level design, characterized in that: Applied to designing integrated circuits, the method comprises the following steps: According to the design target of the integrated circuit, a first integrated circuit is obtained based on EDA design, wherein the first integrated circuit includes a plurality of functional blocks, and the functional blocks include a subcircuit for realizing at least one target function; In response to one or more of the functional blocks being determined as target functional blocks, determining that the input terminals and output terminals of the target functional blocks are electrically connected to the target output terminals and the target input terminals, respectively; Matching a corresponding optimized functional block to the target functional block, wherein the subcircuit included in the optimized functional block has the same function as the subcircuit included in the target functional block, and determining the input and output ends of the optimized functional block; Replacing the target functional block in the first integrated circuit with the optimized functional block to obtain a second integrated circuit includes: deleting the target functional block; electrically connecting the input end of the optimized functional block to the target output end, and electrically connecting the output end of the optimized functional block to the target input end; Obtaining a target integrated circuit that meets the design goal according to the second integrated circuit design; It also includes determining the target functional block by: Pre-establishing an optimized functional block library, wherein the optimized functional block library stores a plurality of the optimized functional blocks; For each of the functional blocks in the first integrated circuit, determining whether the functional block is a target functional block is performed in the following manner: By using a preset rule, it is determined whether the optimized functional block corresponding to the functional block exists in the optimized functional block library; if so, the functional block is determined to be the target functional block; if not, the functional block is determined not to be the target functional block; Judging whether the optimized functional block corresponding to the functional block exists in the optimized functional block library by a preset rule includes: Each of the optimization function blocks is configured with a unique first label, and the first label corresponds to the function of the optimization function block; Each of the functional blocks is configured with a unique second label, and the second label corresponds to the function of the functional block; If the second label corresponding to one of the functional blocks is one of the multiple first labels, it is determined that the optimized functional block corresponding to the functional block exists in the optimized functional block library, and the functional block corresponding to the second label is determined to be the target functional block, and the optimized functional block corresponding to the second label is determined to be the optimized functional block corresponding to the target functional block.

2. The design method for improving integrated circuit performance based on transistor level design according to claim 1, characterized in that: It also includes determining the target functional block by: In response to one or more of the functional blocks in the first integrated circuit being marked, the marked functional blocks are determined to be the target functional blocks.

3. The design method for improving integrated circuit performance based on transistor level design according to claim 1, characterized in that: In response to one or more of the functional blocks being determined as target functional blocks, the method comprises: Manually select and determine one or more functional blocks in the first integrated circuit as the target functional blocks; or, One or more of the functional blocks are determined as the target functional blocks based on preset rules, including: for each functional module, the number of transistor levels in its circuit structure is determined; if the number of transistor levels exceeds a preset threshold, it is further determined whether the functional module can be replaced by a circuit with a smaller number of transistor levels; if so, the functional module is determined to be the target functional block.

4. The design method for improving integrated circuit performance based on transistor level design according to claim 1, characterized in that: The following steps are also included: If the target functional block has a plurality of input terminals and / or output terminals, a unique first code is configured for each input terminal of the target functional block and a unique second code is configured for each output terminal of the target functional block, and the first code is configured for the target output terminal electrically connected to the input terminal and the second code is configured for the target input terminal electrically connected to the output terminal; According to the correspondence between the optimized functional block and the target functional block, the first code is configured for the input end of the optimized functional block, and the second code is configured for the output end of the optimized functional block; After deleting the target functional block, the input end of the optimized functional block having the same first code is electrically connected to the target output end, and the output end of the optimized functional block having the same first code is electrically connected to the target input end.

5. The design method for improving integrated circuit performance based on transistor level design according to claim 1, characterized in that: The optimization functional block further includes a clock balancing circuit configured to synchronize the optimization functional block with a system clock; The optimization functional block includes a front-stage isolation circuit, an optimization circuit and a rear-stage isolation circuit which are electrically connected in sequence, wherein the front-stage isolation circuit and the rear-stage isolation circuit constitute the clock balancing circuit.

6. The design method for improving integrated circuit performance based on transistor level design according to claim 5, characterized in that: The front-stage isolation circuit includes a first data latch module and a jitter emulator, the input end of the first data latch module is configured as the input end of the optimization function block, and the jitter emulator is electrically connected to the first data latch module and the system clock respectively; The first data latch module is used to lock the previous stage signal and the system clock signal to obtain a first input signal and output it to the optimization circuit, wherein the previous stage signal is an input signal of the optimization function block; The jitter simulator is used to obtain the previous stage signal and the system clock signal and generate a first clock signal of a corresponding phase according to an output time node of the first input signal and output the first clock signal to the optimization circuit.

7. The design method for improving integrated circuit performance based on transistor level design according to claim 6, characterized in that: The optimization circuit is a domino circuit structure, which includes a plurality of domino sub-circuits electrically connected in sequence; The front-stage isolation circuit generates a corresponding phase clock signal for each of the domino sub-circuit and outputs the phase clock signal to the corresponding domino sub-circuit.

8. The design method for improving integrated circuit performance based on transistor level design according to claim 6, characterized in that: The post-stage isolation circuit includes a second data latch module, the input signal of the second data latch module includes a post-stage signal and a system clock signal, the post-stage signal is the output signal of the optimization circuit, and the output signal of the second data latch module is the post-stage signal synchronized with the system clock signal.

9. The design method for improving integrated circuit performance based on transistor level design according to claim 1, characterized in that: The method also includes performing APR timing balancing on the second integrated circuit.

10. A design system for improving integrated circuit performance based on transistor level design, characterized in that: The system is configured to obtain a first integrated circuit based on EDA design, and optimize the first integrated circuit using the design method for improving integrated circuit performance based on transistor-level design as described in any one of claims 1 to 9 to obtain a second integrated circuit.

11. A computer-readable storage medium for storing program instructions, characterized in that: The program instructions are configured to be called to execute the steps of the method according to any one of claims 1 to 9.

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