Display panel and display terminal

Abstract

The embodiment of the invention discloses a display panel and a display terminal, the display panel comprises M rows of pixels and M cascaded gate drive circuits, each gate drive circuit is correspondingly connected with one row of pixels, and each gate drive circuit comprises a reset transistor; the grid electrodes of the K continuously arranged reset transistors are connected to the first metal wire, the grid electrodes of the M-K continuously arranged reset transistors are connected to the reset signal wire, and the first metal wire and the reset signal wire are in a disconnected state. According to the display panel provided by the embodiment of the invention, re-cutting of the reset transistors of the panel can be realized through a one-time cutting mode, and at least the problem of re-cutting of connection between the drain electrodes of the N reset transistors and the preset low-potential signal line in the prior art is solved; the cutting efficiency is low and the panel yield is low due to the fact that the number of times of cutting is large.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel and a display terminal. Background Art

[0002] The gate driver on array (GOA) circuit is a technology used in liquid crystal display panels. It integrates the gate driver circuit on the array substrate to achieve the row-by-row scanning drive function. Each GOA unit contains a reset transistor (Reset), which is used to ensure that the gate signal can be correctly reset to the initial state at the beginning of each frame, ready for the drive of a new row of pixels.

[0003] In the GOA circuit of multiple clock signals (N CKs), the first N GOA units are used for precharging, so reset transistors are not required. In the existing panel cutting process, if the GOA units in the finished panel after cutting all contain reset transistors, the connection between the drain of the first N reset transistors and the preset low-potential signal line needs to be cut again. The number of cutting times is large, resulting in low cutting efficiency, and multiple cutting is likely to affect other routings, thereby affecting the yield of the panel after cutting. Summary of the invention

[0004] Embodiments of the present application provide a display panel and a display terminal to at least solve the technical problem that the connection between the drains of the existing N reset transistors and the preset low-potential signal lines is cut again, and the cutting efficiency is low and the panel yield is low due to the large number of cutting times.

[0005] On the one hand, an embodiment of the present application provides a display panel, comprising: M rows of pixels; M cascaded gate drive circuits, each of the gate drive circuits corresponding to a row of the pixels, and each of the gate drive circuits comprising a reset transistor; wherein the gates of K consecutively arranged reset transistors are connected to a first metal routing, and the gates of MK consecutively arranged reset transistors are connected to a reset signal line, the first metal routing and the reset signal line are in a disconnected state, M and K are positive integers, and K<M.

[0006] In one embodiment, the first metal wiring and the reset signal line are made of the same layer and the same material.

[0007] In one embodiment, every N cascaded gate driving circuits from top to bottom along the scanning direction of the pixel form a group; wherein, K consecutively arranged reset transistors belong to the first group of gate driving circuits, N represents the number of driving clock signals corresponding to the display panel, K≤N, and M is an integer multiple of N.

[0008] In one embodiment, the gates of the M reset transistors share a second metal wiring, the reset signal line is arranged on a side close to the Mth reset transistor, and the second metal line is connected to the reset signal line.

[0009] In one embodiment, the second metal wiring is in a disconnected state at a position between the Kth reset transistor and the K+1th reset transistor.

[0010] In one embodiment, the first metal routing line and the reset signal line belong to the same third metal routing line, and the third metal routing line is in a disconnected state at the position of the Kth reset transistor.

[0011] In one embodiment, the third metal wiring between the gate of the Kth reset transistor and the gate of the K+1th reset transistor is in a disconnected state.

[0012] In one embodiment, K=N / 2.

[0013] In one embodiment, K=N.

[0014] On the other hand, an embodiment of the present application further provides a display terminal, comprising the display panel described in any one of the above embodiments.

[0015] The beneficial effects provided by the embodiments of the present application include at least:

[0016] The embodiment of the present application provides a display panel, including M rows of pixels; M cascaded gate drive circuits, each gate drive circuit is connected to a row of pixels, and each gate drive circuit includes a reset transistor; wherein the gates of K consecutively arranged reset transistors are connected to a first metal routing, the gates of MK consecutively arranged reset transistors are connected to a reset signal line, the first metal routing and the reset signal line are disconnected, M and K are positive integers, and K<M. Through the display panel provided by the embodiment of the present application, the gates of K consecutively arranged reset transistors and the gates of other reset transistors are disconnected, the other reset transistors are respectively connected to the reset signal line, and the K consecutively arranged reset transistors are not connected to the reset signal line. If the first metal routing and the reset signal line are the same routing, it can be achieved by a one-time cutting method, at least solving the technical problem of the existing connection between the drain of N reset transistors and the preset low-potential signal line being cut again, and the low cutting efficiency and low panel yield caused by the large number of cutting times. The panel structure provided in the embodiment of the present application can be achieved by only one cutting, which effectively improves the panel cutting efficiency and panel yield.

[0017] Other beneficial effects of the embodiments of the present application will be further described in the following specific implementation manner. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 is a schematic diagram of a GOA circuit provided in an optional embodiment of the present application;

[0019] Figure 2 is a scanning schematic diagram of a GOA circuit in a display panel provided in an optional embodiment of the present application;

[0020] Figure 3 is a scanning schematic diagram of a GOA circuit in a cut display panel provided in an optional embodiment of the present application;

[0021] Figure 4 is a schematic structural diagram of a display panel provided in an optional embodiment of the present application;

[0022] Figure 5 is a schematic diagram of cutting a display panel provided in an optional embodiment of the present application;

[0023] Figure 6 A schematic diagram of cutting another display panel provided in an optional embodiment of the present application

[0024] Figure 7 It is a structural schematic diagram of a display terminal provided in an optional embodiment of the present application.

[0025] Description of Reference Numerals

[0026] 1. Display terminal;

[0027] 10, display panel; 11, first metal wiring; 12, reset signal line; 13, second metal wiring; 14, third metal wiring;

[0028] 101, pull-down maintaining module; 102, down transmission module; 103, pull-up module; 104, pull-down module; 20, terminal body. DETAILED DESCRIPTION

[0029] The technical solutions in the embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application. The described technical solutions are only used to explain and illustrate the ideas of the present application and should not be regarded as limiting the scope of protection of the present application.

[0030] In the description of the present application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise" and the like indicate positions or positional relationships based on the positions or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present application. In addition, the terms "first" and "second" are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present application, the meaning of "multiple" is two or more, unless otherwise clearly and specifically defined.

[0031] In the description of this application, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, an electrical connection, or mutual communication; it can be a direct connection, or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0032] The disclosure below provides many different embodiments or examples to realize the different structures of the present application. In order to simplify the disclosure of the present application, the parts and settings of specific examples are described below. Of course, they are only examples, and the purpose is not to limit the present application. In addition, the present application can repeat reference numbers and / or reference letters in different examples, and this repetition is for the purpose of simplification and clarity, which itself does not indicate the relationship between the various embodiments and / or settings discussed. In addition, the various specific processes and material examples provided by the present application, but those of ordinary skill in the art can appreciate the application of other processes and / or the use of other materials.

[0033] In the drawings, components with the same structure are represented by the same numerical labels, and components with similar structures or functions are represented by similar numerical labels. In addition, for the convenience of understanding and description, the size and thickness of each component shown in the drawings are arbitrarily shown, and the present application does not limit the size and thickness of each component.

[0034] The various embodiments provided in this application are similar, and features in different embodiments may be combined with each other.

[0035] The order of description of the following embodiments is not intended to limit the preferred order of the embodiments.

[0036] Reference Figure 1 As shown in FIG. 1 , in the GOA circuit designed by combining the frame start signal STV and the reset signal Reset, a Reset thin film transistor (TFT) is designed on the Reset line of the non-head-end GOA unit, such as Figure 1 Trst shown connects Q(N) and VSSQ (preset low level). Figure 1 An optional GOA circuit schematic diagram is provided, in which a GOA circuit includes a pull-up control transistor T11, a downlink module 102, a pull-up module 103, a pull-down module 104, a pull-down maintenance module 101 and a bootstrap capacitor Cbt. The pull-up control transistor T11 is connected to the N-6th level transmission signal ST (N-6) and the N-6th level scanning signal G (N-6), and is electrically connected to the first node Q (N), for pulling up the potential of the first node Q (N). The downlink module 102 is connected to the low level signal VSSQ and the clock signal CLK, for outputting the current level transmission signal G (N). The pull-up module 103 is connected to the clock signal CLK, and is electrically connected to the first node Q (N) and the second node M (N), for outputting the current level scanning signal G (N). The pull-down module 104 is connected to the low level Vss and the N+6th level scanning signal G(N+6), and is electrically connected to the first node Q(N), the second node M(N) and the third node P(N), and is used to pull down the potential of the first node Q(N) and the current level scanning signal G(N). The pull-down maintenance module 101 is connected to the low level signal VSSQ, and is electrically connected to the first node Q(N) and the third node P(N), and is used to maintain the potential of the first node Q(N) at the potential of the low level signal VSSQ after the pull-down module 104 pulls down the potential of the first node Q(N). The first end of the bootstrap capacitor Cbt is electrically connected to the first node Q(N), and the second end is electrically connected to the second node M(N). The reset transistor Trst is connected to the low level signal VSSQ and the control signal Reset, and is electrically connected to the first node Q(N). The reset transistor Trst is used to further pull down the potential of the first node Q(N) to the potential of the low level signal VSSQ under the control of the control signal Reset.

[0037] It should be noted that the GOA circuit structure provided in the embodiment of the present application is only for a better understanding of the principle of the present application and cannot be understood as a limitation of the present application. The specific circuit connections in the above-mentioned pull-down maintaining module 101, the downlink module 102, the pull-up module 103 and the pull-down module 104 can be set according to actual needs, and the present application does not make specific limitations on this.

[0038] Reference Figure 2As shown, in order to avoid the inability to effectively charge Q(N), the head-end GOA usually cancels the Reset TFT (Trst), that is, the head-end GOA of the conventional display screen does not set the Reset TFT. In the embodiment of the present application, the head end can be understood as, according to the row scanning order of GOA, the first N rows are the first group of cascaded gate drive circuits, N corresponds to the number of clock signals, that is, N is a group for cyclic scanning, and the first group can be defined as the head-end GOA.

[0039] In order to meet the demand for customized resolution based on existing displays, laser re-cutting will be adopted. Figure 3 As shown, a display screen of a required size is obtained by cutting the GOA display screen once through a second cutting method. Figure 3 As shown in the reverse scan mode GOA display, the GOA head end will be cut during the secondary cutting (such as Figure 3 As shown in the dashed box in the middle, there will be a Trst design on the Reset trace of the GOA head end of the cut bar screen display row. When Trst is turned on, the Q(N) point will be pulled down, resulting in the inability to effectively charge the Q(N) at the GOA head end of the cut bar screen, affecting the display effect.

[0040] The current solution is to disconnect the drain of the first N levels of Trst of the cut strip screen through laser to disconnect it from VSSQ, so that Trst cannot be turned on normally, thereby preventing the first N levels of Q (N) from being effectively charged. However, this method requires cutting N places, which is a lot of work, and because the size of Trst is small, its drain is difficult to cut, and it is easy to cut other traces, thereby reducing the yield of the cut strip screen.

[0041] In order to solve the above problems, the present application provides a display panel. Figure 4 As shown, the display panel 10 includes: M rows of pixels P 1 To P M and M cascaded gate drive circuits G 1 To G M , each gate driving circuit is connected to a row of pixels.

[0042] Each gate drive circuit includes a reset transistor (T 1 To T M ); wherein K consecutively arranged reset transistors (T 1 To T K ) is connected to the gate of the first metal wiring 11, MK reset transistors (T K+1 To T M ) is connected to the reset signal line 12, the first metal wiring 11 and the reset signal line 12 are disconnected, M and K are positive integers, and K<M.

[0043] It should be noted that M is the number of pixel rows on the display panel after cutting. In actual use, the gate drive scan can be performed in the order from the first row to the Mth row, or from the Mth row to the first row. The embodiment of the present application does not limit this.

[0044] In the display panel provided by the embodiment of the present application, the gates of K consecutively arranged reset transistors are disconnected from the gates of other reset transistors, and the other reset transistors are respectively connected to the reset signal lines, while the K consecutively arranged reset transistors are not connected to the reset signal line. If the first metal routing and the reset signal line are the same routing, it can be achieved by a one-time cutting method, which at least solves the technical problem of cutting again the connection between the drains of the existing N reset transistors and the preset low-potential signal line, and the low cutting efficiency and low panel yield caused by the large number of cutting times. The panel structure provided in the embodiment of the present application can be achieved by a single cutting, which effectively improves the panel cutting efficiency and the panel yield.

[0045] The driving principle of the GOA circuit is similar to that of a shift register, which outputs a high-level voltage signal when the scan line is selected and a low-level voltage signal when it is not selected. The GOA units are connected in a cascade manner, and the output signal of one row serves as both the reset signal of the previous row and the input signal of the next row. In the design of GOA, in order to solve the attenuation problem of the clock signal (CLK signal) during the transmission process of a large-size panel, a multi-CLK signal line design is usually adopted, such as a 4CLK, 6CLK, and 8CLK signal line design, to reduce the load and improve efficiency.

[0046] In one embodiment, every N cascaded gate driving circuits from top to bottom along the scanning direction of the pixel are a group; wherein, K consecutively arranged reset transistors belong to the first group of gate driving circuits, N represents the number of driving clock signals corresponding to the display panel 10, K≤N, and M is an integer multiple of N.

[0047] For example, in a GOA circuit designed with 4CLK signal lines, N is 4, and the first four GOA circuits can be regarded as the first-end GOA; in a GOA circuit designed with 6CLK signal lines, N is 6, and the first six GOA circuits can be regarded as the first-end GOA.

[0048] In the embodiment of the present application, the gate drive scanning is performed in order from the first row to the Mth row for exemplary description.

[0049] In one embodiment, the first metal trace 11 and the reset signal line 12 are in the same layer and made of the same material, that is, the first metal trace 11 and the reset signal line 12 are located in the same layer and are made of the same material. The first metal trace 11 and the reset signal line 12 can be the same metal trace, which is disconnected at a specific position, and can be disconnected by laser cutting, or other panel processes to achieve the disconnection of the metal layer.

[0050] Reference Figure 5 As shown in FIG. 1 , in an optional embodiment, an optional structure of the display panel 10 is as follows: the gates of the M reset transistors share the second metal wiring 13, the reset signal line 12 is arranged on a side close to the Mth reset transistor, and the second metal wiring 13 is connected to the reset signal line 12. The second metal wiring 13 is disconnected at a position between the Kth reset transistor and the K+1th reset transistor, as shown in FIG. Figure 5 As shown in L1.

[0051] exist Figure 5 In the example shown, the second metal wiring 13 runs through the entire display panel 10 along the row scanning direction, and the gates of the M reset transistors are formed by the metal layer where the second metal wiring 13 is located. The reset signal line 12 is set at the bottom of the display panel 10, that is, below the Mth row of pixels, which can also be understood as below the Mth GOA. The second metal wiring 13 can be connected to the reset signal line 12 through a via, so that the M reset transistors can obtain the reset signal through the reset signal line 12, and the propagation direction of the reset signal is conducted from bottom to top.

[0052] In order to make the reset transistor at the head end GOA of the cut display panel 10 not work, the second metal wiring 13 between the Kth reset transistor and the K+1th reset transistor can be disconnected. In this way, the first K reset transistors will not be able to obtain the reset signal and the reset transistor will not work normally.

[0053] It should be noted that K can be any positive integer less than N. If K is 1, the first reset transistor cannot work normally, and Q(1) can be charged normally. If K is 2, the first two reset transistors cannot work normally, and Q(1) and Q(2) can be charged normally. The embodiment of the present application does not specifically limit the value of K, but only provides an optional implementation. In this implementation, the closer the value of K is to N, the better the charging effect of the head-end GOA.

[0054] In one example, if N is 6, K is an integer less than 6, for example, K may be 2, 3, 4 or 5, and K may also be equal to 6, as long as at least two Q points can be charged normally.

[0055] In the display panel provided by the embodiment of the present application, the gates of K consecutively arranged reset transistors are disconnected from the gates of other reset transistors, and the other reset transistors are respectively connected to the reset signal lines, while the K consecutively arranged reset transistors are not connected to the reset signal line. If the first metal routing and the reset signal line are the same routing, it can be achieved by a one-time cutting method, which at least solves the technical problem of cutting again the connection between the drains of the existing N reset transistors and the preset low-potential signal line, and the low cutting efficiency and low panel yield caused by the large number of cutting times. The panel structure provided in the embodiment of the present application can be achieved by a single cutting, which effectively improves the panel cutting efficiency and the panel yield.

[0056] If the gate signal of the N / 2-stage reset transistor before the display row is disconnected, so that it cannot work normally, the first N / 2 stages Q (N) cannot be effectively charged; if the N-th display row of the display screen is cut, the wiring is disconnected by laser or other cutting methods, thereby disconnecting the gate signal of the N-stage reset transistor before the display row, so that it cannot work normally, thereby avoiding the first N stages Q (N) cannot be effectively charged. Regardless of which row is cut, only one place of the second metal wiring 13 needs to be cut, which is simple and efficient, reduces the cutting workload, and improves the re-cutting yield and display effect of the GOA display screen.

[0057] Reference Figure 6 As shown, in an optional embodiment, an optional structure of the display panel 10 is: the first metal wiring 11 and the reset signal line 12 belong to the third metal wiring 14, and the third metal wiring 14 is in a disconnected state at the position of the Kth reset transistor, such as Figure 6 As shown in L2.

[0058] Figure 6 In the panel structure shown, the first metal trace 11 and the reset signal line 12 are the same metal trace, namely the third metal trace 14. It can be understood that after a display panel 10 is cut once, the gates of the M reset transistors are all connected to the third metal trace 14. At this time, the third metal trace 14 can be understood as the reset signal line of the entire display panel 10. Figure 6 In the panel structure shown, the reset signal line (that is, the third metal wiring 14) runs through the entire display panel from top to bottom along the row scanning direction of the display panel. After secondary cutting, the third metal wiring 14 is disconnected at the position of the Kth reset transistor, that is, it is divided into the first metal wiring 11 and the reset signal line 12. The third metal wiring 14 is used as a reset signal line, directly connected to the reset signal, and the propagation direction of the reset signal is conducted from bottom to top, that is, it propagates from the Mth reset transistor to the direction of the first reset transistor.

[0059] In one embodiment, disconnecting the third metal wiring 14 at the position of the Kth reset transistor may be disconnecting the third metal wiring 14 between the gate of the Kth reset transistor and the gate of the K+1th reset transistor.

[0060] In order to make the reset transistor at the head end GOA of the cut display panel 10 not work, the third metal wiring 14 between the Kth reset transistor and the K+1th reset transistor can be disconnected. In this way, the first K reset transistors will not be able to obtain the reset signal and the reset transistor will not work normally.

[0061] It should be noted that K can be any positive integer less than N. If K is 1, the first reset transistor cannot work normally, and Q(1) can be charged normally. If K is 2, the first two reset transistors cannot work normally, and Q(1) and Q(2) can be charged normally. The embodiment of the present application does not specifically limit the value of K, but only provides an optional implementation. In this implementation, the closer the value of K is to N, the better the charging effect of the head-end GOA.

[0062] In one example, if N is 8, K is an integer less than 8, for example, K may be 2, 3, 4, 5, 6 or 7, and K may also be equal to 8, as long as at least two Q points can be charged normally.

[0063] In the display panel provided by the embodiment of the present application, the gates of K consecutively arranged reset transistors are disconnected from the gates of other reset transistors, and the other reset transistors are respectively connected to the reset signal lines, while the K consecutively arranged reset transistors are not connected to the reset signal line. If the first metal routing and the reset signal line are the same routing, it can be achieved by a one-time cutting method, which at least solves the technical problem of cutting again the connection between the drains of the existing N reset transistors and the preset low-potential signal line, and the low cutting efficiency and low panel yield caused by the large number of cutting times. The panel structure provided in the embodiment of the present application can be achieved by a single cutting, which effectively improves the panel cutting efficiency and the panel yield.

[0064] If the gate signal of the N / 2-stage reset transistor before the display row is disconnected, so that it cannot work normally, the first N / 2 stages Q (N) cannot be effectively charged; if the N-th display row of the display screen is cut, the routing is disconnected by laser or other cutting methods, thereby disconnecting the gate signal of the N-stage reset transistor before the display row, so that it cannot work normally, thereby avoiding the first N stages Q (N) cannot be effectively charged. Regardless of which row is cut, only one place of the third metal routing 14 needs to be cut, which is simple and efficient, reduces the cutting workload, and improves the re-cutting yield and display effect of the GOA display screen.

[0065] Reference Figure 7As shown, another embodiment of the present application further provides a display terminal 1, comprising the display panel 10 and the terminal body 20 described in any of the above embodiments, wherein the display panel 1 and the terminal body 3 are combined into one. The terminal body 20 may include a backlight module, which is arranged on a side of the substrate of the display panel 10 away from the GOA circuit. The backlight module is used to provide a light source for the display panel 1.

[0066] The display terminal can be: a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, or any other product or component with a display function.

[0067] Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method and core idea of ​​the present application. At the same time, for technical personnel in this field, according to the idea of ​​the present application, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. A display panel, characterized in that: include: M rows of pixels; M cascaded gate driving circuits, each of the gate driving circuits correspondingly connected to a row of pixels, and each of the gate driving circuits comprising a reset transistor; Among them, the gates of K consecutively arranged reset transistors are connected to the first metal wiring, the gates of MK consecutively arranged reset transistors are connected to the reset signal line, the first metal wiring and the reset signal line are disconnected, M and K are positive integers, and K<M.

2. The display panel according to claim 1, characterized in that: The first metal wiring and the reset signal line are formed in the same layer and made of the same material.

3. The display panel according to claim 1, characterized in that: Every N cascaded gate drive circuits from top to bottom along the scanning direction of the pixel form a group; wherein, K consecutively arranged reset transistors belong to the first group of gate drive circuits, N represents the number of drive clock signals corresponding to the display panel, K≤N, and M is an integer multiple of N.

4. The display panel according to claim 3, characterized in that: The gates of the M reset transistors share a second metal wiring, the reset signal line is arranged on a side close to the Mth reset transistor, and the second metal line is connected to the reset signal line.

5. The display panel according to claim 4, characterized in that: The second metal wiring is in a disconnected state at a position between the Kth reset transistor and the K+1th reset transistor.

6. The display panel according to claim 1, characterized in that: The first metal routing line and the reset signal line belong to the same third metal routing line, and the third metal routing line is in a disconnected state at the position of the Kth reset transistor.

7. The display panel according to claim 6, characterized in that: The third metal wiring between the gate of the Kth reset transistor and the gate of the K+1th reset transistor is in a disconnected state.

8. The display panel according to claim 3, characterized in that: K=N / 2.

9. The display panel according to claim 3, characterized in that: K=N.

10. A display terminal, characterized in that: A display panel comprising any one of claims 1 to 9.

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