Capacitor structure, isolation transformer and semiconductor device

Abstract

The invention relates to a capacitor structure, an isolation transformer and a semiconductor device. The isolation transformer comprises a lower coil first dielectric layer covering the lower coil, and the dielectric constant of the first dielectric layer is larger than that of silicon dioxide; the main dielectric layer is located on the first dielectric layer; the second dielectric layer is located on the main dielectric layer, and the dielectric constant of the second dielectric layer is larger than that of silicon dioxide; the upper coil is located on the second dielectric layer; the third dielectric layer covers the upper coil, and the dielectric constant of the third dielectric layer is larger than that of silicon dioxide. According to the invention, the upper coil is coated with the medium with high dielectric constant, and the electric field of the device is optimized (the electric field intensity is reduced), thereby achieving the purpose of improving the withstand voltage of the device.

Description

Technical Field

[0001] The invention relates to the field of semiconductor manufacturing, in particular to a capacitor structure, an isolation transformer, and a semiconductor device. Background Art

[0002] In the semiconductor integration process, an exemplary isolation transformer uses silicon dioxide as an isolation medium between its upper and lower coils. By increasing the thickness of silicon dioxide, the withstand voltage of the upper and lower coils can be improved. However, when the upper coil is etched, more defects will be caused on the surface of the etched material, resulting in the high electric field area at the position of the upper coil being prone to dielectric breakdown, thereby affecting the withstand voltage of the entire transformer. Summary of the invention

[0003] Based on this, it is necessary to provide an isolation transformer with higher withstand voltage.

[0004] An isolation transformer comprises: a first dielectric layer of a lower coil, covering the lower coil, wherein the dielectric constant of the first dielectric layer is greater than the dielectric constant of silicon dioxide; a main dielectric layer, located on the first dielectric layer; a second dielectric layer, located on the main dielectric layer, wherein the dielectric constant of the second dielectric layer is greater than the dielectric constant of silicon dioxide; an upper coil, located on the second dielectric layer; and a third dielectric layer, covering the upper coil, wherein the dielectric constant of the third dielectric layer is greater than the dielectric constant of silicon dioxide.

[0005] The isolation transformer uses a high dielectric constant medium (the second dielectric layer and the third dielectric layer) to cover the upper coil, optimize the electric field of the device (reduce the electric field strength), and thus achieve the purpose of improving the withstand voltage of the device. The first dielectric layer covers the lower coil, which can also reduce the electric field strength at the lower coil, thereby improving the withstand voltage of the device.

[0006] In one embodiment, the isolation transformer further includes a fourth dielectric layer, the lower coil is located on the fourth dielectric layer, and the dielectric constant of the fourth dielectric layer is greater than the dielectric constant of silicon dioxide.

[0007] In one embodiment, the isolation transformer further includes a buffer layer, the material of the buffer layer includes silicon oxide; the buffer layer includes: a first buffer layer located between the upper coil and the third dielectric layer, and / or a second buffer layer located between the lower coil and the first dielectric layer.

[0008] In one embodiment, the thickness of the second dielectric layer is greater than 300 nanometers.

[0009] In one embodiment, the thickness of the fourth dielectric layer is greater than 300 nanometers.

[0010] In one embodiment, the thickness of the first dielectric layer is greater than 200 nanometers.

[0011] In one embodiment, the thickness of the third dielectric layer is greater than 200 nanometers.

[0012] In one embodiment, the material of the first dielectric layer includes silicon nitride or silicon oxynitride.

[0013] In one embodiment, the material of the first dielectric layer includes silicon nitride or silicon oxynitride.

[0014] In one embodiment, the material of the second dielectric layer includes silicon nitride or silicon oxynitride.

[0015] In one embodiment, the material of the second dielectric layer includes silicon nitride or silicon oxynitride.

[0016] In one embodiment, the material of the third dielectric layer includes silicon nitride or silicon nitride oxide.

[0017] In one embodiment, the material of the third dielectric layer includes silicon nitride or silicon oxynitride.

[0018] In one embodiment, the material of the fourth dielectric layer includes silicon nitride or silicon nitride oxide.

[0019] In one embodiment, the material of the fourth dielectric layer includes silicon nitride or silicon oxynitride.

[0020] In one embodiment, the main dielectric layer includes a silicon oxide layer.

[0021] In one embodiment, the isolation transformer further includes a passivation layer, and the passivation layer covers at least a portion of the upper coil.

[0022] In one embodiment, the upper coil and the lower coil are metal coils or alloy coils.

[0023] In one embodiment, the materials of the upper coil and the lower coil include copper and aluminum.

[0024] It is also necessary to provide a semiconductor device.

[0025] A semiconductor device comprises a transformer region and a low-voltage region, wherein the low-voltage region comprises a low-voltage device, and the transformer region comprises the isolation transformer described in any one of the aforementioned embodiments.

[0026] The semiconductor device uses a high dielectric constant medium (the second dielectric layer and the third dielectric layer) to cover the upper coil, optimize the electric field of the device (reduce the electric field strength), and thus achieve the purpose of improving the withstand voltage of the device. The first dielectric layer covers the lower coil, which can also reduce the electric field strength at the lower coil, thereby improving the withstand voltage of the device.

[0027] It is also necessary to provide a capacitor structure having a higher withstand voltage.

[0028] A capacitor structure comprises: a lower plate; a first dielectric layer covering the lower plate, wherein the dielectric constant of the first dielectric layer is greater than the dielectric constant of silicon dioxide; a main dielectric layer located on the first dielectric layer; a second dielectric layer located on the main dielectric layer, wherein the dielectric constant of the second dielectric layer is greater than the dielectric constant of silicon dioxide; an upper plate located on the second dielectric layer; and a third dielectric layer covering the upper plate, wherein the dielectric constant of the third dielectric layer is greater than the dielectric constant of silicon dioxide.

[0029] The capacitor structure uses a high dielectric constant medium (the second dielectric layer and the third dielectric layer) to cover the upper plate, optimizing the electric field of the device (reducing the electric field strength), thereby achieving the purpose of improving the withstand voltage of the device. The first dielectric layer covers the lower plate, which can also reduce the electric field strength at the lower plate, thereby improving the withstand voltage of the device.

[0030] In one of the embodiments, the capacitor structure further includes a fourth dielectric layer, the lower electrode is located on the fourth dielectric layer, and the dielectric constant of the fourth dielectric layer is greater than the dielectric constant of silicon dioxide.

[0031] In one embodiment, the capacitor structure also includes a buffer layer, the material of the buffer layer includes silicon oxide; the buffer layer includes: a first buffer layer located between the upper plate and the third dielectric layer, and / or a second buffer layer located between the lower plate and the first dielectric layer.

[0032] In one embodiment, the thickness of the second dielectric layer is greater than 300 nanometers.

[0033] In one embodiment, the thickness of the fourth dielectric layer is greater than 300 nanometers.

[0034] In one embodiment, the thickness of the first dielectric layer is greater than 200 nanometers.

[0035] In one embodiment, the thickness of the third dielectric layer is greater than 200 nanometers.

[0036] In one embodiment, the material of the first dielectric layer includes silicon nitride or silicon oxynitride.

[0037] In one embodiment, the material of the first dielectric layer includes silicon nitride or silicon oxynitride.

[0038] In one embodiment, the material of the second dielectric layer includes silicon nitride or silicon oxynitride.

[0039] In one embodiment, the material of the second dielectric layer includes silicon nitride or silicon oxynitride.

[0040] In one embodiment, the material of the third dielectric layer includes silicon nitride or silicon nitride oxide.

[0041] In one embodiment, the material of the third dielectric layer includes silicon nitride or silicon oxynitride.

[0042] In one embodiment, the material of the fourth dielectric layer includes silicon nitride or silicon nitride oxide.

[0043] In one embodiment, the material of the fourth dielectric layer includes silicon nitride or silicon oxynitride.

[0044] In one embodiment, the main dielectric layer includes a silicon oxide layer.

[0045] In one embodiment, the capacitor structure further includes a passivation layer, and the passivation layer covers at least a portion of the upper plate.

[0046] In one embodiment, the upper electrode plate and the lower electrode plate are metal plates or alloy plates.

[0047] In one embodiment, the materials of the upper electrode plate and the lower electrode plate include copper and aluminum.

[0048] It is also necessary to provide a semiconductor device.

[0049] A semiconductor device comprises a capacitor region and a low voltage region, wherein the low voltage region comprises a low voltage device, and the capacitor region comprises the capacitor structure described in any one of the above embodiments.

[0050] The semiconductor device uses a high dielectric constant medium (the second dielectric layer and the third dielectric layer) to cover the upper plate, optimize the electric field of the device (reduce the electric field strength), and thus achieve the purpose of improving the withstand voltage of the device. The first dielectric layer covers the lower plate, which can also reduce the electric field strength at the lower plate, thereby improving the withstand voltage of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] In order to better describe and illustrate the embodiments and / or examples of the inventions disclosed herein, reference may be made to one or more drawings. The additional details or examples used to describe the drawings should not be considered as limiting the scope of any of the disclosed inventions, the embodiments and / or examples currently described, and the best modes of these inventions currently understood.

[0052] Figure 1 is a schematic cross-sectional structure diagram of an isolation transformer in one embodiment of the present application;

[0053] Figure 2 This is a schematic diagram of the shape of the upper coil and the lower coil in one embodiment of the present application;

[0054] Figure 3 is a schematic cross-sectional structure diagram of an isolation transformer in another embodiment of the present application;

[0055] Figure 4 is a schematic cross-sectional structure diagram of a capacitor structure in one embodiment of the present application;

[0056] Figure 5 is a schematic cross-sectional structural diagram of a capacitor structure in another embodiment of the present application;

[0057] Figure 6 It is a schematic cross-sectional structure diagram of a capacitor structure in another embodiment of the present application. DETAILED DESCRIPTION

[0058] In order to facilitate the understanding of the present invention, the present invention will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present invention are shown in the drawings. However, the present invention can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present invention more thorough and comprehensive.

[0059] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art of the present invention. The terms used herein in the specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. The term "and / or" used herein includes any and all combinations of one or more related listed items.

[0060] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers. "Connection" in this specification should be understood as "electrical connection", "communication connection" and the like if the connected circuits, modules, units, etc. have transmission of electrical signals or data to each other. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.

[0061] Spatially relative terms such as "under," "below," "below," "under," "above," "above," etc., may be used herein for ease of description to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, the spatially relative terms are intended to include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, then the elements or features described as "under other elements" or "under" or "under" will be oriented as "on" the other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. The device may be oriented otherwise (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0062] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be a limitation of the present invention. When used herein, the singular forms of "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It is understood that "at least one" refers to one or more, and "multiple" refers to two or more. "At least part of an element" refers to part or all of an element. It should also be understood that the terms "compose" and / or "comprise" when used in this specification determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0063] Embodiments of the invention are described herein with reference to cross-sectional views that are schematic diagrams of ideal embodiments (and intermediate structures) of the invention. Thus, variations from the shapes shown due to, for example, manufacturing techniques and / or tolerances can be expected. Therefore, embodiments of the invention should not be limited to the specific shapes of the zones shown herein, but include shape deviations due to, for example, manufacturing. For example, an implanted region shown as a rectangle typically has rounded or curved features and / or an implant concentration gradient at its edges, rather than a binary change from an implanted region to a non-implanted region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is performed. Therefore, the regions shown in the figures are schematic in nature, and their shapes are not intended to show the actual shape of the region of the device and are not intended to limit the scope of the invention.

[0064] Figure 1 1 is a schematic diagram of the cross-sectional structure of an isolation transformer in an embodiment of the present application. Figure 1 The semiconductor device (the area framed by the dotted line in the middle) is integrated in the semiconductor device, including the lower coil 104, the main dielectric layer 105, the first dielectric layer 122, the second dielectric layer 124, the third dielectric layer 126, the fourth dielectric layer 128 and the upper coil 101. The lower coil 104 is located on the fourth dielectric layer 128, the first dielectric layer 122 covers the lower coil 104, the main dielectric layer 105 is located on the first dielectric layer 122, the second dielectric layer 124 is located on the main dielectric layer 105, the upper coil 101 is located on the second dielectric layer 124, and the third dielectric layer 126 covers the upper coil 101. The first dielectric layer 122, the second dielectric layer 124, the third dielectric layer 126 and the fourth dielectric layer 128 are all made of materials with a relatively high dielectric constant, such as a material with a dielectric constant greater than that of silicon dioxide.

[0065] The above-mentioned isolation transformer 100 uses a high dielectric constant medium to cover the upper coil 101 and the lower coil 104 (wherein the second dielectric layer 124 and the third dielectric layer 126 cover the upper coil 101, and the fourth dielectric layer 128 and the first dielectric layer 122 cover the lower coil 104), optimizes the electric field of the device (reduces the electric field strength), thereby achieving the purpose of improving the withstand voltage of the device and can improve the surge resistance of the device.

[0066] In one embodiment of the present application, the materials of the first dielectric layer 122 , the second dielectric layer 124 , the third dielectric layer 126 and the fourth dielectric layer 128 all include silicon nitride (eg silicon nitride) or silicon oxynitride (eg silicon oxynitride).

[0067] In one embodiment of the present application, the main dielectric layer 105 includes a silicon oxide layer. The material of the main dielectric layer 105 includes silicon oxide, such as silicon dioxide. Figure 1In the embodiment shown, the device further includes a low voltage region 106 for arranging a low voltage device ( Figure 1 (not shown).

[0068] In one embodiment of the present application, the thickness of the first dielectric layer 122 and the third dielectric layer 126 is greater than 200 nanometers, which is particularly suitable for the embodiment in which the material of the first dielectric layer 122 and the third dielectric layer 126 is silicon nitride or silicon oxynitride.

[0069] In one embodiment of the present application, the thickness of the second dielectric layer 124 and the fourth dielectric layer 128 is greater than 300 nanometers, which is particularly suitable for the embodiment in which the material of the second dielectric layer 124 and the fourth dielectric layer 128 is silicon nitride or silicon oxynitride.

[0070] In one embodiment of the present application, the thicknesses of the first dielectric layer 122 , the second dielectric layer 124 , the third dielectric layer 126 , and the fourth dielectric layer 128 are all smaller than the thickness of the main dielectric layer 105 .

[0071] Figure 2 1 is a schematic diagram of the shape of the upper coil 101 and the lower coil 104 in one embodiment of the present application. Figure 1 and Figure 2 In the embodiment shown, the upper coil 101 and the lower coil 104 have the same shape. Specifically, the shape of the lower coil 104 is the positive projection of the upper coil 101 on the surface where the lower coil 104 is located, which can improve the mutual coupling coefficient of the inductance. Figure 1 and Figure 2 In the embodiment shown, the upper coil 101 and the lower coil 104 are square spirals; in other embodiments, the upper coil 101 and the lower coil 104 may also be other conventional inductor coil shapes in the art. In one embodiment of the present application, the upper coil 101 and the lower coil 104 are metal coils or alloy coils, and the main material is generally a mixture of Al and Cu. In one embodiment of the present application, the upper coil 101 and the lower coil 104 are made of the same material.

[0072] In one embodiment of the present application, the isolation transformer 100 further includes a passivation layer 102 , which covers at least a portion of the upper coil 101 and is used to protect the dielectric layer of the device and the circuit.

[0073] exist Figure 1 and Figure 2 In the illustrated embodiment, the isolation transformer 100 further includes a pad portion 107 located on the silicon oxynitride layer 103, and the pad portion 107 is electrically connected to the upper coil 101. The passivation layer 102 exposes the pad portion 107, and the pad portion 107 is used to connect the upper coil 101 to a peripheral circuit.

[0074] exist Figure 1In the illustrated embodiment, the device further includes a substrate 112. In one embodiment of the present application, the upper coil 101 and the lower coil 104 are the top metal and the inter metal layer of the device, respectively. The substrate 112 is a semiconductor substrate, and its material may be undoped single crystal silicon, single crystal silicon doped with impurities, silicon on insulator (SOI), stacked silicon on insulator (SSOI), stacked silicon germanium on insulator (S-SiGeOI), silicon germanium on insulator (SiGeOI) and germanium on insulator (GeOI), etc. It may also be at least one of the following materials: Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP or other III / V compound semiconductors. In one embodiment of the present application, the constituent material of the substrate 112 is selected from single crystal silicon. Devices, such as transistors such as NMOS and / or PMOS, may be formed on the substrate 112, Figure 1 These structures are omitted in the embodiment. Similarly, conductive components may be formed in (and on) the substrate 112. The conductive components may be gates, sources or drains of transistors, or metal interconnect structures electrically connected to transistors, etc. Figure 1 In the illustrated embodiment, a shallow trench isolation (STI) structure 114 is also formed in the substrate 112 .

[0075] exist Figure 1 In the embodiment shown, the device further includes contact holes 115 and multi-layer metal interconnection lines 116. The contact holes 115 are filled with conductive materials, such as tungsten plugs, and are electrically connected to corresponding metal interconnection lines 116 to lead out device structures such as active areas in the substrate 112.

[0076] In one embodiment of the present application, an interlayer dielectric (ILD) layer ( Figure 1 The interlayer dielectric may be a silicon oxide layer, for example, a doped or undoped silicon oxide material layer formed by a thermal chemical vapor deposition (thermalCVD) manufacturing process or a high density plasma chemical vapor deposition (HDPCVD) manufacturing process, and may specifically be undoped silicon glass (USG), phosphosilicate glass (PSG) or borophosphosilicate glass (BPSG). In addition, the interlayer dielectric may also be spin-on-glass (SOG) doped with boron or phosphorus, tetraethoxysilane doped with phosphorus (PTEOS) or tetraethoxysilane doped with boron (BTEOS).

[0077] After testing by the inventor, removal Figure 1 After the fourth dielectric layer 128 in the embodiment shown, the isolation transformer 100 still has a relatively high withstand voltage. Figure 3That is, the first dielectric layer 122 covers the lower coil 104 , which can also reduce the electric field strength at the lower coil 104 , thereby improving the withstand voltage of the device.

[0078] In one embodiment of the present application, the isolation transformer 100 further includes a buffer layer, and the material of the buffer layer includes silicon oxide, such as silicon dioxide. The buffer layer includes: a first buffer layer located between the upper coil 101 and the third dielectric layer 126, and / or a second buffer layer located between the lower coil 104 and the first dielectric layer 122. The first buffer layer is used as a buffer layer between the third dielectric layer 126 and the upper coil 101 when the third dielectric layer 126 is deposited, and can reduce defects generated when the third dielectric layer 126 is deposited. Similarly, the second buffer layer is used as a buffer layer between the first dielectric layer 122 and the lower coil 104 when the first dielectric layer 122 is deposited, and can reduce defects generated when the first dielectric layer 122 is deposited.

[0079] The present application accordingly provides a semiconductor device, which includes a transformer area and a low-voltage area 106 , in which low-voltage devices are arranged, and the transformer area includes the isolation transformer 100 described in any of the aforementioned embodiments.

[0080] Based on a general inventive concept, the present application also provides a capacitor structure with higher withstand voltage. Figure 4 2 is a schematic diagram of a cross-sectional structure of a capacitor structure 200 in an embodiment of the present application. Figure 4 The semiconductor device (the area framed by the dashed line) is integrated in the semiconductor device, including the lower plate 204, the main dielectric layer 205, the first dielectric layer 222, the second dielectric layer 224, the third dielectric layer 226, the fourth dielectric layer 228 and the upper plate 201. The lower plate 204 is located on the fourth dielectric layer 228, the first dielectric layer 222 covers the lower plate 204, the main dielectric layer 205 is located on the first dielectric layer 222, the second dielectric layer 224 is located on the main dielectric layer 205, the upper plate 201 is located on the second dielectric layer 224, and the third dielectric layer 226 covers the upper plate 201. The first dielectric layer 222, the second dielectric layer 224, the third dielectric layer 226 and the fourth dielectric layer 228 are all made of materials with a relatively high dielectric constant, such as a material with a dielectric constant greater than that of silicon dioxide.

[0081] The above-mentioned capacitor structure 200 uses a high dielectric constant dielectric to coat the upper plate 201 and the lower plate 204 (wherein the second dielectric layer 224 and the third dielectric layer 226 coat the upper plate 201, and the fourth dielectric layer 228 and the first dielectric layer 222 coat the lower plate 204), optimizes the electric field of the device (reduces the electric field strength), thereby achieving the purpose of improving the withstand voltage of the device and can improve the surge resistance of the device.

[0082] In one embodiment of the present application, the materials of the first dielectric layer 222 , the second dielectric layer 224 , the third dielectric layer 226 and the fourth dielectric layer 228 all include silicon nitride (eg silicon nitride) or silicon oxynitride (eg silicon oxynitride).

[0083] In one embodiment of the present application, the main dielectric layer 205 includes a silicon oxide layer. The material of the main dielectric layer 205 includes silicon oxide, such as silicon dioxide. Figure 4 In the embodiment shown, the device further includes a low voltage region 206 for arranging a low voltage device ( Figure 4 (not shown).

[0084] In one embodiment of the present application, the thickness of the first dielectric layer 222 and the third dielectric layer 226 is greater than 200 nanometers, which is particularly suitable for the embodiment in which the material of the first dielectric layer 222 and the third dielectric layer 226 is silicon nitride or silicon oxynitride.

[0085] In one embodiment of the present application, the thickness of the second dielectric layer 224 and the fourth dielectric layer 228 is greater than 300 nanometers, which is particularly suitable for the embodiment in which the material of the second dielectric layer 224 and the fourth dielectric layer 228 is silicon nitride or silicon oxynitride.

[0086] In one embodiment of the present application, the thicknesses of the first dielectric layer 222 , the second dielectric layer 224 , the third dielectric layer 226 , and the fourth dielectric layer 228 are all smaller than the thickness of the main dielectric layer 205 .

[0087] In one embodiment of the present application, the shape of the upper plate 201 and the lower plate 204 can be a chamfered rectangle, an ellipse, a circle or other conventional capacitor plate shapes in the art, and the shape of the upper plate 201 and the lower plate 204 can be the same. In one embodiment of the present application, the upper plate 201 and the lower plate 204 are metal plates or alloy plates, and the main material is generally a mixture of Al and Cu. In one embodiment of the present application, the material of the upper plate 201 and the lower plate 204 is the same.

[0088] In one embodiment of the present application, the capacitor structure 200 further includes a passivation layer 202, which covers at least a portion of the upper plate 201 and is used to protect the dielectric layer of the device and the circuit. Figure 4 In the illustrated embodiment, the passivation layer 202 partially exposes the upper electrode plate 201 , and the upper electrode plate 201 can be connected to the peripheral circuit through the exposed portion.

[0089] exist Figure 1In the illustrated embodiment, the device further includes a substrate 212. In one embodiment of the present application, the upper plate 201 and the lower plate 204 are the top metal and the inter metal layer of the device, respectively. The substrate 212 is a semiconductor substrate, and its material may be undoped single crystal silicon, single crystal silicon doped with impurities, silicon on insulator (SOI), stacked silicon on insulator (SSOI), stacked silicon germanium on insulator (S-SiGeOI), silicon germanium on insulator (SiGeOI) and germanium on insulator (GeOI), etc. It may also be at least one of the following materials: Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP or other III / V compound semiconductors. In one embodiment of the present application, the constituent material of the substrate 212 is selected from single crystal silicon. Devices, such as transistors such as NMOS and / or PMOS, may be formed on the substrate 212, Figure 4 These structures are omitted in the embodiment. Similarly, conductive components may be formed in (and on) the substrate 212. The conductive components may be gates, sources or drains of transistors, or metal interconnect structures electrically connected to transistors, etc. Figure 4 In the illustrated embodiment, a shallow trench isolation (STI) structure 214 is also formed in the substrate 212 .

[0090] exist Figure 4 In the embodiment shown, the device further includes contact holes 215 and multi-layer metal interconnection lines 216. The contact holes 215 are filled with conductive materials, such as tungsten plugs, and are electrically connected to corresponding metal interconnection lines 216 to lead out device structures such as active areas in the substrate 212.

[0091] In one embodiment of the present application, an interlayer dielectric (ILD) layer ( Figure 4 The interlayer dielectric may be a silicon oxide layer, for example, a doped or undoped silicon oxide material layer formed by a thermal chemical vapor deposition (thermalCVD) manufacturing process or a high density plasma chemical vapor deposition (HDPCVD) manufacturing process, and may specifically be undoped silicon glass (USG), phosphosilicate glass (PSG) or borophosphosilicate glass (BPSG). In addition, the interlayer dielectric may also be spin-on-glass (SOG) doped with boron or phosphorus, tetraethoxysilane doped with phosphorus (PTEOS) or tetraethoxysilane doped with boron (BTEOS).

[0092] After testing by the inventor, removal Figure 4 After the fourth dielectric layer 228 in the embodiment shown, the capacitor structure 200 still has a relatively high withstand voltage. Figure 5That is, the first dielectric layer 222 covers the lower electrode plate 204, which can also reduce the electric field intensity at the lower electrode plate 204, thereby improving the withstand voltage of the device.

[0093] In one embodiment of the present application, the capacitor structure 200 further includes a buffer layer, and the material of the buffer layer includes silicon oxide, such as silicon dioxide. The buffer layer includes: a first buffer layer 232 located between the upper plate 201 and the third dielectric layer 226, and / or a second buffer layer 234 located between the lower plate 204 and the first dielectric layer 222. Figure 6 The first buffer layer 232 is used as a buffer layer between the third dielectric layer 226 and the upper plate 201 when the third dielectric layer 226 is deposited, which can reduce the defects generated when the third dielectric layer 226 is deposited. Similarly, the second buffer layer 234 is used as a buffer layer between the first dielectric layer 222 and the lower plate 204 when the first dielectric layer 222 is deposited, which can reduce the defects generated when the first dielectric layer 222 is deposited.

[0094] In the description of this specification, the description with reference to the terms "some embodiments", "other embodiments", "ideal embodiments", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.

[0095] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0096] The above-mentioned embodiments only express several implementation methods of the present invention, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for ordinary technicians in this field, several variations and improvements can be made without departing from the concept of the present invention, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be subject to the attached claims.

Claims

1. An isolation transformer, characterized in that: include: Lower coil; A first dielectric layer, covering the lower coil, wherein the dielectric constant of the first dielectric layer is greater than the dielectric constant of silicon dioxide; A main dielectric layer, located on the first dielectric layer; A second dielectric layer, located on the main dielectric layer, wherein the dielectric constant of the second dielectric layer is greater than the dielectric constant of silicon dioxide; an upper coil, located on the second dielectric layer; A third dielectric layer covers the upper coil, and the dielectric constant of the third dielectric layer is greater than the dielectric constant of silicon dioxide.

2. The isolation transformer according to claim 1, characterized in that: It also includes a fourth dielectric layer, the lower coil is located on the fourth dielectric layer, and the dielectric constant of the fourth dielectric layer is greater than the dielectric constant of silicon dioxide.

3. The isolation transformer according to claim 1, characterized in that: It also includes a buffer layer, wherein the material of the buffer layer includes silicon oxide; The buffer layer includes: a first buffer layer located between the upper coil and the third dielectric layer, and / or a second buffer layer located between the lower coil and the first dielectric layer.

4. The isolation transformer according to claim 1, characterized in that: The thickness of the second dielectric layer is greater than 300 nanometers, and / or The thickness of the first dielectric layer and the third dielectric layer is greater than 200 nanometers.

5. The isolation transformer according to claim 1, characterized in that: The materials of the first dielectric layer, the second dielectric layer and the third dielectric layer all include silicon nitride or silicon nitride oxide.

6. The isolation transformer according to claim 5, characterized in that: The materials of the first dielectric layer, the second dielectric layer and the third dielectric layer all include silicon nitride or silicon oxynitride.

7. The isolation transformer according to claim 1, characterized in that: The main dielectric layer includes a silicon oxide layer.

8. A semiconductor device, comprising a transformer area and a low voltage area, wherein the low voltage area comprises a low voltage device, characterized in that: The transformer section comprises an isolation transformer as claimed in any one of claims 1 to 7.

9. A capacitor structure, characterized in that: include: Lower plate; A first dielectric layer, covering the lower electrode plate, wherein the dielectric constant of the first dielectric layer is greater than the dielectric constant of silicon dioxide; A main dielectric layer, located on the first dielectric layer; A second dielectric layer, located on the main dielectric layer, wherein the dielectric constant of the second dielectric layer is greater than the dielectric constant of silicon dioxide; An upper plate, located on the second dielectric layer; A third dielectric layer covers the upper electrode plate, and the dielectric constant of the third dielectric layer is greater than the dielectric constant of silicon dioxide.

10. A semiconductor device comprising a capacitor region and a low voltage region, wherein the low voltage region comprises a low voltage device, characterized in that: The capacitor region includes the capacitor structure of claim 9.

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