Flat plate type inductive element

Abstract

The invention provides a flat plate type inductive element which comprises a first circuit board, a second circuit board and an iron core. The first circuit board comprises a first through hole and a first combination surface, and a plurality of layers of first wires surrounding the first through hole are formed on the first circuit board. The second circuit board comprises a second through hole and a second combination surface used for being combined with the first combination surface, and multiple layers of second wires surrounding the second through hole are formed on the second circuit board. When current flows through the flat plate type inductive element, the potential of a first low-voltage end of a layer of first wires located on the first combination surface is roughly the same as the potential of a second low-voltage end of a layer of second wires located on the second combination surface. And the potential of the first high-voltage end of the layer of first wire located on the first bonding surface is roughly the same as the potential of the second high-voltage end of the layer of second wire not located on the second bonding surface.

Description

Technical Field

[0001] The invention relates to a flat plate inductive element, in particular to a flat plate inductive element formed by stacking multiple circuit boards. Background Art

[0002] With the rapid development of the information industry, power supplies or circuits related to power conversion have played an indispensable role. In power supplies or circuits related to power conversion, they basically include inductive components such as inductors and transformers, and their main function is to control the coupling and flow of energy through the switching of switches. Generally speaking, the structure of a traditional wound inductor or transformer usually includes a combination of an iron core, an enameled wire coil, an insulating tape and / or a bobbin. The manufacturing process requires the use of a winding machine to wind the enameled wire on a bobbin or an iron core, and then it is insulated and assembled with a coating tape, and then it can be completed through processes such as impregnation and dispensing. Therefore, traditional inductors or traditional transformers are nothing more than large size, cumbersome manufacturing procedures, and high costs.

[0003] For this reason, in the technical field of power electronics, flat-type inductors and flat-type transformers (hereinafter referred to as flat-type inductive elements) that use the wiring of the circuit board as a coil have gradually developed. Specifically, the flat-type inductive element uses the copper foil wiring of the circuit board as a coil, replacing the winding frame and enameled wire process, and has the advantages of being light, thin, small in size, easy to produce, and highly stable. However, since the copper foil wiring needs to wrap around the periphery of the iron core, it is limited by design parameters such as the size of the iron core and the number of turns, and the copper foil wiring often does not have enough width, resulting in a higher impedance value. In addition, most circuit boards are designed with multi-layer boards, which makes it difficult for the inner layer of the circuit board to conduct heat, resulting in the copper foil coil temperature being too high.

[0004] Specifically, since the flat inductive element is formed on a single circuit board, the impedance of the copper foil trace T of the circuit board can be equivalent to Figure 1 As shown. Figure 1 In the figure, it is assumed that the equivalent impedance R of the coil W is 1 ohm, and the current I flowing through the planar inductive element 100 is 3A. Therefore, the power loss (Ploss = I2*R) of the current I flowing through the coil W can be calculated to be (3*3)*1 = 9W. Therefore, the impedance value of the coil W is related to the amount of power loss. In addition, these power losses will cause the coil W to heat up, so the accumulation of this heat in the inner layer of the circuit board with poor heat dissipation will cause the copper foil coil to be overheated.

[0005] Therefore, how to provide a planar inductive element to reduce the total impedance of the wiring and reduce the loss of the planar inductive element and reduce the heat loss is an issue that needs to be urgently addressed in the art. Summary of the invention

[0006] In order to solve the above problems, the present invention provides a flat inductive element to overcome the problems of the conventional technology. Therefore, the flat transformer of the present invention includes a first circuit board, a second circuit board and an iron core. The first circuit board includes a first coil, a first through-hole and a first bonding surface, the first coil includes multiple layers of first wiring, and the first wiring is respectively surrounded by the first through-hole. The second circuit board includes a second coil, a second through-hole and a second bonding surface for bonding the first bonding surface, the second coil includes multiple layers of second wiring, and the second wiring is respectively surrounded by the second through-hole. The iron core includes a first iron core column. Among them, the first coil is electrically connected to the second coil to form a parallel structure, and the first iron core column is penetrated through the first through-hole and the second through-hole to form a flat inductive element. Among them, a first routing layer in the multi-layer first routing located on the first bonding surface has a first high voltage end and a first low voltage end, and a second routing layer in the multi-layer second routing located on the second bonding surface has a second high voltage end and a second low voltage end; when current flows through the planar inductive element, the potentials of the first low voltage end and the second low voltage end are substantially the same, and the potentials of the first high voltage end and the second high voltage end are substantially the same.

[0007] In one embodiment, the first routing line of the layer located at the first bonding surface and the second routing line of the layer located at the second bonding surface are mirror-configured, so that the potential of any specific point of the first routing line of the layer located at the first bonding surface is the same as the potential of the position at the same specific point in the second routing line of the layer located at the second bonding surface.

[0008] In one embodiment, on the plane defined by the X-axis and the Y-axis, the first routing line of the layer located at the first bonding surface and the second routing line of the layer located at the second bonding surface are mirror-imaged; so that the first routing line of the layer located at the first bonding surface and the second routing line of the layer located at the second bonding surface have the same potential at positions corresponding to the same X-axis coordinate value and Y-axis coordinate value along the Z-axis direction, wherein the X-axis, Y-axis, and Z-axis are perpendicular to each other.

[0009] In one embodiment, current flows from the end of the first wiring of the layer located at the first bonding surface and the end of the second wiring of the layer not located at the second bonding surface, so that the first bonding surface and the second bonding surface are both high-voltage layers.

[0010] In one embodiment, the current flows out from the end of the first wiring of the layer located at the first bonding surface and the end of the second wiring of the layer located at the second bonding surface, so that the first bonding surface and the second bonding surface are both low-voltage layers.

[0011] In one embodiment, the impedance of the multi-layer first routing lines in each layer is substantially equal to the impedance of the multi-layer second routing lines in the corresponding layer.

[0012] In one embodiment, the impedance of the outer layer of the second circuit board is greater than the impedance of each layer within the outer layer of the second circuit board.

[0013] In one embodiment, the end of the first routing layer located at the first joint surface forms the first end of the first coil, and the end of another first routing layer in the multi-layer first routing layer away from the first routing layer forms the second end of the first coil. The end of another second routing layer in the multi-layer second routing layer away from the second routing layer forms the third end of the second coil, and the end of the second routing layer in the second joint surface forms the fourth end of the second coil. The first end is electrically connected to the fourth end, and the second end is electrically connected to the third end to form a parallel structure.

[0014] In one embodiment, the planar inductive element is a planar inductor, and the first coil and the second coil form an inductor coil in a parallel structure.

[0015] In one embodiment, the planar inductive element is a planar transformer, and the first coil and the second coil form one of the primary side coil or the secondary side coil of a parallel structure.

[0016] In one embodiment, the other of the primary side coil or the secondary side coil is disposed on the first circuit board or the second circuit board, so that the first core column is passed through the first through hole and the second through hole to form a flat-plate transformer.

[0017] In one embodiment, the core further includes a second core column, and the other of the primary side coil or the secondary side coil is configured on a third circuit board; the first core column is penetrated through the first through hole and the second through hole, and the second core column is penetrated through the third through hole of the third circuit board to form a flat-plate transformer.

[0018] The main purpose and effect of the present invention is that the first and second traces of the flat-plate inductive element are electrically connected in parallel in structure and placed in the same iron core, so that the current flowing through the flat-plate inductive element can be shunted (or regarded as reducing the total impedance of the traces). In this way, the effect of reducing power loss and heat loss can be achieved.

[0019] In order to further understand the techniques, means and effects adopted by the present invention to achieve the predetermined objectives, please refer to the following detailed description and drawings of the present invention. It is believed that the objectives, features and characteristics of the present invention can be deeply and specifically understood thereby. However, the drawings are only provided for reference and illustration and are not intended to limit the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 is a schematic diagram of an equivalent circuit of a conventional planar inductive element;

[0021] Figure 2 is a schematic diagram of an equivalent circuit of a flat-plate inductive element of the present invention;

[0022] Figure 3A is a circuit structure diagram of the first circuit board of the present invention;

[0023] Figure 3B is a circuit structure diagram of the second circuit board of the present invention;

[0024] Figure 4A A top view schematic diagram of the topmost wiring configuration of the first circuit board of the present invention;

[0025] Figure 4B A top perspective schematic diagram of the bottom layer wiring configuration of the second circuit board of the present invention;

[0026] Figure 4C A bottom view schematically showing the wiring arrangement of the bottom layer of the second circuit board of the present invention;

[0027] Figure 5A It is a cross-sectional view along the first axis after the first circuit board and the second circuit board of the present invention are stacked;

[0028] Figure 5B It is a structural exploded diagram of the flat-plate inductive element of the present invention;

[0029] Fig. 6A It is a schematic diagram of an equivalent circuit of a wiring portion of a circuit board of the present invention;

[0030] Figure 6B for Fig. 6A The equivalent circuit diagram of the wiring when the flat-type inductive element operates;

[0031] Fig. 7A It is a schematic diagram of an equivalent circuit of the first embodiment of the present invention after the wiring parts of the first circuit board and the second circuit board are stacked;

[0032] Figure 7B It is a schematic diagram of an equivalent circuit of a second embodiment of the present invention after the wiring parts of the first circuit board and the second circuit board are stacked;

[0033] Figure 7C The equivalent circuit diagram of the third embodiment of the present invention after the wiring parts of the first circuit board and the second circuit board are stacked

[0034] Figure 8 It is a cross-sectional view of one embodiment of a planar transformer of the present invention.

[0035] Wherein, the reference numerals are:

[0036] 100: Flat-type inductive element

[0037] W: Coil

[0038] 1: First circuit board

[0039] 12: Wiring Department

[0040] H1: First piercing

[0041] 14: Connection

[0042] T1, T1_1~T1_4: First wiring

[0043] T1_1_H: first high voltage terminal

[0044] T1_1_L: first low voltage terminal

[0045] W1: First coil

[0046] W1-1: First end

[0047] W1-2: Second end

[0048] 16: Circuit Department

[0049] Ts: Specific routing

[0050] 2: Second circuit board

[0051] 22: Wiring Department

[0052] H2: Second piercing

[0053] 24: Connection

[0054] T2, T2_1~T2_4: Second wiring

[0055] T2_N_H: Second high voltage terminal

[0056] T2_N_L: Second low voltage terminal

[0057] W2: Second coil

[0058] W2-1: The third end

[0059] W2-2: The fourth end

[0060] via:through hole

[0061] L1~L4、LA、LB: Layer

[0062] 18: First joint surface

[0063] 28: Second joint surface

[0064] 3: The third circuit board

[0065] H3: The third perforation

[0066] T3_1~T3_4: The third routing

[0067] W3: The third coil

[0068] W3-1: The fifth terminal

[0069] W3-2: The Sixth Terminal

[0070] 38: The third joint surface

[0071] 48: Fourth joint surface

[0072] WP: Primary coil

[0073] WS: Secondary coil

[0074] C: Iron core

[0075] C-1: The first core piece

[0076] C-2: Second core piece

[0077] C1: First core column

[0078] C2: Second core column

[0079] I: Current

[0080] R: equivalent impedance

[0081] V1~V4: voltage

[0082] E1: First span pressure

[0083] E2: Second span pressure

[0084] E3: Third span pressure

[0085] E4: Fourth span pressure

[0086] A1: First axis

[0087] A2: Second axis DETAILED DESCRIPTION

[0088] The technical content and detailed description of the present invention are described below with reference to the accompanying drawings:

[0089] See also Figure 2 is a schematic diagram of an equivalent circuit of a flat-plate inductive element of the present invention, and is referred to in conjunction with Figure 1 One of the purposes and effects of the present invention is that the planar inductive element 100 is connected in parallel by two circuit boards, with the first coil W1 as the main coil and the second coil W2 as the auxiliary coil, so that the copper loss caused by the DC resistance (DCR) of the planar inductive element 100 can be reduced, thereby reducing the temperature of the planar inductive element 100 during operation (i.e., the heat caused by the loss). Specifically, in Figure 1Under the same conditions (i.e. the equivalent impedance R of coil W is 1 ohm, and the current I flowing through the planar inductive element is 3A), the equivalent impedance R of the first coil W1 is 1 ohm, and the equivalent impedance R of the second coil W2 is the same as the first coil W1, so that the two coils connected in parallel can evenly divide the current I (i.e. the first coil W1 and the second coil W2 each flow through a current of 1.5A). Therefore, their respective power losses are (1.5*1.5)*1=2.25, and the sum of the power losses of the two is 4.5W. Therefore, it can be clearly seen that the planar inductive element 100 of the present invention can halve the power loss of the current I flowing through the coils W1 and W2 by connecting the two coils W1 and W2 in parallel (i.e. Figure 1 The 9W is reduced to Figure 2 4.5W), and accordingly reduce the heat caused by losses.

[0090] See also Figure 3A is a circuit structure diagram of the first circuit board of the present invention, and Figure 3B The circuit structure diagram of the second circuit board of the present invention is shown in FIG. Figure 1 . Figure 3A Main presentation Figure 2 The first circuit board 1 includes the first coil W1, the first through hole H1, the routing portion 12, the connecting portion 14 and the first joint surface 18 that can be used to form the planar inductive element 100. The first coil W1 includes multiple layers of first routing wires T1_1 to T1_N from top to bottom, and the multiple layers of first routing wires T1_1 to T1_N surround the first through hole H1 respectively. The multiple layers of first routing wires T1_1 to T1_N are connected in series in sequence, and the two ends of the entire set of serial routing wires are electrically connected to the connecting portion 14 (directly connected or connected to other layers through holes such as but not limited to through holes, blind holes, buried holes, etc., and then connected by routing wires of other layers).

[0091] Related References Figure 4A The top first wiring T1_1 among the multiple layers of first wirings T1_1 - T1_N of the first coil W1 is located on the first bonding surface 18 , and the top first wiring T1_1 has a first high voltage end T1_1_H and a first low voltage end T1_1_L.

[0092] Figure 3B Main presentation Figure 2The second circuit board 2 includes a second coil W2, a second through hole H2, a routing portion 22, a connecting portion 24 and a second joint surface 28 that can be used to form a planar inductive element 100. The second coil W2 includes multiple layers of second routing wires T2_1 to T2_N from top to bottom, and the multiple layers of second routing wires T2_1 to T2_N surround the second through hole H2 respectively. The multiple layers of second routing wires T2_1 to T2_N are connected in series with each other, and both ends of the entire set of serial routing wires are electrically connected to the connecting portion 24 (directly connected or connected to other layers through holes such as but not limited to through holes, blind holes, buried holes, etc., and then connected by routing wires of other layers).

[0093] Related References Figure 4B , 4C , the top perspective schematic diagram and the bottom schematic diagram of the bottom layer wiring configuration in the second circuit board, the bottom layer second wiring T2_N among the multiple layers of second wiring T2_1~T2_N of the second coil W2 is located on the second bonding surface 28, and the bottom layer second wiring T2_N has a second high voltage end T2_N_H and a second low voltage end T2_N_L.

[0094] It is worth mentioning that, in one embodiment, the number of turns of the first trace T1 around the first through hole H1 can be adjusted according to actual needs (such as but not limited to parameters such as inductance and turns ratio), and due to the characteristics of the planar inductive element 100 formed on the circuit board, the number of turns can be a non-integer number to facilitate fine-tuning of parameters.

[0095] The first circuit board 1 may be a main circuit board, and it may also include a circuit part 16 for configuring circuit elements. The second circuit board 2 may be an auxiliary circuit board, mainly used to provide another set of coils W2, and thus may selectively include a circuit part ( Figure 3B In addition, Figure 4A In the embodiment, the wiring section 12 can also form an additional specific wiring Ts. The specific wiring Ts can mainly be used to sense voltage and current by coupling the first wiring T1 or the second wiring T2. Therefore, the specific wiring Ts can be used for detection (for example, but not limited to, as a coil for sensing current size such as a current transformer), or used to obtain coupled energy to power components such as, but not limited to, a controller. On the other hand, although Figure 4B Although not specifically shown, the wiring portion 22 may also be as Figure 4A The implementation method is used to form additional routing (for example, but not limited to, specific routing Ts), which will not be described in detail here.

[0096] Related References Figure 5A is a cross-sectional view along the first axis after the first circuit board and the second circuit board are stacked, and is also referred to in conjunction with Figures 2 to 4B . Figure 5AThe circuit structure is mainly composed of a flat plate type inductive element 100, and then used as Figure 4B A cross-sectional view taken along the first axis A1. Figure 5A In the present invention, the flat inductive element 100 further includes an iron core C, and the iron core C includes a first iron core member C-1, a second iron core member C-2, and a first iron core column C1. The present invention mainly stacks the second circuit board 2 on one side of the first circuit board 1, and after the first iron core member C-1 and the second iron core member C-2 of the iron core C are combined, the first iron core column C1 is penetrated through the first through hole H1 and the second through hole H2 to form a flat inductive element. Among them, the iron core C has Figure 5A In addition to the UT type shown, it can also be, for example but not limited to, an EE type, an EI type, a U type, etc. iron core, which is not limited here. When the second circuit board 2 is stacked on one side of the first circuit board 1, the connecting portion 24 is also stacked on one side of the connecting portion 14. Therefore, the connecting portions 14 and 24 can be electrically connected by, for example but not limited to, welding, tinning, etc., so as to electrically connect the first coil W1 to the second coil W2 to form a parallel structure of the two coils.

[0097] On the other hand, after the two circuit boards 1 and 2 are stacked, the first core column C1 is passed through, so that the core C is covered with two coils W1 and W2 to form a flat inductive element 100. Therefore, the present invention electrically connects the first coil W1 and the second coil W2 of the flat inductive element 100 in parallel in structure and places them in the same core C, so that the current can be shunted (or regarded as reducing the total impedance of the wiring), thereby reducing power loss and heat loss. In addition, in order to facilitate the sheathing of the core C, the wiring parts 12 and 22 are preferably of the same shape, and the first through hole H1 and the second through hole H2 can also be through holes of the same shape, but it is not limited to this.

[0098] See also Figure 5B The structural exploded diagram of the flat-plate inductive element of the present invention is shown in FIG. Figure 2-5A . Figure 5B Mainly for Figure 5A The stack structure is exploded into a three-dimensional structure diagram, and thus the X-axis, Y-axis, and Z-axis are defined to be perpendicular to each other. Moreover, on the plane defined by the X-axis and the Y-axis, the bonding surfaces of the first circuit board 1 and the second circuit board 2 are the first bonding surface 18 and the second bonding surface 28. Moreover, it can be seen from the three-dimensional structure that the first core member C-1 is a structure in which the first core column passes through the first through hole H1 and the second through hole H2, and the second core member C-2 can just fit the structure on the side of the routing portion 12, 22. In this way, after the first core member C-1 and the second core member C-2 are combined, the first circuit board 1 and the second circuit board 2 can be fixed to prevent them from being unstable and shaking.

[0099] Furthermore, see Figure 4A , 4B, on the plane defined by the X-axis and the Y-axis, the first wiring T1_1 of the top layer of the first coil W1 and the second wiring T2_4 of the bottom layer of the second coil W2 are mirror-imaged. Therefore, when the potentials of the first low voltage terminal T1_1_L and the second low voltage terminal T2_N_L are substantially the same, and the potentials of the first high voltage terminal T1_1_H and the second high voltage terminal T2_N_H are substantially the same, then the first wiring T1_1 of the first bonding surface 18 and the second wiring T2_N of the second bonding surface 28 have the same potentials corresponding to the same X-axis coordinate value and Y-axis coordinate value positions along the Z-axis direction.

[0100] See also Fig. 6A is a schematic diagram of an equivalent circuit of the first coil W1 of the circuit board of the present invention, Figure 6B for Fig. 6A The equivalent circuit diagram when a total voltage of 400V is applied to both ends of the first coil W1 is shown in Figure 1. Figure 2 ~5. Fig. 6A The first circuit board 1 is used as an illustrative example with four layers of material, but the present invention is not limited thereto. Therefore, the first circuit board 1 and the second circuit board 2 of the present invention can actually have two layers of material or more than two layers of material, and the number of layers of the first circuit board 1 and the second circuit board 2 can also be different.

[0101] Related References Figure 3A , 4A , 6A, 7A, the first circuit board 1 has a first plate layer L1 (top layer), a second plate layer L2, a third plate layer L3 and a fourth plate layer L4 (bottom layer) from top to bottom. On the above four plates, first traces T1_1 to T1_4 surrounding the first through hole H1 are formed respectively. These four first traces T1_1 to T1_4 can be connected in series through vias to form a first coil W1, and the end of the first trace T1_1 of the first plate layer L1 forms the first end W1-1 of the first coil W1, and the end of the first trace T1_4 of the fourth plate layer L4 forms the second end W1-2 of the first coil W1.

[0102] The second circuit board 2 is similar to this. The second circuit board 2 has a first layer of plate L1 (top layer), a second layer of plate L2, a third layer of plate L3 and a fourth layer of plate L4 (bottom layer) from top to bottom. On the above four layers of plate, second traces T2_1 to T2_4 surrounding the second through hole H2 are formed respectively. These four layers of second traces T2_1 to T2_4 can be connected in series through the via to form a second coil W2, and the two ends of the second coil W2 are the third end W2-1 and the fourth end W2-2.

[0103] exist Figure 6BIn the figure, it is assumed that when the planar inductive element 100 is in operation, the total voltage across the first end W1-1 to the second end W1-2 is 400V, and the impedance of the first traces T1_1 to T1_4 of each layer is the same. Therefore, the partial voltage across V1 to V4 borne by the first traces T1_1, T1_2, T1_3, and T1_4 of each layer is 100V (i.e., one-fourth of the total voltage across 400V). In this case, the voltage difference between the first plate L1 (top layer) and the fourth plate L4 (bottom layer) is at least 200V (i.e., it spans the voltage across the second plate L2 and the third plate L3), and the maximum voltage difference of the first coil W1 is 400V (i.e., the total voltage across).

[0104] Related References Fig. 7A This is a schematic diagram of an equivalent circuit of the first embodiment of the present invention in which the first coil W1 and the second coil W2 are connected in parallel after the first circuit board 1 and the second circuit board 2 are stacked. When the stack of the first circuit board 1 and the second circuit board 2 is combined, the first circuit board 1 has a first bonding surface 18 (i.e., the bottom surface of the first circuit board 1) close to the second circuit board 2, and the second circuit board 2 also has a second bonding surface 28 (i.e., the top surface of the second circuit board 2) close to the first circuit board 1. Therefore, the topmost first wiring T1_1 of the first coil W1 on the bonding surface 18 and the bottommost second wiring T2_4 of the second coil W2 on the bonding surface 28 are short and quite close to each other, and the two are insulated only by the thin insulating paint coated on the surfaces of the circuit boards 1 and 2.

[0105] However, if the voltage difference between the two coils is too large (for example but not limited to Figures 6A-6B The total voltage across the board is V400V). When the two circuit boards 1 and 2 are directly bonded together, the high voltage layer (i.e., the first layer L1) of the first circuit board 1 will bond with the low voltage layer (i.e., the fourth layer L4) of the second circuit board 2, making the voltage across the two layers as high as 400V, which may cause spark damage between the contact surfaces of the two circuit boards 1 and 2. However, if the bonding surface is not specially insulated by thickening its surface paint, the insulation will inevitably result in insufficient insulation. In addition, if tape or other insulation mechanisms are required, the cost and work time will increase.

[0106] Therefore, please refer to Figure 7B This is a schematic diagram of an equivalent circuit of the second embodiment of the present invention after the wiring parts of the first circuit board and the second circuit board are stacked. The present invention electrically connects the second end W1-2 of the bottom layer of the first coil W1 to the third end W2-1 of the top layer of the second coil W2, and the first end W1-1 of the top layer of the first coil W1, located on the bonding surface 18, is electrically connected to the fourth end W2-2 of the bottom layer of the second coil W2, located on the bonding surface 28, so that the first coil W1 and the second coil W2 form a parallel structure through the above-mentioned electrical connection. In this way, Fig. 7AAs shown in FIG. 1 , when the first terminal W1-1 is a ground terminal, the fourth terminal W2-2 is also a ground terminal. Figure 7B As shown, when the first terminal W1 - 1 receives a 400V voltage, the fourth terminal W2 - 2 also receives a 400V voltage.

[0107] Therefore, if Fig. 7A For the structure, when the current I flows from the first end W1-1 and the fourth end W2-2 to the ground end, the first joint surface 18 is a low-voltage layer, and the voltage across the two ends of the first line T1_1 (i.e., the part of the line located on the first layer of the first circuit board 1) is E1 (i.e., the voltage across the two ends of the first line T1_1 changes from the ground 0V to 100V). Similarly, the second joint surface 28 is also a low-voltage layer, and the voltage across the two ends of the second line T2_4 (i.e., the part of the line located on the fourth layer of the second circuit board 2) is E2 (i.e., the voltage across the two ends of the second line T2_4 changes from the ground 0V to 100V). Therefore, the voltage across the two ends of the first line T1_1 E1 and the voltage across the two ends of the second line T2_4 can be made to have substantially the same range (i.e., the upper and lower limits of the voltage range at the two ends of the line are 100V and 0V, respectively). The “substantially” mentioned herein means that it can accept a pressure difference of, for example, but not less than, plus or minus 5%. The same descriptions that appear in the following text can be deduced accordingly and will not be repeated here.

[0108] Similarly, if Figure 7B For the architecture, when the current I flows from the first end W1-1 and the fourth end W2-2 into the traces T1 and T2, the first bonding surface 18 is a high-voltage layer, and the voltage across the two ends of the first trace T1_1 is E1 (i.e., the voltage across the two ends of the first trace T1_1 changes from 300V to 400V). The second bonding surface 28 is also a high-voltage layer, and the voltage across the two ends of the second trace T2_4 is E2 (i.e., the voltage across the two ends of the second trace T2_4 also changes from 300V to 400V). Therefore, the voltage across E1 across the two ends of the first trace T1_1 and the voltage across E2 across the two ends of the second trace T2_4 can also be made to have roughly the same variation range (i.e., the upper and lower limits of the voltage range at the two ends of the traces are 400V and 300V, respectively). Therefore, if you use the following Fig. 7A , 7B With the circuit configuration shown, the voltage difference between the two traces T1 and T2 is not too large, so there is no concern of sparking or damage to the flat inductive element 100 even if it is insulated only by the basic surface insulating paint of the circuit boards 1 and 2. The joint surface does not need to be specially insulated with thicker surface paint, or with additional tape or other insulating mechanisms, which can avoid increasing costs and work hours.

[0109] In addition, the potentials of the first traces T1_1 to T1_4 of each layer and the second traces T2_4 to T2_1 of the corresponding layer (for example but not limited to, the first trace T1_2 of the second layer of the board L2 corresponds to the second trace T2_3 of the third layer of the board L3, and so on) of any layer are roughly the same. For example but not limited to, Fig. 7A The potential of the through hole via point of the first trace T1_2 of the second layer board L2 is substantially the same as the potential of the through hole via point of the second trace T2_3 of the third layer board L3, and so on, which will not be repeated here.

[0110] In detail, Figures 7A-7B In the embodiment, the first wiring T1_1 located at the first bonding surface 18 has a first high voltage end and a first low voltage end (with Fig. 7A For example, the ground terminal is the first low voltage terminal, and the other end of the ground terminal at 100V is the first high voltage terminal), so that the voltage E1 of the first wiring T1_1 of the first joint surface 18 varies from the first low voltage terminal to the first high voltage terminal in the range of 0 to 100V. The second wiring T2_4 located at the second joint surface 28 also has a second high voltage terminal and a second low voltage terminal (with Fig. 7A For example, the ground terminal is the second low voltage terminal, and the other end of the ground terminal at 100V is the second high voltage terminal), so that the cross voltage E2 of the second wiring T2_4 of the second bonding surface 28 also changes from the second low voltage terminal to the second high voltage terminal in the range of 0 to 100V. The cross voltage E1 and the cross voltage E2 are substantially the same. The cross voltage refers to that the potentials of the first low voltage terminal and the second low voltage terminal are both grounded and substantially the same, and the potentials of the first high voltage terminal and the second high voltage terminal are both 100V and substantially the same. In addition, the cross voltages at corresponding points between the high voltage terminal and the low voltage terminal are also substantially the same.

[0111] In addition, Figure 7C In, mainly in Fig. 7A A third circuit board 3 is additionally added to the structure, and the third circuit board 3 is similar to the first circuit board 1 or the second circuit board 2. Specifically, the third circuit board 3 includes a third coil W3, and the two ends of the third coil W3 respectively form a fifth end W3-1 and a sixth end W3-2. In addition, the third coil W3 is formed by third traces T3_1 to T3_4, and the first circuit board 1 and the third circuit board 3 are also stacked to form a third bonding surface 38 and a fourth bonding surface 48. Among them, the circuit structure and characteristics of the first circuit board 1 and the second circuit board 2 are the same as Fig. 7A On the other hand, the circuit structure and characteristics of the first circuit board 1 and the third circuit board 3 are the same as Figure 7B .

[0112] That is, when the current I flows from the second end W1-2 and the fifth end W3-1 into the traces T1_4 and T3_1, the third joint surface 38 is a high-voltage layer, and the voltage across the two ends of the first trace T1_4 of the fourth layer of plate L4 is E3 (i.e., the voltage across the two ends of the first trace T1_4 changes from 300V to 400V). The fourth joint surface 48 is also a high-voltage layer, and the voltage across the two ends of the third trace T3_1 of the third coil W3 is E4 (i.e., the voltage across the two ends of the third trace T3_1 also changes from 300V to 400V). Therefore, the third voltage across E3 and the fourth voltage across E4 can also have roughly the same range of variation (i.e., the upper and lower limits of the voltage range at both ends of the traces are 400V and 300V, respectively).

[0113] For further information, please refer to Figure 4A , 4B If the first wiring T1_1 of the first bonding surface 18 and the second wiring T2_4 of the second bonding surface 28 of the planar inductive element 100 of the present invention can be arranged in a mirror image, a better effect can be achieved. Specifically, assuming Figure 4A , 4B The first and second traces T1_1 and T2_4 are respectively connected by the two connecting surfaces 18 and 28, and the shapes of the first and second traces T1_1 and T2_4 are exactly the same as the number of turns around the through holes H1 and H2, so that the first and second traces T1_1 and T2_4 are mirror images. Therefore, when the two connecting surfaces 18 and 28 are connected, the first and second traces T1_1 and T2_4 can be completely overlapped and stacked. Also because the two are in a mirror configuration, when the current I flows through the first trace T1_1 and the second trace T2_4 of the two bonding surfaces 18 and 28, there is almost no voltage difference between any specific point of the first trace T1_1 and the position of the second trace T2_4 at the same specific point, so that the potentials of the two same points are the same (for example, the potential of the first trace T1_1 at a certain point on the bonding surface 18 is 50V, then the potential of the second trace T2_4 at the same point on the bonding surface 28 should also be 50V), so the requirements for the thickness of its surface paint will be lower.

[0114] Furthermore, see Figure 5B X, Y, and Z axes. On the plane defined by the X-axis and the Y-axis, the first trace T1_1 and the second trace T2_4 are in a mirror-image configuration. Therefore, the first trace T1_1 of the first bonding surface 18 and the second trace T2_4 of the second bonding surface 28 have the same potential corresponding to the same X-axis coordinate value and Y-axis coordinate value position along the Z-axis direction. Similarly, if the first traces T1_2 to T1_4 of other layers and the second traces T2_3 to T2_1 of the corresponding layers are also in a mirror-image configuration, the first traces T1_2 to T1_4 and the second traces T2_3 to T2_1 will also have the same potential corresponding to the same X-axis coordinate value and Y-axis coordinate value position along the Z-axis direction.

[0115] It is worth mentioning that Fig. 7A , 7B In the figure, only the impedance of each layer of the first trace T1_1~T1_4 and the second trace T2_1~T2_4 is shown, so that the voltage divided by each layer is exactly 1 / 4. However, the impedance of each layer of the first trace T1_1~T1_4 and the second trace T2_1~T2_4 can be different, so that the voltage divided by each layer is different. For example but not limited to, the impedance distribution of the first trace T1_1~T1_4 in the four-layer board is 0.5, 0.5, 2, 1, then the voltage V1~V4 divided by each layer should be 50V, 50V, 200V, 100V. Therefore, as long as the impedance formed by the first traces T1_1 to T1_4 on each layer of the first circuit board 1 is substantially equal to the impedance formed by the second traces T2_4 to T2_1 on the corresponding layer of the second circuit board 2 (i.e., the first traces T1_1 to T1_4 correspond to the second traces T2_4 to T2_1 respectively), the present invention can be achieved. Figures 7A-7B efficacy.

[0116] On the other hand, in one embodiment, the impedance of the traces T1_1 to T1_4, T2_1 to T2_4 is related to the number of turns of the traces T1_1 to T1_4, T2_1 to T2_4 on each layer around the through holes H1 and H2 and the thickness of the traces T1_1 to T1_4, T2_1 to T2_4. However, except that the traces T1_1 and T2_4 on the bonding surfaces 18 and 28 are mirror images to achieve special effects, the impedance size is mainly considered for the other layers, so the number of turns of the traces T1_2 to T1_4, T2_1 to T2_3 on each layer and the thickness of the traces T1_2 to T1_4, T2_1 to T2_3 are not limited to have a corresponding relationship. On the contrary, if the number of turns of the traces T1_2 ˜ T1_4 , T2_1 ˜ T2_3 of the corresponding layers and the thickness of the traces T1_2 ˜ T1_4 , T2_1 ˜ T2_3 are the same, it can be reasonably inferred that the impedances of the two corresponding layers should be the same.

[0117] Furthermore, due to the characteristics of the circuit board, the heat dissipation effect of the layer material on the surface or closer to the outer layer is usually better. On the contrary, the heat dissipation effect of the layer material closer to the inner layer is generally poorer because there are one or more layers of other layer materials stacked above and below it. Therefore, the first traces T1_1~T1_4, T2_1~T2_4 of each layer of the first circuit board 1 of the present invention can use this feature to increase the heat dissipation effect. That is, the number of turns and the thickness of the first traces T1_1, T1_4 (especially the first trace T1_4 of the fourth layer of the plate L4) of the first layer of the plate L1 of the first circuit board 1 can be designed to have a higher impedance (for example, but not limited to configuring the first trace T1_4 with a larger number of turns), and the impedance of the second layer of the plate L2 and the third layer of the plate L3 can be reduced accordingly to achieve the effect of improving the heat dissipation efficiency. The design of the second circuit board 2 is also the same, and it will not be repeated here.

[0118] On the other hand, see Figures 7A to 7C , since the circuit boards 1 and 2 of the present invention are four-layer boards, they can be increased or decreased according to actual needs. For example, but not limited to, the second layer of board L2 and the third layer of board L3 are reduced in the circuit boards 1 and 2. Alternatively, the second circuit board 2 is additionally provided with two layers of boards LA and LB ( Figures 7A to 7C The six-layer board is formed by the virtual frame. And the other wirings can be arranged on the additional layers of board LA and LB. The first circuit board 1 or the third circuit board 3 is deduced by analogy, and will not be described in detail here.

[0119] Related References Figures 3A to 7C , the planar inductive element 100 of the present invention can be a planar inductor or a planar transformer. Specifically, when the planar inductive element 100 is a planar inductor, a parallel structured inductive coil (i.e., a coil assembly) can be formed by connecting the first coil W1 and the second coil W2 in parallel, and the planar inductor is then formed by sleeved iron core C. When the planar inductive element 100 is a planar transformer, a parallel structured primary coil or secondary coil (i.e., a primary coil or a secondary coil assembly) can be formed by connecting the first coil W1 and the second coil W2 in parallel. Furthermore, the primary coil or the other of the secondary coils can be configured in a variety of ways.

[0120] Specifically, see Figures 7A to 7C The primary coil or the other of the secondary coils may be arranged on an additional layer of sheet material LA, LB or the like. Figure 7C The additional circuit board (ie, the third circuit board 3) is configured to form a flat-plate transformer by having the first core column C1 pass through the first through hole H1 and the second through hole H2. Figure 4AThe other of the primary side coil or the secondary side coil can be a specific trace Ts and arranged on the same layer as the first traces T1_1 to T1_4 (or the second traces T2_1 to T2_4), and can also form a flat-plate transformer by passing the first core column C1 through the first through hole H1 and the second through hole H2.

[0121] On the other hand, see Figure 8 It is a cross-sectional view of one embodiment of a planar transformer of the present invention. Figure 8 The circuit structure is mainly composed of a flat plate type inductive element 100, and then used as Figure 4B A cross-sectional view of a section taken along the second axis A2. Figure 8 In the figure, the circuit structure of the third circuit board 3 may be similar to that of the circuit boards 1 and 2, and include a third through-hole H3. The third circuit board 3 is mainly for the other of the primary side coil WP or the secondary side coil WS (here the secondary side coil WS is taken as an example) to be arranged on the third circuit board 3 in a wiring manner, and the iron core C further includes a second iron core column C2. When the first iron core member C-1 and the second iron core member C-2 of the iron core C are sleeved on the circuit boards 1, 2, and 3, the first iron core column C1 is penetrated through the first through-hole H1 and the second through-hole H2, and the second iron core column C2 is penetrated through the third through-hole H3. In this way, a flat-plate transformer can also be formed. It is worth mentioning that in one embodiment, Figure 8 The core C may be a U-shaped core, or may be, for example but not limited to, a UU-shaped core, etc., which is not limited here.

[0122] The above description is only a detailed description and drawings of the preferred specific embodiments of the present invention. The features of the present invention are not limited thereto and are not intended to limit the present invention. The entire scope of the present invention shall be subject to the following patent application scope. All solutions and similar variations of the solutions within the scope of the present invention shall be included in the scope of the present invention.

Claims

1. A flat-plate inductive element, characterized in that: include: A first circuit board includes a first coil, a first through hole and a first bonding surface, wherein the first coil includes multiple layers of first wiring, and the multiple layers of first wiring respectively surround the first through hole; and A second circuit board includes a second coil, a second through hole and a second bonding surface for bonding the first bonding surface, the second coil includes multiple layers of second wiring, and the multiple layers of second wiring surround the second through hole respectively; An iron core, comprising a first iron core leg; The first coil is electrically connected to the second coil to form a parallel structure, and the first iron core column is passed through the first through hole and the second through hole to form the flat inductive element; Among them, a first routing layer in the multi-layer first routing located on the first bonding surface has a first high voltage end and a first low voltage end, and a second routing layer in the multi-layer second routing located on the second bonding surface has a second high voltage end and a second low voltage end; when a current flows through the planar inductive element, the potential of the first low voltage end is substantially the same as that of the second low voltage end, and the potential of the first high voltage end is substantially the same as that of the second high voltage end.

2. The flat-plate inductive element according to claim 1, characterized in that: The first routing line of the layer and the second routing line of the layer are in a mirror image configuration, so that the potential of any specific point of the first routing line of the layer is the same as the potential of the position of the second routing line of the layer at the same specific point.

3. The flat-plate inductive element according to claim 1, characterized in that: In the plane defined by an X-axis and a Y-axis, the first routing line of the layer and the second routing line of the layer are in a mirror image configuration; so that the first routing line of the layer and the second routing line of the layer have the same potential at the same X-axis coordinate value and the same Y-axis coordinate value position along a Z-axis direction, wherein the X-axis, Y-axis, and Z-axis are perpendicular to each other.

4. The flat-plate inductive element according to claim 1, characterized in that: The current flows in from the end of the first wiring of the layer and the end of the second wiring of the layer, so that the first bonding surface and the second bonding surface are both high-voltage layers.

5. The flat-plate inductive element according to claim 1, wherein: The current flows out from the end of the first wiring of the layer and the end of the second wiring of the layer, so that the first bonding surface and the second bonding surface are both low-voltage layers.

6. The flat-plate inductive element according to claim 1, characterized in that: The impedance of the multi-layer first routing lines in each layer is substantially equal to the impedance of the multi-layer second routing lines in the corresponding layer.

7. The flat-plate inductive element according to claim 1, characterized in that: The impedance of the outer layer of the first circuit board is greater than the impedance of each layer inside the outer layer of the first circuit board.

8. The flat-plate inductive element according to claim 1, characterized in that: The impedance of the outer layer of the second circuit board is greater than the impedance of each layer inside the outer layer of the second circuit board.

9. The flat-plate inductive element according to claim 1, characterized in that: The end of the first routing layer forms a first end of the first coil, and the end of another first routing layer in the multiple layers of first routing away from the first routing layer forms a second end of the first coil; the end of another second routing layer in the multiple layers of second routing away from the second routing layer forms a third end of the second coil, and the end of the second routing layer forms a fourth end of the second coil; the first end is electrically connected to the fourth end, and the second end is electrically connected to the third end to form a parallel structure.

10. The flat plate type inductive element according to claim 9, characterized in that: The planar inductive element is a planar inductor, and the first coil and the second coil form an inductor coil in a parallel structure.

11. The flat-plate inductive element according to claim 9, characterized in that: The planar inductive element is a planar transformer, and the first coil and the second coil form one of a primary side coil or a secondary side coil of a parallel structure.

12. The flat-plate inductive element according to claim 11, characterized in that: The other of the primary side coil and the secondary side coil is disposed on the first circuit board or the second circuit board, so that the flat-plate transformer is formed by the first core column penetrating the first through hole and the second through hole.

13. The flat-plate inductive element according to claim 11, characterized in that: The iron core further includes a second iron core column, and the other of the primary side coil or the secondary side coil is configured on a third circuit board; the first iron core column is penetrated through the first through hole and the second through hole, and the second iron core column is penetrated through a third through hole of the third circuit board to form the flat-plate transformer.

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