Method for measuring temperature of semiconductor wafer
By introducing impurities on the surface of the semiconductor wafer to form an amorphous layer and performing heat treatment, the film thickness difference is measured to convert temperature, and the temperature difference in batch annealing furnace is solved, high-precision and simple temperature measurement are achieved, and the wafer is improved Accuracy of temperature measurement.
Patent Information
- Application Number
- CN202410608415.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2023-06-16
- Filing Date
- 2024-05-16
- Publication Date
- 2024-12-17
AI Technical Summary
In batch annealing furnaces, temperature differences in semiconductor wafers lead to deterioration of yield and characteristics, and it is difficult for the prior art to accurately measure the temperature of the wafer.
By introducing impurities on the wafer surface to form an amorphous layer, recrystallize it through heat treatment, and the film thickness difference is measured to convert the temperature, and the relationship between the film thickness difference and the temperature is used to perform accurate temperature measurement.
High-precision and simplified measurement of semiconductor wafer temperature are achieved, uneven effects between samples are suppressed, and the need to use expensive monitoring wafers for temperature measurement is avoided.
Smart Images
Figure CN119153347A_ABST
Abstract
Description
Technical Field
[0001] The present embodiment relates to a method for measuring the temperature of a semiconductor wafer. Background Art
[0002] In the annealing process using a batch annealing furnace, the temperature difference of the semiconductor wafer due to the position in the furnace becomes the main factor affecting the yield or characteristic degradation. The temperature in the furnace is controlled according to the temperature distribution corresponding to the position in the furnace. However, even if the temperature distribution looks the same, there is a case where the actual temperature of the semiconductor wafer is different.
[0003] [Prior art literature]
[0004] [Patent Document]
[0005] [Patent Document 1] Japanese Patent Application Publication No. 2000-232142
[0006] [Patent Document 2] Japanese Patent Application Publication No. 2010-129773 Summary of the invention
[0007] [Problems to be solved by the invention]
[0008] Provided is a method for measuring the temperature of a semiconductor wafer capable of more appropriately measuring the temperature of the semiconductor wafer.
[0009] [Technical means to solve the problem]
[0010] The temperature measuring method of the semiconductor wafer of the present embodiment comprises a step of introducing impurities into the first surface of a wafer having a first surface to form an amorphous layer on the first surface side of the wafer. The temperature measuring method comprises a step of measuring a first film thickness as the film thickness of the amorphous layer. The temperature measuring method comprises a step of heat-treating the wafer to recrystallize a part of the amorphous layer. The temperature measuring method comprises a step of measuring a second film thickness as the film thickness of the amorphous layer after the heat treatment. The temperature measuring method comprises a step of measuring the temperature of the wafer during the heat treatment based on the film thickness difference between the first film thickness and the second film thickness. BRIEF DESCRIPTION OF THE DRAWINGS
[0011] Figure 1 This is a flowchart showing an example of the temperature measurement method of the semiconductor wafer according to the first embodiment.
[0012] Figure 2 It is a cross-sectional view showing an example of the temperature measurement method of the semiconductor wafer according to the first embodiment.
[0013] Figure 3 This is a graph showing an example of the temperature conversion table according to the first embodiment.
[0014] Figure 4 This is a graph showing an example of the temperature measurement result in the first embodiment.
[0015] Figure 5 This is a graph showing an example of the crystal growth rate of the recrystallized amorphous layer according to the second embodiment. DETAILED DESCRIPTION
[0016] Hereinafter, an embodiment of the present invention will be described with reference to the accompanying drawings. This embodiment does not limit the present invention. The accompanying drawings are schematic or conceptual diagrams, and the ratios of the various parts may not be the same as the actual objects. In the specification and the accompanying drawings, the same symbols are marked for the same elements as those described in the drawings already mentioned, and the detailed description is appropriately omitted.
[0017] (First embodiment)
[0018] Figure 1 1 is a flowchart showing an example of the temperature measurement method of the semiconductor wafer W according to the first embodiment. Figure 2 1 is a cross-sectional view showing an example of a method for measuring the temperature of a semiconductor wafer W according to the first embodiment. The actual temperature of the semiconductor wafer W during annealing in a furnace such as a batch annealing furnace is determined based on Figure 1 and Figure 2 To determine.
[0019] First, ion implantation is performed on the semiconductor wafer W ( S10 ). More specifically, impurities are introduced (implanted) into the surface F of the semiconductor wafer W having the surface F, so that the amorphous layer 20 is formed on the surface F side of the semiconductor wafer W.
[0020] The semiconductor wafer W has a semiconductor substrate 10. The semiconductor substrate 10 is, for example, a single crystal silicon (Si) substrate. An amorphous layer 20 is formed on a portion of the semiconductor substrate 10 by implantation damage. Figure 2 As shown, the film thickness Ini including P aSi The amorphous Si layer (amorphous layer 20) is formed on the surface F (upper surface) side of the semiconductor wafer W. The film thickness Ini aSi It is the film thickness of the amorphous layer 20 after ion implantation and before annealing.
[0021] The dopant (impurity) implanted by ion implantation is, for example, P + However, the dopant is not limited to P + The energy of the ion implantation is, for example, 20 keV. For example, the implantation is performed under the implantation conditions such that the film thickness of the amorphous layer 20 becomes 6 nm or more. The dose of the ion implantation is, for example, 1×10 15 ions / cm 2 In addition, the concentration of impurities in the amorphous layer 20 is, for example, 1×10 19 atoms / cm 3 above.
[0022] Next, the film thickness Ini of the amorphous layer 20 is measured. aSi (S20). The film thickness is measured, for example, by a spectroscopic ellipsometer. However, the present invention is not limited thereto, and the film thickness may also be measured by TEM (Transmission Electron Microscope) observation or SEM (Scanning Electron Microscope) observation.
[0023] Next, the semiconductor wafer W is annealed in a furnace ( S30 ). More specifically, the semiconductor wafer W is heat-treated so that a portion of the amorphous layer 20 is recrystallized.
[0024] By annealing, the amorphous layer 20 in contact with the single crystal semiconductor substrate 10 is recrystallized. Figure 2 As shown, the film thickness of the amorphous layer 20 changes to the film thickness Aft. aSi . Film thickness Aft aSi is the film thickness of the amorphous layer 20 after annealing. When the processing time is constant, the amount of change in the film thickness of the amorphous layer 20 depends on the speed of crystal growth (solid phase epitaxial growth).
[0025] Annealing is performed in an inert atmosphere at an arbitrary treatment temperature and treatment time. For example, annealing is performed in a N2 atmosphere at 400°C for 240 minutes.
[0026] Next, the film thickness Aft of the amorphous layer 20 is measured. aSi (S40) The film thickness in step S40 is measured by the same method as step S20. aSi and film thickness Aft aSi , to calculate the film thickness difference Δ(Ini aSi -Aft aSi ).
[0027] Next, the film thickness difference Δ is converted into temperature (S50). That is, the temperature of the semiconductor wafer W during the heat treatment is measured based on the film thickness difference Δ. More specifically, the film thickness difference Δ is converted into the temperature of the semiconductor wafer W during the heat treatment based on a predetermined relationship between the film thickness difference Δ and the temperature of the semiconductor wafer W during the heat treatment.
[0028] Figure 3 This is a graph showing an example of a temperature conversion table according to the first embodiment. The vertical axis of the graph represents temperature (furnace setting temperature). The horizontal axis of the graph represents film thickness difference Δ.
[0029] Figure 3The four data points shown represent the results of previously performed measurements of the relationship between the film thickness difference Δ and temperature (temperature sensitivity of the film thickness variation). When the furnace setting temperature is 400°C and annealing is performed, multiple setting temperatures are selected from a temperature range including 400°C in the measurement of the relationship between the temperature and the film thickness difference Δ. Figure 3 In the example shown, four temperatures of 394° C., 397° C., 400° C., and 403° C. are selected as set temperatures.
[0030] Figure 3 The dashed line shown represents the result of fitting the four data points. A polynomial is obtained by fitting. By substituting the polynomial obtained by fitting into the film thickness difference Δ calculated in step S40, the film thickness difference Δ can be converted into temperature.
[0031] Figure 4 This is a graph showing an example of the temperature measurement result of the first embodiment. The vertical axis of the graph represents the temperature (actual temperature or the temperature converted in step S50). The horizontal axis of the graph represents the position in the furnace. Figure 4 In the illustrated example, five positions (TOP, CT, CNT, CB, and BTM) within the furnace from the top to the bottom of the batch annealing furnace in which a plurality of semiconductor wafers W are thermally treated are shown.
[0032] like Figure 4 As shown in FIG. 1 , the temperature of the semiconductor wafer W at five positions in the furnace is measured. Thus, the temperature distribution in the batch annealing furnace with respect to the set temperature of 400° C. can be obtained.
[0033] As described above, according to the first embodiment, the temperature of the semiconductor wafer W during the heat treatment is measured based on the film thickness difference Δ. This makes it possible to measure the temperature of the semiconductor wafer W more accurately and more simply.
[0034] Furthermore, since the film thickness difference Δ before and after annealing is used for the same semiconductor wafer W, the influence of the variation among samples of the semiconductor wafer W can be suppressed in the case of evaluating the position in the furnace, etc. Thus, the temperature of the semiconductor wafer W can be measured with higher accuracy.
[0035] In the first embodiment, before the impurities are introduced, a covering film covering the surface F is not formed. The covering film is, for example, a protective film. The covering film includes, for example, an oxide film. The covering film may also include, for example, a conductive metal film.
[0036] In addition, the annealing temperature (processing temperature) is not limited to 400°C, and may be 100°C or higher and 700°C or lower.
[0037] As a method of measuring the temperature in the furnace with higher accuracy, a temperature measurement monitoring wafer with a thermocouple may be used. However, the temperature measurement monitoring wafer is expensive and may be difficult to use in applications with predetermined conditions.
[0038] On the other hand, in the first embodiment, the temperature in the furnace can be measured more simply without using a temperature measurement monitor wafer.
[0039] (Second embodiment)
[0040] Figure 5 This is a graph showing an example of the crystal growth rate of the recrystallized amorphous layer 20 according to the second embodiment. The second embodiment is different from the first embodiment in that the element (element species) and concentration of the dopant are changed according to the annealing conditions.
[0041] The vertical axis of the graph represents the crystal growth rate (solid phase epitaxial growth rate). The horizontal axis of the graph represents 1000 / T, where the annealing temperature is T. Figure 5 In the example shown, P is shown as a dopant. + , Ge, Si, and Ar. In addition, P + 1×10 15 ions / cm 2 , 3×10 15 ions / cm 2 , and 5×10 15 ions / cm 2 In addition, the straight line overlapping with the data points of Si and Ge is the literature value of Si (100).
[0042] In the second embodiment, in step S10, impurities are introduced into the surface F of the semiconductor wafer W so that the crystal growth rate of the recrystallized amorphous layer 20 becomes a desired rate. More specifically, impurities are introduced into the surface F of the semiconductor wafer W at an element or concentration corresponding to the temperature during the heat treatment. In addition, the annealing treatment time is fixed.
[0043] like Figure 5 As shown, there is a linear relationship between 1000 / T and the crystal growth rate (logarithmic scale). Therefore, the higher the annealing temperature T, the higher the crystal growth rate. On the other hand, the lower the annealing temperature T, the lower the crystal growth rate.
[0044] First, the relationship between the crystal growth rate and the dopant element will be described.
[0045] By changing the dopant element, the straight line representing the relationship between the annealing temperature T and the crystal growth rate is shifted parallel to each other. Ar slows down the crystal growth rate relative to the literature value of Si (100). P speeds up the crystal growth rate relative to the literature value of Si (100).
[0046] When the crystal growth rate is fast, the crystal growth may progress to the outermost surface of the semiconductor wafer W during annealing. In this case, the film thickness difference Δ cannot be used for temperature conversion. On the other hand, when the crystal growth rate is slow, it may be difficult to obtain a sufficient film thickness difference Δ by temperature measurement depending on the accuracy of film thickness measurement.
[0047] Therefore, the element of the dopant is changed so that the crystal growth rate is within the desired speed range. Thus, the temperature of the semiconductor wafer W can be more appropriately measured according to the temperature zone in which the temperature evaluation is performed. For example, since the higher the annealing temperature T, the faster the crystal growth rate, a dopant that slows down the crystal growth rate is selected. An example of a dopant that slows down the crystal growth rate is Ar. On the other hand, since the lower the annealing temperature T, the slower the crystal growth rate, a dopant that speeds up the crystal growth rate is selected. An example of a dopant that speeds up the crystal growth rate is P.
[0048] In addition, the dopant element may be selected from at least one of silicon (Si), germanium (Ge), phosphorus (P), arsenic (As), argon (Ar), and antimony (Sb).
[0049] Next, the relationship between the crystal growth rate and the dopant concentration will be described.
[0050] By changing the concentration (dose) of the dopant, the straight line representing the relationship between the annealing temperature T and the crystal growth rate is also shifted in parallel. In addition, the change in the crystal growth rate caused by the change in the concentration of the dopant is smaller than the change in the crystal growth rate caused by the change in the element of the dopant. Figure 5 In the example shown, P + The higher the dose (concentration), the faster the crystal growth rate. + The lower the dose (concentration), the slower the crystal growth rate.
[0051] The concentration of the dopant may be changed so that the crystal growth rate falls within a desired rate range.
[0052] In addition, the semiconductor wafer W is heat treated for a specific time or longer. In a batch annealing furnace, for example, a relatively long heat treatment of several tens of minutes to several hours is performed. When element species such as Ar and P are used, the temperature of the semiconductor wafer W can be measured even for a relatively long heat treatment.
[0053] As described in the second embodiment, the element (element species) and concentration of the dopant may be changed according to the annealing conditions. The temperature measurement method of the semiconductor wafer W according to the second embodiment can achieve the same effects as those of the first embodiment.
[0054] Several embodiments of the present invention have been described, but these embodiments are presented as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in various other ways, and various omissions, substitutions, and changes can be made without departing from the scope of the invention. These embodiments or their variations are included in the scope or spirit of the invention, and are also included in the invention described in the claims and the scope equivalent thereto.
[0055] [Explanation of Symbols]
[0056] 10: Semiconductor substrate
[0057] 20: Amorphous layer
[0058] F: Noodles
[0059] W:Semiconductor wafer
[0060] Ini aSi :Film thickness
[0061] Aft aSi :Film thickness
[0062] Δ: film thickness difference.
Claims
1. A method for measuring the temperature of a semiconductor wafer, comprising the following steps: Introducing impurities into the first surface of a wafer having a first surface to form an amorphous layer on the first surface side of the wafer; measuring a first film thickness as the film thickness of the amorphous layer; thermally treating the wafer to recrystallize a portion of the amorphous layer; measuring a second film thickness which is the film thickness of the amorphous layer after the heat treatment; as well as The temperature of the wafer during the heat treatment is measured based on the film thickness difference between the first film thickness and the second film thickness. 2 . The method for measuring the temperature of a semiconductor wafer according to claim 1 , further comprising the step of introducing the impurity into the first surface of the wafer so that a crystal growth rate of the recrystallized amorphous layer becomes a desired rate. 3 . The method for measuring the temperature of a semiconductor wafer according to claim 2 , further comprising the step of introducing the impurity into the first surface of the wafer at an element or a concentration of the impurity corresponding to a temperature during heat treatment. 4 . The method for measuring the temperature of a semiconductor wafer according to claim 1 , wherein the impurity element includes at least one of Si, Ge, P, As, Ar, and Sb. 5 . The method for measuring the temperature of a semiconductor wafer according to claim 1 , further comprising the step of introducing the impurity into the wafer without forming a cover film covering the first surface. 6 . The method for measuring the temperature of a semiconductor wafer according to claim 1 , further comprising the step of heat-treating the wafer for a predetermined time or longer.
7. The method for measuring the temperature of a semiconductor wafer according to claim 1, wherein Measuring the temperature of the wafer during heat treatment based on the film thickness difference comprises the following steps: The film thickness difference is converted into the temperature of the wafer during the heat treatment based on a predetermined relationship between the film thickness difference and the temperature of the wafer during the heat treatment. 8 . The method for measuring the temperature of a semiconductor wafer according to claim 2 , wherein the impurity element includes at least one of Si, Ge, P, As, Ar, and Sb. 9 . The method for measuring the temperature of a semiconductor wafer according to claim 3 , wherein the impurity element includes at least one of Si, Ge, P, As, Ar, and Sb.