Failure positioning method and failure analysis method

Abstract

The invention provides a failure positioning method and a failure analysis method, and the failure positioning method comprises the steps: analyzing a diagnosis path, and determining a failure path of a test sample; grinding the test sample to the upper layer of the failure path, and carrying out EBAC test on the test sample; obtaining a failure position of the test sample based on a result of the EBAC test; or, when the failure position cannot be positioned in the EBAC test, entering a positioning analysis step; the positioning analysis step comprises the following steps: performing hot spot positioning on a test sample; based on a hot spot positioning result, obtaining a failure position of the test sample; or, when the failure position cannot be positioned through hot spot positioning, the test sample is processed to the front-section device layer, and the failure position is determined. According to the configuration, the positioning analysis step is added, so that when the EBAC cannot position the failure position, the failure position can be quickly and accurately positioned, the working efficiency and the success rate of failure positioning are improved, the time consumed by failure positioning is shortened, and the analysis cost is further reduced.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing, and in particular to a failure location method and a failure analysis method. Background Art

[0002] Failure analysis is an important part of semiconductor process development and yield improvement. Failure location plays a vital role in the failure analysis process. At present, the commonly used failure location methods in the semiconductor industry are mainly thermal emission microscopy (Thermal), photon radiation microscopy (EMMI), optically induced resistance change microscopy (OBIRCH), electron beam induced resistance change microscopy (EBIRCH), etc. The Nano Prober is a nanoprobe system integrated with a scanning electron microscope (SEM). It can perform nano-level failure analysis on devices in integrated circuit chips. In addition to the measurement of electrical characteristic parameters, it also integrates EBAC (E-beam Absorbed Current) and EBIRCH and other positioning functions. However, each failure location method has its own limitations. In the process of failure analysis, we often encounter problems that some conventional failure location methods cannot achieve failure location.

[0003] For example, EBAC is a good positioning method when the interconnection line is short-circuited or open-circuited. The failed sample can be directly located to the short-circuit position through EBAC on the diagnostic path. However, when the structure is grounded, the current will take the path with the least resistance, so the current cannot be received on the probe, and the EBAC image has no signal, so it cannot be positioned through the EBAC function.

[0004] Taking actual cases as an example, the failed samples obtained through digital logic and automatic test vector generation (ATPG) testing can be diagnosed to obtain one or several suspected failure paths (trace paths). Then the failure analysis work will start from sample grinding, grinding to the top layer of the failure path for EBAC testing, and obtaining the result of short circuit or open circuit of the target path in a certain layer. Then, according to the EBAC results, grinding to the failure layer, the failure location is determined by the SEM machine, and finally the failure analysis is performed by the TEM (Transmission Electron Microscope) machine to find the cause of the failure. However, in the actual failure location process, once the EBAC image has no signal, the failure analysis plan can only be changed to a plan of grinding layer by layer and performing SEM observation (layer by layer check), which not only reduces the work efficiency, but also greatly reduces the success rate of failure analysis.

[0005] Based on this, how to avoid using a layer-by-layer grinding solution when there is no signal in the EBAC function, which causes a decrease in work efficiency and failure analysis success rate, has become a technical problem that technicians in this field need to solve. Summary of the invention

[0006] The purpose of the present invention is to provide a failure location method and a failure analysis method to solve the problem that when the EBAC function cannot be accurately located, the layer-by-layer grinding analysis method is used, resulting in a decrease in work efficiency and failure analysis success rate.

[0007] In order to achieve the above object, the present invention provides a failure location method, comprising:

[0008] Analyze the diagnostic path and determine the failure path of the test sample;

[0009] Grinding the test sample to the uppermost layer of the failure path, and performing an EBAC test on the test sample;

[0010] Based on the result of the EBAC test, the failure position of the test sample is obtained; or, when the EBAC test cannot locate the failure position, a positioning analysis step is entered;

[0011] The positioning analysis step comprises:

[0012] Obtaining appropriate test conditions and locating hot spots of the test sample;

[0013] Based on the result of hot spot positioning, the failure position of the test sample is obtained; or when the hot spot positioning cannot locate the failure position, the test sample is processed to the front-end device layer to determine the failure position.

[0014] Optionally, obtaining the failure position of the test sample based on the result of the EBAC test includes:

[0015] Based on the image obtained by the EBAC test, it is found that the failure path is short-circuited or open-circuited in a certain layer;

[0016] The test sample is ground to the layer where short circuit or open circuit occurs, and the failure position is determined by SEM.

[0017] Optionally, when the EBAC test cannot locate the failure position, entering the location analysis step includes:

[0018] When there is no signal in the image of the EBAC test, the positioning analysis step is entered.

[0019] Optionally, the obtaining of suitable test conditions and performing hotspot positioning on the test sample includes:

[0020] The layout of the test sample is analyzed to find the ground terminal near the failure path, to test whether the failure path and the ground terminal are short-circuited, and to select test conditions based on the resistance value to locate the hot spot of the test sample.

[0021] Optionally, a two-needle method of a nanoprobe machine is used to test whether a short circuit occurs between the failure path and the ground terminal.

[0022] Optionally, the EBIRCH function of the nanoprobe machine is used to locate the hotspot of the test sample.

[0023] Optionally, when the hotspot location cannot locate the failure position, processing the test sample to the front-end device layer to determine the failure position includes:

[0024] The test sample is processed to the front-end device layer, and the failure position is located using the VC observation function of a scanning electron microscope and a nanoprobe machine.

[0025] Optionally, the test sample is obtained by utilizing digital logic and ATPG testing, and a diagnostic path is analyzed to obtain a failure path of the test sample.

[0026] In order to achieve the above object, the present invention also provides a failure analysis method, comprising:

[0027] Obtaining the failure position of the test sample using the failure location method as described above;

[0028] TEM analysis was performed to determine the cause and mechanism of failure.

[0029] Optionally, a FIB machine is used to prepare TEM samples, and a TEM machine is used to analyze the TEM samples.

[0030] Compared with the existing failure location methods, the failure location method and failure analysis method provided by the present application have the following advantages:

[0031] The failure localization method provided in the present application, by adding a positioning analysis step, can further locate the failure of the test sample by hotspot localization when there is no signal in the image of the EBAC test, and finally locate the failure position in different ways according to the result of the hotspot localization, instead of having to grind layer by layer and perform SEM observation when the EBAC test cannot locate the failure position as in the existing failure localization method. Therefore, the failure localization method provided in the present application can improve the work efficiency and success rate of failure localization, reduce the time spent on failure localization, and thus reduce the analysis cost, providing reference and help for process improvement.

[0032] The failure analysis method provided in the present application, by adopting the above-mentioned failure location method, can effectively improve the work efficiency and success rate of failure location when the EBAC test cannot locate the failure position, avoid layer-by-layer grinding and SEM observation, save a lot of manpower and material resources, reduce the cost of failure analysis, and improve the work efficiency of failure analysis. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 A schematic diagram of a process flow of a failure location method provided by an embodiment of the present invention;

[0034] Figure 2 A schematic diagram of a failure analysis method according to an embodiment of the present invention;

[0035] Figure 3 The nanoprobe machine provided in the embodiment of the present invention uses a two-needle method to test and find the current relationship diagram between the failure path and the ground leakage;

[0036] Figure 4 A schematic diagram of locating a failure position through an abnormal VC on a CT layer using a SEM machine provided in an embodiment of the present invention;

[0037] Figure 5 A planar TEM image and EDS analysis result of the failure position provided by the embodiment of the present invention;

[0038] Figure 6 A cross-sectional TEM image of a failure location provided by an embodiment of the present invention;

[0039] Figure 7 The EDS analysis result of the failure position provided by the embodiment of the present invention. DETAILED DESCRIPTION

[0040] In order to make the purpose, advantages and features of the present invention clearer, the present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention. In addition, the structure shown in the drawings is often a part of the actual structure. In particular, the emphasis of each drawing is different, and sometimes different scales are used.

[0041] As used in this specification, the singular forms "a", "an" and "the" include plural objects, the term "or" is generally used to include the meaning of "and / or", the term "several" is generally used to include the meaning of "at least one", and the term "at least two" is generally used to include the meaning of "two or more". In addition, the terms "first", "second" and "third" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first", "second" and "third" may explicitly or implicitly include one or at least two of the features, "one end" and "the other end" and "the proximal end" and "the distal end" generally refer to two corresponding parts, which include not only the endpoints, and the terms "installed", "connected" and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral body; it can be directly connected or indirectly connected through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. In addition, as used in this specification, an element disposed on another element generally only indicates that there is a connection, coupling, cooperation or transmission relationship between the two elements, and the connection, coupling, cooperation or transmission between the two elements may be direct or indirect through an intermediate element, and it cannot be understood as indicating or implying the spatial position relationship between the two elements, that is, one element may be in any orientation such as inside, outside, above, below or on one side of another element, unless the content clearly indicates otherwise. The terms "upper", "lower", "top" and "bottom" are generally relative position relationships arranged in the direction of gravity; the terms "vertical, vertical direction" generally refer to the direction of gravity, which is generally perpendicular to the ground, and "horizontal, horizontal plane direction" generally refers to the direction parallel to the ground; for ordinary technicians in this field, the specific meanings of the above terms in this specification can be understood according to specific circumstances.

[0042] The purpose of the present invention is to provide a failure location method and a failure analysis method to solve the problem that when the EBAC function cannot be accurately located, the layer-by-layer grinding analysis method is used, resulting in a decrease in work efficiency and failure analysis success rate.

[0043] Those skilled in the art can understand that the EBAC function and EBIRCH function mentioned above are both commonly used methods for failure location in the semiconductor field. Among them, EBAC (Electron Beam Absorbed Current) is a function that can quickly and effectively locate the position of an open circuit (Open) or a short circuit (Short) on the line. The electron beam passes through the protective layer or the metal dielectric layer, and accumulates charges in the metal layer. The metal layer can be as deep as 3 to 4 layers. The accumulated charges form a current due to the loop formed by the probe. The position of the open circuit and the short circuit can be determined by the current image. The EBIRCH (Electron Beam Induced Resistance Change) function is to form a current loop by placing two nanoprobes on the pad or metal wire / through hole, and a certain voltage is applied. Under the irradiation of the electron beam, the component will produce a temperature change due to the heating of the electron beam, which will cause a change in resistance, and the current will also change accordingly. The EBIRCH function effectively locates the failure point by detecting the position of the current change. In the prior art, once the EBAC function fails to locate the failure position, the operator needs to grind the test sample layer by layer and perform SEM (Scanning Electron Microscope) observation, which is time-consuming and labor-intensive, and increases the cost of failure analysis. Based on this, the present application proposes a failure location method and a failure analysis method. By adding a location analysis step, when EBAC fails to locate the failure position, the test sample is further tested through the EBIRCH function to narrow the possible range of the failure position, improve the efficiency of failure analysis, and reduce the cost of failure analysis.

[0044] Please refer to Figure 1 The present invention provides a failure location method, comprising:

[0045] Step S1: Analyze the diagnostic path and determine the failure path of the test sample;

[0046] Step S2: grinding the test sample to the uppermost layer of the failure path, and performing an EBAC test on the test sample;

[0047] Step S3: based on the result of the EBAC test, obtaining the failure position of the test sample; or, when the EBAC test cannot locate the failure position, entering the location analysis step;

[0048] The positioning analysis steps include:

[0049] Step S30: obtaining appropriate test conditions and locating hot spots of the test samples;

[0050] Step S31: based on the result of hotspot positioning, the failure position of the test sample is obtained; or, when the hotspot positioning cannot locate the failure position, the test sample is processed to the front-end device layer to determine the failure position.

[0051] It should be noted that in this embodiment, the test sample is obtained by digital logic and ATPG (Automatic Test Pattern Generation) testing, and the diagnostic path is analyzed to obtain the failure path of the test sample. Among them, ATPG is a process in which the test pattern vector used in semiconductor device testing is automatically generated by a program. The test vector is loaded onto the input pin of the device in sequence, and the output signal is collected and compared with the budgeted test vector to determine the test result. After the test sample is tested by digital logic and ATPG, the operator can directly perform subsequent tests on the measured path where failure may occur until the failure position is accurately located. At the same time, the failure path should be understood as the path of the test current, which can be a circuit formed by all or part of the connection of several metal wires in the entire test structure. In step S2, grinding the test sample to the top layer of the failure path is equivalent to grinding the test sample to the top layer of the above-mentioned several metal wires. In this embodiment, a nanoprobe machine with integrated EBAC test and EBIRCH functions is used to test the test sample. In other embodiments, a test machine with the same or similar functions can also be used for testing, and this embodiment does not limit this.

[0052] With such configuration, by adding a positioning analysis step, when the EBAC test cannot locate the failure position, the test sample can be further located by hotspot positioning, and the failure position can be finally located in different ways according to the result of hotspot positioning, instead of having to grind layer by layer and perform SEM observation when the EBAC test cannot locate the failure position as in the existing failure location method. Therefore, the above failure location method can improve the work efficiency and success rate of failure location, reduce the time spent on failure location, and thus reduce the analysis cost, providing reference and help for process improvement.

[0053] As an optional embodiment, based on the result of the EBAC test, the failure position of the test sample is obtained, including:

[0054] Step S3-1: Based on the image obtained by the EBAC test, it is found that the failure path is short-circuited or open-circuited in a certain layer;

[0055] Step S3-2: Grind the test sample to the layer where the short circuit or open circuit occurs, and determine the failure position through a SEM machine.

[0056] As mentioned above, the EBAC test is a test method that quickly locates the short circuit or open circuit position based on the current image. Under the premise that the nanoprobe machine is operating normally and the test conditions have been optimized, the current image obtained based on the EBAC test can locate the failure position. At the same time, the test sample is ground to the failure layer and observed through the SEM machine to lock the failure position.

[0057] Furthermore, when the EBAC test cannot locate the failure position, the location analysis step is entered, including:

[0058] Step S3-3: When there is no signal in the image of the EBAC test, enter the positioning analysis step.

[0059] It should be noted that, in combination with the EBAC test principle, when the EBAC test cannot locate the failure position (i.e., the EBAC image has no signal), excluding the reasons of the test machine and the test conditions, the problem of the failure path being grounded may be considered. If the failure path is grounded, the current will choose the path with the smallest resistance to flow. Therefore, the current cannot be collected on the probe, and the EBAC test cannot form a current image. In the prior art, once the above situation occurs, only layer-by-layer grinding and SEM observation can be performed to search for the failure position in a large range. In this embodiment, through the additional positioning analysis step, the test sample that could not be located by conventional positioning means can also quickly and accurately locate the failure position.

[0060] In an optional embodiment, obtaining suitable test conditions and locating hot spots of the test sample includes:

[0061] Step S30-1: Analyze the layout of the test sample, find the ground terminal near the failure path, test whether the failure path and the ground terminal are short-circuited, and select test conditions based on the resistance value to locate the hotspot of the test sample.

[0062] It should be noted that in this embodiment, the two-needle method of the nanoprobe machine is used to test whether the failure path and the ground terminal are short-circuited. It can be understood by those skilled in the art that the two-needle method is also called the ohmmeter method. The two probes are connected to a constant current source and a voltmeter. The constant current source outputs a constant current. The voltmeter measures the voltage between the two probes, and then the resistance value is obtained by Ohm's law, so that it can be determined whether the failure path and the ground terminal are short-circuited. After the resistance is measured using the two-needle method, based on the measured resistance value, the appropriate test machine conditions are selected, and the EBIRCH function of the nanoprobe machine is used to locate the hot spot of the test sample. As described above, when the EBIRCH function is used, the component will produce temperature changes due to the heating of the electron beam, which will cause the resistance value to change, so that the current change can be generated. The nanoprobe machine detects the change in the current position, and then can locate the current change position (i.e., the hot spot position). In this way, the failure location method of this embodiment uses the EBIRCH function to locate the hot spot of the test sample when the EBAC function cannot locate the failure position, further narrowing the scope of searching for the failure position.

[0063] Furthermore, when the hotspot location cannot locate the failure location, the test sample is processed to the front-end device layer to determine the failure location, including:

[0064] Step S31 - 1 : Process the test sample to the front-end device layer, and use the VC observation function of the scanning electron microscope and the nanoprobe machine to locate the failure position.

[0065] Those skilled in the art can understand that if the EBIRCH function of the nanoprobe machine cannot capture the hotspot, based on the principle of the EBIRCH function, it is suspected that the failure occurs in the front-end device layer of the process. Therefore, it is necessary to process the test sample in the front-end device layer and use SEM VC observation and the nanoprobe machine to locate the failure position. With this configuration, when both EBAC and EBIRCH cannot locate the exact failure position, the failure position is preferentially considered to be in the front-end device layer, and the test sample is observed in the front-end device layer, which further narrows the observation range and reduces the workload of failure location.

[0066] In another embodiment, please refer to Figure 2 The present invention also provides a failure analysis method, comprising:

[0067] Step S100: obtaining the failure position of the test sample using the failure location method described above;

[0068] Step S200: Perform TEM analysis to determine the cause and mechanism of failure.

[0069] It should be noted that in step S100, the failure location of the test sample is obtained by the above failure location method, including three methods:

[0070] 1) Use the EBAC function of the nanoprobe machine to locate the failure position;

[0071] 2) When EBAC cannot locate the hotspot, use the EBIRCH function of the nanoprobe machine to locate the hotspot;

[0072] 3) When EBIRCH cannot capture the hotspot, the test sample is ground to the front-end device layer, and the failure position is located by combining SEM VC observation and nanoprobe equipment.

[0073] In step S200, it can be understood by those skilled in the art that when performing TEM analysis on the failure position, a FIB (Focused Ion Beam) machine is usually used to prepare TEM samples, and a TEM (Transmission Electron Microscope) machine is used to analyze the TEM samples. Among them, the FIB machine is a micro-dissection instrument that uses an electric lens to focus the ion beam into a very small size. It forms a gallium ion beam through electric lens focusing, and achieves the purpose of cutting through physical collision. It has good controllability and can better control the processing accuracy. At the same time, the TEM machine is used to observe the TEM sample, and EDS analysis is used to determine the cause and mechanism of failure. Among them, EDS (Energy Dispersive Spectrometer) is an instrument for X-ray energy spectrum analysis. When electrons interact with matter, the incident electrons that can be focused can excite primary X-rays. The characteristic X-rays emitted by different elements have different wavelengths and energies, so that all diffraction patterns of the measured material can be obtained, which can assist the TEM machine to analyze the cause and mechanism of failure.

[0074] The following is a specific embodiment, please refer to Figures 3 to 7 , the failure location method and failure analysis method provided in this embodiment are described.

[0075] The diagnostic path is analyzed first, and the test sample is ground to the uppermost layer of the suspected failure path;

[0076] The EBAC test was carried out by the nanoprobe machine and it was found that the EBAC image could not be obtained;

[0077] Analyze the layout, find the ground terminal near the failure path, use the two-needle method of the nanoprobe machine to test the electrical properties of the ground terminal, and find that the failure path is leaking to the ground terminal (such as Figure 3 shown);

[0078] Select appropriate test conditions based on the resistance value obtained from the electrical test, and use the EBIRCH function of the nanoprobe machine for positioning;

[0079] The EBIRCH function cannot capture hot spots, and the failure location is suspected to be located in the device layer at the front end of the process;

[0080] The test samples were processed to the front-end device layer, and the failure position was located by SEM VC observation and nanoprobe machine (such as Figure 4 shown);

[0081] Perform TEM analysis on the failure location to obtain a planar TEM image of the failure location and EDS analysis results (such as Figure 5 ), cross-sectional TEM image of the failure location (as shown Figure 6 As shown) and the corresponding EDS analysis results (as shown Figure 7 Finally, the failure cause and mechanism are determined.

[0082] It should be noted that Figures 4 to 7 The position indicated by the arrow in the figure is the failure position obtained by using the above failure location method. Therefore, the above failure location method and failure analysis method can quickly and accurately locate the failure position when the EBAC function cannot accurately locate the failure position, thereby improving the efficiency of failure analysis and reducing the cost of failure analysis.

[0083] In summary, in the failure location method and the failure analysis method provided in the embodiments of the present invention, the failure location method includes: analyzing the diagnostic path to determine the failure path of the test sample; grinding the test sample to the topmost layer of the failure path, and performing an EBAC test on the test sample; obtaining the failure position of the test sample based on the result of the EBAC test; or, when the EBAC test cannot locate the failure position, entering the location analysis step; the location analysis step includes: obtaining suitable test conditions to perform hotspot location on the test sample; obtaining the failure position of the test sample based on the result of the hotspot location; or, when the hotspot location cannot locate the failure position, processing the test sample to the front-end device layer to determine the failure position.

[0084] With such configuration, by adding a positioning analysis step, when there is no signal in the image of the EBAC test, the test sample can be further located for failure by means of hotspot positioning, and the failure position can be finally located in different ways according to the result of the hotspot positioning. Unlike the existing failure positioning method, when the EBAC test cannot locate the failure position, it is only necessary to grind layer by layer and perform SEM observation. Therefore, the failure positioning method provided in the present application can improve the work efficiency and success rate of failure positioning, reduce the time spent on failure positioning, and thus reduce the analysis cost, providing reference and help for process improvement.

[0085] Furthermore, by adopting the above-mentioned failure location method, when the EBAC test cannot locate the failure position, the work efficiency and success rate of failure location can be effectively improved, and layer-by-layer grinding and SEM observation can be avoided, thereby saving a lot of manpower and material resources, reducing the cost of failure analysis, and improving the work efficiency of failure analysis.

[0086] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A failure location method, characterized in that: include: Analyze the diagnostic path and determine the failure path of the test sample; Grinding the test sample to the uppermost layer of the failure path, and performing an EBAC test on the test sample; Based on the result of the EBAC test, the failure position of the test sample is obtained; or, when the EBAC test cannot locate the failure position, a positioning analysis step is entered; The positioning analysis step comprises: Obtaining appropriate test conditions and locating hot spots of the test sample; Based on the result of hot spot positioning, the failure position of the test sample is obtained; or when the hot spot positioning cannot locate the failure position, the test sample is processed to the front-end device layer to determine the failure position.

2. The failure location method according to claim 1, characterized in that: The method of obtaining the failure position of the test sample based on the result of the EBAC test includes: Based on the image obtained by the EBAC test, it is found that the failure path is short-circuited or open-circuited in a certain layer; The test sample is ground to the layer where short circuit or open circuit occurs, and the failure position is determined by SEM.

3. The failure location method according to claim 1, characterized in that: When the EBAC test fails to locate the failure position, entering the location analysis step includes: When there is no signal in the image of the EBAC test, the positioning analysis step is entered.

4. The failure location method according to claim 1, characterized in that: The obtaining of suitable test conditions and locating the hotspot of the test sample comprises: The layout of the test sample is analyzed to find the ground terminal near the failure path, to test whether the failure path and the ground terminal are short-circuited, and to select test conditions based on the resistance value to locate the hot spot of the test sample.

5. The failure location method according to claim 4, characterized in that: A two-needle method of a nanoprobe machine is used to test whether the failure path and the ground terminal are short-circuited.

6. The failure location method according to claim 4, characterized in that: The EBIRCH function of the nanoprobe machine is used to locate the hotspot of the test sample.

7. The failure location method according to claim 1, characterized in that: When the hot spot positioning cannot locate the failure position, processing the test sample to the front-end device layer to determine the failure position includes: The test sample is processed to the front-end device layer, and the failure position is located using the VC observation function of a scanning electron microscope and a nanoprobe machine.

8. The failure location method according to claim 1, characterized in that: The test sample is obtained by using digital logic and ATPG testing, and the diagnosis path is analyzed to obtain the failure path of the test sample.

9. A failure analysis method, characterized in that: include: Obtaining the failure position of the test sample using the failure location method according to any one of claims 1 to 8; TEM analysis was performed to determine the cause and mechanism of failure.

10. The failure analysis method according to claim 9, characterized in that: The TEM samples are prepared by using a FIB machine, and the TEM samples are analyzed by using a TEM machine.

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