Semiconductor structure and forming method thereof
By setting the main connection electrode and the unit connection electrode in the upper electrode layer of the semiconductor structure, the electrical connection of multiple effective electrodes is achieved, and the problem of insufficient capacitance density in the prior art is solved, which improves the capacitance density and saves device area.
Patent Information
- Application Number
- CN202310710834.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-06-14
- Publication Date
- 2024-12-17
AI Technical Summary
In semiconductor manufacturing, as the complexity of integrated circuits increases, the prior art cannot meet the demand for capacitance density, resulting in the limitation of the splicing of MOM capacitors, which cannot effectively improve capacitance density and save device area.
By providing a connecting electrode in the upper electrode layer of the semiconductor structure, including a main connecting electrode and a unit connecting electrode, the main connecting electrode is electrically connected to the unit connecting electrode, and the unit connecting electrode is electrically connected to the active electrode, so that a plurality of active electrodes are connected, This improves capacitance density and saves device area.
It realizes improving capacitance density in the semiconductor structure, ensuring device performance, and effectively saving device area. Through the width proportional design of the main connection electrode and the unit connection electrode, the carrying capacity of the total electrical signal is ensured.
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Figure CN119153447A_ABST
Abstract
Description
Technical Field
[0001] The embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular to a semiconductor structure and a method for forming the same. Background Art
[0002] In semiconductor manufacturing, with the development trend of ultra-large-scale integrated circuits, in order to achieve the requirements of saving device area and capacitance density, the manufacturing process of semiconductor integrated circuit chips uses batch processing technology to form arrayed capacitor devices on the substrate and splice multiple capacitors. Among them, MOM (metal-oxide-metal) capacitors have been widely used in the manufacture of many semiconductor devices because they can be implemented together with copper interconnect structures and have high capacitance density.
[0003] However, as semiconductor devices become increasingly complex, the number of MOM capacitors integrated in the same semiconductor structure is gradually increasing. When forming a semiconductor structure in the prior art, the number of MOM capacitors that can be spliced is limited, resulting in the inability to meet the demand for capacitance density.
[0004] Therefore, how to improve the capacitance density in the semiconductor structure and save the device area has become a technical problem that technical personnel in this field need to solve urgently. Summary of the invention
[0005] In view of this, an embodiment of the present invention provides a semiconductor structure and a method for forming the same, so as to improve capacitance density and save device area.
[0006] An embodiment of the present invention provides a semiconductor structure, including:
[0007] substrate;
[0008] a lower electrode layer located on the substrate;
[0009] an isolation layer located on the lower electrode layer;
[0010] an upper electrode layer located on the isolation layer;
[0011] Among them, the upper electrode layer includes a plurality of effective electrodes and connecting electrodes electrically connected to the effective electrodes, the effective electrodes are arranged in an array, the connecting electrodes include unit connecting electrodes and main connecting electrodes, the unit connecting electrodes are electrically connected to the effective electrodes, the main connecting electrodes are electrically connected to the unit connecting electrodes, and the width of the unit connecting electrodes is greater than the width of the effective electrodes, and the width of the main connecting electrodes is greater than the width of the unit connecting electrodes.
[0012] Optionally, the main connection electrode includes at least a first main connection electrode and a second main connection electrode, the first main connection electrode is electrically connected to the unit connection electrode, the second main connection electrode is electrically connected to the first main connection electrode, and the width of the second main connection electrode is greater than that of the first main connection electrode.
[0013] Optionally, the plurality of effective electrodes are symmetrically arranged based on a central axis of any one of the connecting electrodes; and the unit connecting electrodes are symmetrically arranged based on a central axis of any one of the main connecting electrodes.
[0014] Optionally, the unit connection electrode is vertically electrically connected to the effective electrode, the first main connection electrode is vertically electrically connected to the unit connection electrode, and the second main connection electrode is vertically electrically connected to the first main connection electrode.
[0015] Optionally, the extending direction of the first main connection electrode is the same as the extending direction of the effective electrode;
[0016] An extending direction of the second main connection electrode is the same as an extending direction of the unit connection electrode.
[0017] Optionally, the width of the first main connection electrode is 1.5 to 2 times the width of the unit connection electrode, and the width of the second main connection electrode is 1.5 to 2 times the width of the first main connection electrode.
[0018] Optionally, there are multiple main connection electrodes, and the multiple main connection electrodes are connected in a tree-like manner according to the number of electrode levels, and the main connection electrode with the lowest electrode level is electrically connected to the unit connection electrode.
[0019] Optionally, the number of main connection electrodes increases proportionally with the number of effective electrodes, and the multiple effective electrodes are symmetrically connected based on the central axis of the main connection electrode with the highest level, and the level of the main connection electrode corresponds to the number of the main connection electrodes.
[0020] Optionally, the material of the effective electrode or the connecting electrode is one or more of aluminum, copper, silver, gold, nickel, tungsten, and tin.
[0021] An embodiment of the present invention further provides a method for forming a semiconductor structure, comprising:
[0022] providing a substrate;
[0023] forming a lower electrode layer on the substrate;
[0024] forming an isolation layer on the lower electrode layer;
[0025] forming a first electrode in an upper electrode layer on the isolation layer, the first electrode comprising at least an effective electrode and a first main connection electrode;
[0026] forming a second electrode in the upper electrode layer on the isolation layer, the second electrode comprising at least a cell connection electrode and a second main connection electrode;
[0027] The width of the unit connection electrode is greater than the width of the effective electrode, the width of the first main connection electrode is greater than the width of the unit connection electrode, and the width of the second main connection electrode is greater than the width of the first main connection electrode.
[0028] Optionally, the extension direction of the first electrode is a first direction, the extension direction of the second electrode is a second direction, and the first direction is perpendicular to the second direction.
[0029] Optionally, the effective electrodes are arranged symmetrically based on the central axis of any connecting electrode; and the unit connecting electrodes are arranged symmetrically based on the central axis of any main connecting electrode.
[0030] Optionally, the width of the first main connection electrode is 1.5 to 2 times the width of the unit connection electrode, and the width of the second main connection electrode is 1.5 to 2 times the width of the first main connection electrode.
[0031] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:
[0032] In the embodiment of the present invention, a connection electrode electrically connected to an effective electrode is provided on the upper electrode layer, wherein the connection electrode includes a main connection electrode and a unit connection electrode, and the main connection electrode is electrically connected to the unit connection electrode, and the unit connection electrode is electrically connected to the effective electrode, so that multiple effective electrodes are connected based on the main connection electrode and the unit connection electrode, thereby improving the capacitance density in the semiconductor structure and effectively saving the device area. In addition, when the width of the main connection electrode is greater than the width of the unit connection electrode, and the width of the unit connection electrode is greater than the width of the effective electrode, the main connection electrode electrically connected to the unit connection electrode can withstand the total amount of electrical signals of multiple effective electrodes electrically connected to the unit connection electrode, thereby ensuring device performance. BRIEF DESCRIPTION OF THE DRAWINGS
[0033] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying creative work.
[0034] Figure 1 It is an optional structural schematic diagram of a MOM capacitor;
[0035] Figure 2 for Figure 1 Schematic diagram of the disassembled structure;
[0036] Figure 3 and Figure 4 is an optional schematic diagram of a semiconductor structure;
[0037] Figure 5 A schematic cross-sectional view of a semiconductor structure provided by an embodiment of the present invention;
[0038] Figure 6 An optional structural schematic diagram of a semiconductor structure provided by an embodiment of the present invention;
[0039] Figure 7 The embodiment of the present invention provides Figure 6 A schematic diagram of the disassembled structure of the structure shown;
[0040] Figure 8 A schematic diagram of another optional structure of a semiconductor structure provided by an embodiment of the present invention;
[0041] Figures 9 to 19 A schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure provided by an embodiment of the present invention. DETAILED DESCRIPTION
[0042] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.
[0043] As can be seen from background technology, along with the increasing complexity of semiconductor devices, the number of capacitors integrated in the same semiconductor device increases gradually, wherein, MOM (metal-oxide-metal, metal-oxide-metal) capacitors are widely used. And when the prior art forms semiconductor devices, the splicing number of MOM capacitors is restricted, resulting in being unable to meet the demand for capacitance density. Now in conjunction with prior art, the reason for this problem is analyzed.
[0044] MOM capacitors are generally interdigital capacitors formed by metal wiring. Figure 1 The optional structural schematic diagram of the MOM capacitor is shown as an example. Figure 1Shown, MOM capacitor comprises: low voltage line end 11 and high voltage line end 12.Wherein, along with the progress of process technology, the metal wire of MOM capacitor can be closer, can be wired by multi-layer metal layer simultaneously, makes the capacitance density of MOM capacitor relatively large.And, in order to save area, when MOM capacitor is designed, multi-layer metal wire can be superimposed to form semiconductor device.
[0045] However, on the same metal layer, only one metal line extending in one direction can be photolithographically processed (corresponding to Figure 1 The thin wires extending along the X-axis direction) and the metal wires extending in the other direction (corresponding to Figure 1 In the embodiment of the present invention, the metal wire of the photolithography X direction can be obtained by the method of the present invention, and the metal wire of the photolithography Y direction can be obtained by the method of the present invention. For example, when the metal wire of the photolithography X direction, its width can be accomplished to be 7nm and the following scope, and when the metal wire of the photolithography Y direction, it can not be photolithography simultaneously with the metal wire of the X direction, that is, it is impossible to expose the metal wire width of two directions simultaneously on the same metal layer. Therefore, when making MOM capacitor, the metal thin wire of one direction can be photolithography first at the same metal layer, and then the port wide wire of another direction of the photolithography at this metal layer, or, at a metal layer, the metal thin wire is photolithography, and then at another metal layer, the metal thick wire is photolithography, and, by connecting two layers of through holes, the electrical connection of the metal thin wire and the metal wide wire is realized, wherein, the metal thin wire and the metal wide wire can adopt SADP (Self-Aligned Double Patterning, dual patterning technology) technology to realize.
[0046] correspond Figure 1 The MOM capacitor shown in Figure 1 gives Figure 2 The disassembled structure diagram of the MOM capacitor device shown in FIG. Figure 2 It can be based on Figure 1 The MOM capacitor shown is disassembled.
[0047] Reference Figure 2 , the low voltage line terminal 11 is an integral line terminal. In an optional example, the low voltage line terminal 11 can be obtained by integral casting. The high voltage line terminal 12 may include: a plurality of first high voltage line terminals 121 and a second high voltage line terminal 122, wherein the first high voltage line terminal 121 may correspond to the metal thin wire (finger) of the MOM capacitor, and the second high voltage line terminal 122 may be a port wide line (terminal) for realizing the electrical connection of a plurality of fingers. In an example, the second high voltage line terminal 122 may be referred to as the port circuit metal line of the capacitor. Among them, the first high voltage line terminal 121 and the second high voltage line terminal 122 can be obtained based on the photolithography of different metal layers, and the electrical connection is realized through the corresponding connection holes. In a specific example, by applying a voltage to the second high voltage line terminal 122, the plurality of the first high voltage line terminals 121 can obtain the corresponding voltage.
[0048] When designing an integrated circuit, when multiple MOM capacitors are required in the same device, Figure 1 The MOM capacitor shown can be used as a capacitor basic unit, and for saving device area, improves capacitance density, and multiple MOM capacitor basic units can be spliced. Wherein, because the line width of the terminal corresponding to the MOM capacitor basic unit is fixed, if the line width of the port circuit is changed, the effective length of the finger in the MOM capacitor also changes, thereby causing the capacitance of each MOM capacitor basic unit to decrease. Therefore, usually according to the line width of the port circuit of the MOM capacitor basic unit, multiple MOM capacitor basic units are spliced into a row of modes, and it is realized to improve capacitance density and save device area. Figure 3 and Figure 4 An optional schematic diagram showing a semiconductor structure is shown exemplarily, Figure 3 It is a semiconductor structure composed of four MOM capacitor basic units. Figure 4 It is a semiconductor structure composed of 9 MOM capacitor basic units, wherein the position enclosed by the dotted line is a MOM capacitor basic unit.
[0049] However, the inventors have found that as the number of MOM capacitor basic units spliced increases, a column of MOM capacitors is arranged larger and larger, resulting in an increasing current on the terminal width line. Since the line width of the terminal is fixed, the maximum current it can withstand is also fixed. The method of splicing multiple MOM capacitor basic units with a fixed terminal line width cannot withstand the current required for large-scale MOM capacitor array applications, thereby affecting the number of MOM capacitor basic units that can be spliced in the Y-axis direction, resulting in the number of capacitors being limited, and the demand for capacitance density of the semiconductor structure cannot be met.
[0050] Based on this, an embodiment of the present invention provides a semiconductor structure and a method for forming the same, wherein the semiconductor structure includes: a substrate, a lower electrode layer located on the substrate, an isolation layer located on the lower electrode layer, and an upper electrode layer located on the isolation layer; wherein the upper electrode layer includes a plurality of effective electrodes, and connecting electrodes electrically connected to the effective electrodes, the effective electrodes are arranged in an array, the connecting electrodes include a main connecting electrode and a unit connecting electrode, the main connecting electrode is electrically connected to the unit connecting electrode, the unit connecting electrode is electrically connected to the effective electrode, and the width of the main connecting electrode is greater than the width of the unit connecting electrode, and the width of the unit connecting electrode is greater than the width of the effective electrode.
[0051] It can be seen that the embodiment of the present invention provides a connection electrode electrically connected to the effective electrode on the upper electrode layer, wherein the connection electrode includes a main connection electrode and a unit connection electrode, and the main connection electrode is electrically connected to the unit connection electrode, and the unit connection electrode is electrically connected to the effective electrode, so that multiple effective electrodes can be connected based on the main connection electrode and the unit connection electrode, thereby improving the capacitance density in the semiconductor structure and effectively saving the device area. In addition, when the width of the main connection electrode is greater than the width of the unit connection electrode, and the width of the unit connection electrode is greater than the width of the effective electrode, the main connection electrode electrically connected to the unit connection electrode can withstand the total amount of electrical signals of multiple effective electrodes electrically connected to the unit connection electrode, thereby ensuring device performance.
[0052] The technical solutions in the embodiments of the present invention will be described clearly and completely below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all the embodiments.
[0053] As an optional example of the disclosure of the embodiments of the present invention, Figure 5 FIG. 2 shows a schematic cross-sectional view of a semiconductor structure according to an embodiment of the present invention. Figure 5 As shown, the semiconductor structure includes: a substrate 20 , a lower electrode layer 21 located on the substrate, an isolation layer 22 located on the lower electrode layer 21 , and an upper electrode layer 23 located on the isolation layer 22 .
[0054] In an optional example, the substrate 20 may be a semiconductor substrate, such as silicon, germanium, silicon germanium, silicon carbide, gallium arsenide, or indium gallium, etc. Alternatively, the substrate may also be other types of substrates such as a silicon on insulator substrate or a germanium on insulator substrate, and those skilled in the art may select them according to actual needs.
[0055] The lower electrode layer 21 may be a layer structure with low voltage metal lines formed on the substrate surface, and may be formed on the substrate surface by a corresponding semiconductor process. The lower electrode layer may serve as a lower plate of a capacitor device.
[0056] The isolation layer 22 may be used to isolate the layer structure of the lower electrode layer and the upper electrode layer formed subsequently. The material of the isolation layer may be one or more of silicon nitride, silicon oxide, silicon oxynitride, and the like.
[0057] The upper electrode layer 23 may be a layer structure having a high voltage metal line formed on an isolation layer, and may be formed on the isolation layer by a corresponding semiconductor process. The upper electrode layer may serve as an upper plate of a capacitor device. In a specific example, the upper electrode layer and the lower electrode layer may be electrically connected based on a through hole.
[0058] The upper electrode layer 23 may include a plurality of effective electrodes 231 and connection electrodes electrically connected to the effective electrodes. The effective electrodes are arranged in an array, and the connection electrodes may include unit connection electrodes (not shown in the figure) and main connection electrodes 232 .
[0059] In some embodiments, based on the fact that there are multiple effective electrodes 231, in order to enable the connecting electrode to withstand the total amount of electrical signals of multiple effective electrodes and ensure device performance, when the connecting electrode includes a unit connecting electrode and a main connecting electrode 232, the unit connecting electrode can be electrically connected to the effective electrode 231, the main connecting electrode 232 can be electrically connected to the unit connecting electrode, and the width of the unit connecting electrode can be greater than the width of the effective electrode 231, and the width of the main connecting electrode 232 can be greater than the width of the unit connecting electrode.
[0060] In some embodiments, the material of the effective electrode or the connecting electrode may be one or more of aluminum, copper, silver, gold, nickel, tungsten, and tin.
[0061] Figure 6 The optional structural diagram of the semiconductor structure of the embodiment of the present invention is exemplarily shown. Figure 6 As shown, the unit connection electrode 233 is electrically connected to the effective electrode 231, and the main connection electrode 232 is electrically connected to the unit connection electrode 233. Wherein, the Aa line and the Bb line are tangent lines, Figure 5 It can be considered Figure 6 Cross-sectional structure along line Aa.
[0062] As an optional implementation, when the unit connection electrode 233 is electrically connected to the effective electrode 231 and the main connection electrode 232 is electrically connected to the unit connection electrode 233, the extension direction of the effective electrode may be the same as the extension direction of the main connection electrode 232. Figure 6 , refer to Figure 7 The disassembled structural schematic diagram of the semiconductor structure shown in the figure, based on the limitation of the photolithography process, when the extension direction of the effective electrode 231 is the same as the extension direction of the main connecting electrode 232, the effective electrode 231 and the main connecting electrode 232 with the same extension direction can be simultaneously photolithographically processed, and then the unit connecting electrode 233 with another extension direction can be photolithographically processed to obtain the semiconductor structure in the embodiment of the present invention.
[0063] It should be noted that the main connection electrode is used to apply electrical parameters, such as voltage; the unit connection electrode is electrically connected to the main connection electrode, and is used to shunt the electrical parameters to multiple effective electrodes electrically connected to the unit connection electrode. Therefore, to ensure that the main connection electrode can carry the electrical parameters of multiple unit connection electrodes, the width of the main connection electrode needs to be greater than the width of the unit connection electrode; to ensure that the unit connection electrode can carry the electrical parameters of multiple effective electrodes, the width of the unit connection electrode needs to be greater than the width of the effective electrode.
[0064] In a specific example, when designing a semiconductor device, the width of the unit connection electrode can be calculated based on the number of pre-designed MOM capacitor basic units and the value of the effective electrode transmission electrical parameter, and then the width of the main connection electrode can be calculated, so as to electrically connect the effective electrode to the unit connection electrode, and electrically connect the unit connection electrode to the main connection electrode.
[0065] Continue to refer to Figure 6 , when the unit connection electrode 233 is electrically connected to the effective electrode 231, and the main connection electrode 232 is electrically connected to the unit connection electrode 233, a plurality of MOM capacitor basic units can be spliced in a dendritic shape. Wherein, two MOM capacitor basic units are connected in series, and two MOM capacitor basic units (the parts enclosed by the dotted lines) connected in series are connected in parallel to obtain a new unit group, that is, 4 MOM capacitor basic units form a new unit group, and then two new unit groups are spliced based on the main connection electrode, thereby effectively saving device area and improving capacitance density.
[0066] It can be seen that the embodiment of the present invention provides a connection electrode electrically connected to the effective electrode on the upper electrode layer, wherein the connection electrode includes a main connection electrode and a unit connection electrode, and the main connection electrode is electrically connected to the unit connection electrode, and the unit connection electrode is electrically connected to the effective electrode, so that multiple effective electrodes can be connected based on the main connection electrode and the unit connection electrode with different extension directions, thereby improving the capacitance density in the semiconductor structure and effectively saving the device area. In addition, when the width of the main connection electrode is greater than the width of the unit connection electrode, and the width of the unit connection electrode is greater than the width of the effective electrode, the main connection electrode electrically connected to the unit connection electrode can withstand the total amount of electrical signals of multiple effective electrodes electrically connected to the unit connection electrode, thereby ensuring device performance.
[0067] In some embodiments, as the number of effective electrodes increases, the number of unit connection electrodes will also gradually increase. In order to carry the total amount of electrical signals of multiple effective electrodes and ensure device performance, as an optional implementation, Figure 8 Another optional schematic diagram of the semiconductor structure in the embodiment of the present invention is shown as an example. Figure 8As shown, the main connection electrodes may include at least a first main connection electrode 2321 and a second main connection electrode 2322 .
[0068] As the number of basic units of the MOM capacitor increases, the first main connection electrode 2321 can be electrically connected to the unit connection electrode 233, the second main connection electrode 2322 can be electrically connected to the first main connection electrode 2321 to carry the electrical parameters required by the first main connection electrode 2321, and the width of the second main connection electrode 2322 can be greater than that of the first main connection electrode 2321.
[0069] correspond Figure 6 , refer to Figure 8 As shown, the two unit groups ( Figure 8 The dotted circle area) can be used as a new unit, and the corresponding unit connection electrode 233 is electrically connected based on the first main connection electrode 2321. In addition, when the second main connection electrode 2322 is electrically connected to the first main connection electrode 2321, the splicing of 16 MOM capacitor basic units is realized, and when the width of the second main connection electrode 2322 is greater than the width of the first main connection electrode 2321, it can carry the electrical parameters required by the first main connection electrode 2321, and then carry the electrical parameters required by the 16 MOM capacitor basic units.
[0070] In some embodiments, the plurality of effective electrodes 231 may be arranged symmetrically based on the central axis of any of the connecting electrodes, such as Figure 6 As shown, multiple effective electrodes 231 (parts encircled by dashed lines in the figure) can be symmetrically arranged based on the central axis of any connecting electrode (for example, the corresponding unit connecting electrode 233); the unit connecting electrodes can be symmetrically arranged based on the central axis of any main connecting electrode, such as Figure 8 As shown, a plurality of unit connection electrodes 233 (parts enclosed by dashed circles in the figure) are symmetrically arranged based on the central axis of any main connection electrode (eg, the corresponding first main connection electrode 2321).
[0071] It should be noted that, in order to withstand the required total current of multiple MOM capacitor basic units connected in series, the high voltage line width closer to the array center spliced by multiple MOM capacitor basic units is wider, and the low voltage line width closer to the array edge spliced by multiple MOM capacitor basic units is wider.
[0072] In some embodiments, in order to save device area and improve capacitance density, the unit connection electrode can be vertically electrically connected to the effective electrode, the first main connection electrode can be vertically electrically connected to the unit connection electrode, and the second main connection electrode can be vertically electrically connected to the first main connection electrode.
[0073] Furthermore, based on the vertical electrical connection between the effective electrode and the unit connection electrode, the vertical electrical connection between the first main connection electrode and the unit connection electrode, and the vertical electrical connection between the second main connection electrode and the first main connection electrode, the extension direction of the first main connection electrode can be the same as the extension direction of the effective electrode, and the extension direction of the second main connection electrode can be the same as the extension direction of the unit connection electrode, so that the electrode pattern in the semiconductor structure of the embodiment of the present invention can be obtained based on the photolithography of the same metal layer, and no additional jumper structure is required to realize the corners between the effective electrodes.
[0074] In some embodiments, in order to achieve that the second main connection electrode can withstand the electrical parameters of the first main connection electrode connected in series, and the first main connection electrode can withstand the electrical parameters of the unit connection electrodes connected in series, during design, the width of the first main connection electrode can be 1.5 to 2 times the width of the unit connection electrode, and the width of the second main connection electrode can be 1.5 to 2 times the width of the first main connection electrode.
[0075] In some embodiments, the number of the main connection electrodes is multiple. To improve the capacitance density, the multiple main connection electrodes can be connected in a tree-like manner according to the number of electrode levels, wherein the main connection electrode with the lowest electrode level is electrically connected to the unit connection electrode, thereby saving device area and improving capacitance density. For example: the number of main connection electrodes is 3, namely the first main connection electrode, the second main connection electrode, and the third main connection electrode, wherein the first main connection electrode has the lowest level and the third main connection electrode has the highest level; the first main connection electrode is electrically connected to the unit connection electrode, the second main connection electrode is electrically connected to the first main connection electrode, and the third main connection electrode is electrically connected to the second main connection electrode, and the width of the third main connection electrode is greater than that of the second main connection electrode, the width of the second main connection electrode is greater than that of the first main connection electrode, and the width of the first main connection electrode is greater than that of the unit connection electrode.
[0076] As an optional implementation, in the semiconductor structure of an embodiment of the present invention, the number of effective electrodes arranged in an array may be greater than or equal to 4, that is, the number of MOM capacitor basic units arranged in an array is greater than or equal to 4.
[0077] Among them, as the number of MOM capacitor basic units arranged in the array increases, in some embodiments, the number of the main connecting electrodes can be increased proportionally with the number of the effective electrodes, and the multiple effective electrodes are symmetrically connected based on the central axis of the main connecting electrode with the highest level, and the level number of the main connecting electrode corresponds to the number of the effective electrodes.
[0078] The main connection electrode may be an electrode connected to a capacitor unit group, such as a first main connection electrode connected to a unit connection electrode, or a second main connection electrode connected to the first main connection electrode, or a third main connection electrode connected to the second main connection electrode, and so on.
[0079] It is understandable that, for the convenience of the design of semiconductor structure, when multiple MOM capacitor basic units are needed, the line width corresponding to the effective electrode and the unit connection electrode of each capacitor basic unit can be fixed, so that multiple MOM capacitor basic units can be composed of a new unit group within a controllable range, and then spliced based on the new unit group, then the number of main connection electrodes can have a certain proportional relationship with the number of effective electrodes, for example Figure 8 In the embodiment, the number of main connection electrodes is 2, namely, the first main connection electrode 2321 and the second main connection electrode 2322; the number of effective electrodes is 16, and the ratio of the number of main connection electrodes to the number of effective electrodes is 1 / 4.
[0080] When there are multiple main connection electrodes, multiple effective electrodes can be symmetrically connected based on the central axis of the main connection electrode with the highest level, for example Figure 8 In the embodiment, 16 effective electrodes are symmetrically connected based on the central axis of the second main connection electrode with the highest level. The level of the second main connection electrode can be determined according to the number of main connection electrodes, that is, the level of the main connection electrode can correspond to the number of effective electrodes, for example Figure 8 When 16 effective electrodes are spliced in a dendrite-like manner, 4 effective electrodes can be grouped together, and 8 effective electrodes can be connected in series based on the first main connecting electrode to obtain a capacitor unit, and then 2 capacitor units can be connected in series based on the second main connecting electrode to obtain a dendrite-like splicing structure of multiple capacitor basic units.
[0081] It should be noted that the number of capacitor basic units spliced in the semiconductor structure of the embodiment of the present invention can be set according to actual needs. The above example is only an optional implementation and does not limit the semiconductor structure of the embodiment of the present invention. Among them, the number of capacitor basic units spliced in the semiconductor structure of the embodiment of the present invention can be determined based on the line width of the main connection electrode corresponding to the capacitor basic units arranged in the array, and the line width of the main connection electrode can be formed within the range of process requirements.
[0082] In the embodiment of the present invention, a connection electrode electrically connected to an effective electrode is provided on the upper electrode layer, wherein the connection electrode includes at least a first main connection electrode and a unit connection electrode, and the first main connection electrode is vertically electrically connected to the unit connection electrode, and the unit connection electrode is vertically electrically connected to the effective electrode, so that multiple effective electrodes can be connected based on the first main connection electrode and the unit connection electrode with different extension directions, thereby improving the capacitance density in the semiconductor structure and effectively saving the device area. In addition, when the width of the first main connection electrode is greater than the width of the unit connection electrode, and the width of the unit connection electrode is greater than the width of the effective electrode, the first main connection electrode vertically electrically connected to the unit connection electrode can withstand the total amount of electrical signals of multiple effective electrodes vertically electrically connected to the unit connection electrode, thereby ensuring device performance.
[0083] In another embodiment of the present invention, a method for forming a semiconductor structure is provided. Figures 9 to 19 The schematic diagram of the structure corresponding to each step in the first embodiment of the method for forming a semiconductor structure according to the embodiment of the present invention is shown. Figures 9 to 19 Can be corresponding Figure 8 Schematic diagram of the cross-sectional structure of the Cc line.
[0084] refer to Fig. 9 , providing a substrate 100.
[0085] The substrate is used to provide a process platform for the subsequent formation of the device structure. The substrate may be a semiconductor substrate, such as silicon, germanium, silicon germanium, silicon carbide, gallium arsenide, or indium gallium. Alternatively, the substrate may also be other types of substrates such as a silicon-on-insulator substrate or a germanium-on-insulator substrate, and those skilled in the art may select the substrate according to actual needs.
[0086] refer to Fig.10 , forming a lower electrode layer 110 located on the substrate 100.
[0087] The lower electrode layer 110 may be formed by a deposition process, and may be a conductive material layer or a metal oxide layer, and may be formed of conductive materials such as copper (Cu), aluminum (Al), or metal oxides. In an optional example, the lower electrode layer may serve as a lower plate of a capacitor device.
[0088] refer to Fig.11 , forming an isolation layer 120 located on the lower electrode layer 110.
[0089] The isolation layer 120 can be formed by a deposition process. The material of the isolation layer is one or more of silicon nitride, silicon oxide, and silicon oxynitride. The isolation layer can be a single-layer structure or a stacked-layer structure. For example, the isolation layer can be a stack of silicon oxide and silicon nitride. The present invention does not make any specific limitation here.
[0090] refer to Fig.12 , forming a first electrode 140 in the upper electrode layer 130 located on the isolation layer 120;
[0091] The upper electrode layer 130 may be formed by a deposition process, an etching process, etc. Moreover, based on the characteristics of the capacitor device, the first electrode 140 may at least include an effective electrode 141 and a first main connection electrode 142 .
[0092] In an optional example, the formation process of the upper electrode layer 130 may be specifically as follows:
[0093] Reference Fig.13 , forming a patterned first mask layer 131 on the isolation layer 120, wherein a first mask pattern 1311 in the first mask layer 131 exposes a partial area of the isolation layer 120;
[0094] Reference Fig.14 , forming a first electrode material layer 132 on the first mask layer 131, wherein the first electrode material layer 132 completely covers the first mask layer 131 and the isolation layer 120 exposed by the first mask layer;
[0095] Reference Fig.15 , removing the first electrode material layer on the first mask layer, and retaining the first electrode material layer on the isolation layer as the first electrode 140.
[0096] In some embodiments, corresponding to the number of the first electrodes, the electrode corresponding to the central axis of the first electrode is the first main connection electrode 142 , and the width of the first main connection electrode 142 is greater than that of the effective electrode 141 .
[0097] refer to Fig.16 , forming a second electrode in the upper electrode layer 130 located on the isolation layer 120.
[0098] Based on the characteristics of the capacitor device and the number of effective electrodes 141 in the first electrode, the second electrode may at least include a unit connection electrode 150 and a second main connection electrode (not shown in the figure).
[0099] In an optional example, the number of effective electrodes in the first electrodes may be greater than or equal to 4. For example, the number of effective electrodes is 16.
[0100] In the example where the first mask layer is retained, the formation process of the upper electrode layer may be specifically as follows:
[0101] Reference Fig.17 , forming a patterned second mask layer 133 located on the isolation layer, wherein a second mask pattern in the second mask layer 133 exposes a partial area of the first mask layer 131 and a partial area of the first electrode;
[0102] Reference Fig.18 , forming a second electrode material layer 134 on the second mask layer 133, wherein the second electrode material layer 134 completely covers the second mask layer and the first mask layer and a partial area of the first electrode exposed by the second mask layer;
[0103] Reference Fig.19 , remove the second electrode material layer on the second mask layer 133, and retain the first mask layer 133 and the second electrode material layer on the first electrode in a part of the region as the second electrode, the second electrode being, for example Fig.19 The cell connection electrode 150 is shown in FIG.
[0104] It should be noted that, in the process of forming the semiconductor structure, in order to achieve that the second main connection electrode formed subsequently can withstand the electrical parameters of the first main connection electrode, the first main connection electrode can withstand the electrical parameters of the unit connection electrode formed subsequently, and the unit connection electrode formed subsequently can withstand the electrical parameters of the effective electrode, the width of the unit connection electrode can be greater than the width of the effective electrode, the width of the first main connection electrode can be greater than the width of the unit connection electrode, and the width of the second main connection electrode can be greater than the width of the first main connection electrode. Accordingly, in the process of forming the semiconductor structure, the width of the mask pattern for forming the unit connection electrode is greater than the width of the mask pattern for forming the effective electrode, the width of the mask pattern for forming the first main connection electrode is greater than the width of the mask pattern for forming the unit connection electrode, and the width of the mask pattern for forming the second main connection electrode is greater than the width of the mask pattern for forming the first main connection electrode.
[0105] In some embodiments, the extending direction of the first electrode may be a first direction, the extending direction of the second electrode may be a second direction, and the first direction is perpendicular to the second direction. Figure 6 The direction shown by the line Bb perpendicular to the line Aa; the second direction can be Figure 6 The direction is shown by line Aa which is perpendicular to line Bb.
[0106] In some embodiments, the effective electrodes may be arranged symmetrically based on the central axis of any connecting electrode; and the unit connecting electrodes may be arranged symmetrically based on the central axis of any main connecting electrode.
[0107] In some embodiments, in order to achieve that the second main connection electrode can withstand the electrical parameters of the first main connection electrode, and the first main connection electrode can withstand the electrical parameters of the unit connection electrode, the width of the first main connection electrode is 1.5 to 2 times the width of the unit connection electrode, and the width of the second main connection electrode is 1.5 to 2 times the width of the first main connection electrode.
[0108] In the method for forming a semiconductor of an embodiment of the present invention, a connection electrode electrically connected to an effective electrode is formed on an upper electrode layer, wherein the connection electrode includes at least a first main connection electrode and a unit connection electrode, and the first main connection electrode is electrically connected to the unit connection electrode, and the unit connection electrode is electrically connected to the effective electrode, so that multiple effective electrodes can be connected based on the first main connection electrode and the unit connection electrode, thereby improving the capacitance density in the semiconductor structure and effectively saving the device area. In addition, when the width of the first main connection electrode is greater than the width of the unit connection electrode, and the width of the unit connection electrode is greater than the width of the effective electrode, the first main connection electrode electrically connected to the unit connection electrode can withstand the total amount of electrical signals of multiple effective electrodes electrically connected to the unit connection electrode, thereby ensuring device performance.
[0109] The above describes multiple implementation schemes provided by the embodiments of the present invention. The various optional methods introduced in the implementation schemes can be combined and cross-referenced with each other without conflict, thereby extending a variety of possible implementation schemes, which can all be considered as implementation schemes disclosed and open in the embodiments of the present invention.
[0110] Although the embodiments of the present invention are disclosed above, the present application is not limited thereto. Any person skilled in the art may make various changes and modifications without departing from the spirit and scope of the present application. Therefore, the protection scope of the present application shall be subject to the scope defined by the claims.
Claims
1. A semiconductor structure, It is characterized in that include: substrate; a lower electrode layer located on the substrate; an isolation layer located on the lower electrode layer; an upper electrode layer located on the isolation layer; Among them, the upper electrode layer includes a plurality of effective electrodes and connecting electrodes electrically connected to the effective electrodes, the effective electrodes are arranged in an array, the connecting electrodes include unit connecting electrodes and main connecting electrodes, the unit connecting electrodes are electrically connected to the effective electrodes, the main connecting electrodes are electrically connected to the unit connecting electrodes, and the width of the unit connecting electrodes is greater than the width of the effective electrodes, and the width of the main connecting electrodes is greater than the width of the unit connecting electrodes.
2. The semiconductor structure according to claim 1, It is characterized in that The main connection electrodes include at least a first main connection electrode and a second main connection electrode, the first main connection electrode is electrically connected to the unit connection electrode, the second main connection electrode is electrically connected to the first main connection electrode, and the second main connection electrode is wider than the first main connection electrode.
3. The semiconductor structure according to claim 2, It is characterized in that The plurality of effective electrodes are symmetrically arranged based on a central axis of any one of the connection electrodes; and the unit connection electrodes are symmetrically arranged based on a central axis of any one of the main connection electrodes.
4. The semiconductor structure according to claim 2, It is characterized in that The unit connection electrode is vertically and electrically connected to the effective electrode, the first main connection electrode is vertically and electrically connected to the unit connection electrode, and the second main connection electrode is vertically and electrically connected to the first main connection electrode.
5. The semiconductor structure according to claim 4, It is characterized in that The extending direction of the first main connection electrode is the same as the extending direction of the effective electrode; An extending direction of the second main connection electrode is the same as an extending direction of the unit connection electrode.
6. The semiconductor structure according to claim 2, It is characterized in that The width of the first main connection electrode is 1.5 to 2 times the width of the unit connection electrode, and the width of the second main connection electrode is 1.5 to 2 times the width of the first main connection electrode.
7. The semiconductor structure according to claim 1, It is characterized in that There are multiple main connection electrodes, and the multiple main connection electrodes are connected in a tree-like manner according to the number of electrode levels. The main connection electrode with the lowest electrode level is electrically connected to the unit connection electrode.
8. The semiconductor structure according to claim 7, It is characterized in that The number of main connection electrodes increases in proportion to the number of effective electrodes, and the multiple effective electrodes are symmetrically connected based on the central axis of the main connection electrode with the highest level, and the level of the main connection electrode corresponds to the number of effective electrodes.
9. The semiconductor structure according to claim 1, It is characterized in that The material of the effective electrode or the connecting electrode is one or more of aluminum, copper, silver, gold, nickel, tungsten, and tin.
10. A method for forming a semiconductor structure, It is characterized in that include: providing a substrate; forming a lower electrode layer on the substrate; forming an isolation layer on the lower electrode layer; forming a first electrode in an upper electrode layer on the isolation layer, the first electrode comprising at least an effective electrode and a first main connection electrode; forming a second electrode of the upper electrode layer located on the isolation layer, the second electrode comprising at least a cell connection electrode and a second main connection electrode; The width of the unit connection electrode is greater than the width of the effective electrode, the width of the first main connection electrode is greater than the width of the unit connection electrode, and the width of the second main connection electrode is greater than the width of the first main connection electrode.
11. The method for forming a semiconductor structure according to claim 10, It is characterized in that The extending direction of the first electrode is a first direction, the extending direction of the second electrode is a second direction, and the first direction is perpendicular to the second direction.
12. The method for forming a semiconductor structure according to claim 10, It is characterized in that The effective electrodes are arranged symmetrically based on the central axis of any connecting electrode; and the unit connecting electrodes are arranged symmetrically based on the central axis of any main connecting electrode.
13. The method for forming a semiconductor structure according to claim 10, It is characterized in that The width of the first main connection electrode is 1.5 to 2 times the width of the unit connection electrode, and the width of the second main connection electrode is 1.5 to 2 times the width of the first main connection electrode.