Multi-channel modulated wide bandgap semiconductor device structure and manufacturing method thereof

Abstract

The invention provides a multi-channel modulated wide bandgap semiconductor device structure and a manufacturing method thereof. A grid electrode, a P + masking layer, a second P-well region, a second source P + region and a second source N + region of the device structure are arranged in a middle region of an N + current expansion layer in a penetrating manner along a first direction; the second P-well region, the second source P + region and the second source N + region are located between the grid electrode and the P + masking layer, the two second source N + regions are located on the two sides of the second source P + region in the second direction respectively, and the two second P-well regions are correspondingly located on the outer sides of the two second source N + regions; the second source N + region, the second P-well region and the N + current expansion layer form a new current path; the two first source P + regions are arranged on the two sides of the N + current expansion layer in the second direction respectively. A first P-well region and a first source N + region are arranged between the first source P + region and the grid electrode on any side in an overlapped mode, the device structure can improve the conduction characteristic of the device, the device can be modulated to have low conduction resistance at different temperatures, and the requirements of different application scenes are met.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor devices, and in particular to a multi-channel modulated wide bandgap semiconductor device structure and a manufacturing method thereof. Background Art

[0002] In recent years, silicon carbide SiC and gallium nitride GaN, as third-generation semiconductor materials, have excellent material properties and are more advantageous than traditional Si materials in physical properties such as bandgap width, critical breakdown electric field strength, and electron saturation drift velocity. The power devices prepared, such as diodes and transistors, have better electrical properties and can be used in high-power, high-voltage, high-frequency, and high-temperature applications that silicon-based devices cannot meet. They are also one of the breakthrough paths to surpass Moore's Law. Therefore, they are widely used in the field of new energy and have promoted the development of the "new energy revolution."

[0003] At present, in power switch applications, the Baliga figure of merit BFOM is usually used as an indicator of the applicability of semiconductor materials in power electronics, which is expressed as: BFOM = εμE 3 , where ε is the dielectric constant, μ is the mobility, and E is the breakdown field strength of the semiconductor. The BFOM value is roughly positively correlated with the sixth power of the bandgap width Eg. Wide bandgap semiconductors have lower power loss and higher conversion efficiency in the application of power devices, and can be better applied to power electronics.

[0004] However, wide bandgap semiconductor trench MOSFET devices still have some shortcomings in design and practical application: one of the most studied problems is that wide bandgap semiconductor devices cause a very high electric field on the gate dielectric layer during the blocking process, and the device is prone to failure; the needs of the device in different temperature application scenarios also need to be paid attention to. The device channel resistance is negatively correlated with temperature. As the temperature rises, the threshold voltage decreases, and the on-resistance also decreases, but the positive temperature coefficient of other resistances in the device area (JFET area resistance, drift area resistance, etc.) will offset this effect, ultimately resulting in an on-resistance with a positive temperature coefficient at higher temperatures; currently commercially available devices have an on-resistance that is basically a negative temperature coefficient at negative temperatures, and after passing an inflection point of about 0 to 25°C, the positive temperature coefficient is maintained, which results in the device having a lower on-resistance near the inflection point; that is, the current device is more suitable for application scenarios at room temperature, but for some higher temperature application scenarios, it is necessary to design devices with better on-resistance at higher temperatures.

[0005] Therefore, the wide bandgap semiconductor device causes a very high electric field on the gate dielectric layer during the blocking process, especially at the groove corners, which causes the gate dielectric layer to quickly breakdown under high drain voltage, which becomes a problem that needs to be solved. At the same time, it is necessary to design devices with better on-resistance at higher temperatures so that the devices can meet the needs of different temperature application scenarios. In combination with the current development status of the prior art, the present invention provides a new multi-channel modulated wide bandgap semiconductor device structure and a manufacturing method thereof. Summary of the invention

[0006] Based on the above description, the present invention provides a multi-channel modulated wide bandgap semiconductor device structure and a manufacturing method thereof, which can improve the conduction characteristics of the device while making the inflection point of the overall on-resistance from a negative temperature coefficient to a positive temperature coefficient controllable, that is, the device can be modulated to have a lower on-resistance at a required higher temperature.

[0007] The technical solution of the present invention to solve the above technical problems is as follows:

[0008] In a first aspect, the present invention provides a multi-channel modulated wide bandgap semiconductor device structure, comprising: a substrate, an epitaxial layer, an N+ current spreading layer, a first source N+ region, a second source N+ region, a first source P+ region, a second source P+ region, a first P-well region, a second P-well region, a P+ shielding layer, a gate, a source and a drain;

[0009] The epitaxial layer, the N+ current spreading layer and the source electrode are sequentially arranged on the substrate; the drain electrode is arranged at the bottom of the substrate;

[0010] The gate, the P+ shielding layer, the second P-well region, the second source P+ region and the second source N+ region are all arranged in the middle area of ​​the N+ current expansion layer along the first direction, wherein the second P-well region, the second source P+ region and the second source N+ region are located between the gate and the P+ shielding layer, and two second source N+ regions are respectively located on both sides of the second source P+ region along the second direction, and two second P-well regions are respectively located on the outside of two second source N+ regions; so that the second source N+ region, the second P-well region and the N+ current expansion layer form a new current path; the P+ shielding layer is arranged close to the epitaxial layer;

[0011] Two first source P+ regions are respectively arranged on both sides of the N+ current spreading layer along the second direction and are spaced apart from the gate; the first P-well region and the first source N+ region are superimposed between the first source P+ region and the gate on either side;

[0012] The first direction and the second direction are arranged perpendicularly.

[0013] Based on the above technical solution, the present invention can also be improved as follows.

[0014] Further, the middle region of the gate is a split gate;

[0015] The middle region of the split gate is filled with source metal.

[0016] Furthermore, the gate includes a gate trench, a gate dielectric layer and polysilicon;

[0017] The trench is arranged in the N+ current spreading layer along the first direction, the gate dielectric layer is arranged on the inner wall side of the gate trench, and the polysilicon is arranged in a groove formed by the gate dielectric layer.

[0018] Furthermore, the multi-channel modulated wide bandgap semiconductor device structure further includes an interlayer dielectric layer;

[0019] The interlayer dielectric layer covers the open portion of the groove formed by the gate dielectric layer.

[0020] Furthermore, the stacking of the first P-well region and the first source N+ region specifically includes: the first source N+ region is located above the first P-well region, and the upper surface of the first source N+ region contacts the lower surface of the interlayer dielectric layer.

[0021] Furthermore, the multi-channel modulated wide bandgap semiconductor device structure also includes a source ohmic contact region;

[0022] The source contacts the first source N+ region, the second source N+ region, the first source P+ region, and the second source P+ region through the source ohmic contact region.

[0023] Furthermore, the substrate is a wide bandgap semiconductor material.

[0024] In a second aspect, the present invention further provides a method for manufacturing a multi-channel modulated wide bandgap semiconductor device structure as described in the first aspect, comprising:

[0025] An epitaxial layer and an N+ current spreading layer are sequentially grown on the substrate;

[0026] Forming a first P-well region by ion implantation, secondary epitaxy or growing a P-type oxide; forming a first source N+ region by ion implantation;

[0027] forming a first source P+ region by ion implantation;

[0028] Dry etching to form a gate trench;

[0029] forming a second P-well region by ion implantation;

[0030] Forming a P+ masking layer by P-type ion implantation;

[0031] forming a second source N+ region and a second source P+ region by ion implantation;

[0032] Growing and etching to form a gate at the gate trench;

[0033] Growing, depositing and etching to form an interlayer dielectric layer at the gate;

[0034] Depositing source metal on the interlayer dielectric layer to form a source electrode;

[0035] A drain metal is deposited at the bottom of the substrate to form a drain, thereby obtaining a multi-channel modulated wide bandgap semiconductor device structure.

[0036] Based on the above technical solution, the present invention can also be improved as follows.

[0037] Furthermore, growing and etching the gate at the gate trench specifically includes:

[0038] Gate dielectric layer growth, gate polysilicon growth and etching;

[0039] The gate polysilicon is etched to form a split gate.

[0040] Furthermore, before depositing the source metal on the interlayer dielectric layer, the method further includes:

[0041] An ohmic contact metal is deposited on the interlayer dielectric layer, the first source N+ region and the first source P+ region to form a source ohmic contact region.

[0042] Compared with the prior art, the technical solution of this application has the following beneficial technical effects:

[0043] The multi-channel modulated wide bandgap semiconductor device structure provided by the present invention is formed with a substrate, an epitaxial layer, an N+ current expansion layer, a first source N+ region, a second source N+ region, a first source P+ region, a second source P+ region, a first P-well region, a second P-well region, a P+ shielding layer, a gate, a source and a drain; the epitaxial layer, the N+ current expansion layer and the source are sequentially arranged on the substrate; the drain is arranged at the bottom of the substrate; the gate, the P+ shielding layer, the second P-well region, the second source P+ region and the second source N+ region are all arranged in the middle area of ​​the N+ current expansion layer along the first direction, wherein the second P-well region, the second source P+ region and the second The source N+ region is located between the gate and the P+ shielding layer, and the two second source N+ regions are respectively located on both sides of the second source P+ region along the second direction, and the two second P-well regions are respectively located outside the two second source N+ regions; so that the second source N+ region, the second P-well region and the N+ current expansion layer form a new current path; the P+ shielding layer is arranged close to the epitaxial layer; the two first source P+ regions are respectively arranged on both sides of the N+ current expansion layer along the second direction, and are arranged with intervals from the gate; the first P-well region and the first source N+ region are superimposed between the first source P+ region and the gate on either side; wherein the first direction and the second direction are arranged perpendicularly. Compared with the prior art, it has the following beneficial effects:

[0044] (1) The deep shielding structure formed by the P+ shielding layer and the second P-well region can better protect the gate groove corner and improve the gate oxide reliability of the device; further, the P+ shielding layer can be kept in a grounded state through the second source P+ region, which enhances the protection of the P+ shielding layer on the gate and can better improve the dynamic characteristics of the device;

[0045] (2) The second source N+ region, the second P-well region and the N+ current extension layer will form a new current path, thereby utilizing multiple channels to modulate the trench MOSFET; multi-channel modulation can increase the current density of the device, and more channels and more current paths can improve the conduction characteristics of the device.

[0046] (3) Multi-channels can be designed with different threshold voltages. Different threshold voltages result in different on-resistances of the channels. Therefore, multi-channel modulation can control the on-resistance of the device channel region, and further control the positive temperature coefficient portion of the device's overall on-resistance, making the inflection point of the overall on-resistance from the negative temperature coefficient to the positive temperature coefficient controllable. In other words, the device can be modulated to have a lower on-resistance at a desired higher temperature. This type of device is more suitable for high-temperature application scenarios. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] Figure 1 A schematic structural diagram of a multi-channel modulated wide bandgap semiconductor device structure provided in Embodiment 1 of the present invention;

[0048] Figure 2 The gate polysilicon layout diagram provided in Embodiment 1 of the present invention;

[0049] Figure 3 A schematic diagram of current paths of a multi-channel modulated wide bandgap semiconductor device structure provided in Embodiment 1 of the present invention;

[0050] Figure 4 A schematic diagram of the manufacturing process of a multi-channel modulated wide bandgap semiconductor device structure provided in Embodiment 2 of the present invention;

[0051] Figure 5 A schematic structural diagram of a multi-channel modulated wide bandgap semiconductor device structure provided in Embodiment 3 of the present invention;

[0052] Figure 6 A schematic structural diagram of a multi-channel modulated wide bandgap semiconductor device structure provided in Embodiment 4 of the present invention;

[0053] Figure 7 A schematic structural diagram of a multi-channel modulated wide bandgap semiconductor device structure provided in Embodiment 5 of the present invention;

[0054] Figure 8 A schematic structural diagram of a multi-channel modulated wide bandgap semiconductor device structure provided in Embodiment 6 of the present invention;

[0055] Fig. 9 A schematic structural diagram of a multi-channel modulated wide bandgap semiconductor device structure provided in Embodiment 7 of the present invention;

[0056] In the accompanying drawings, the components represented by the reference numerals are listed as follows:

[0057] 1. Substrate; 2. Epitaxial layer; 3. N+ current spreading layer; 4. First source N+ region; 5. Second source N+ region; 6. First source P+ region; 7. Second source P+ region; 8. First P-well region; 9. Second P-well region; 10. P+ masking layer; 11. Gate; 1101. Gate dielectric layer, 1102. Polysilicon; 12. Interlayer dielectric layer; 13. Source ohmic contact region; 14. Source; 15. Drain. DETAILED DESCRIPTION

[0058] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. Embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0059] In the prior art, in order to better protect the gate oxide layer and relatively excellent conduction characteristics of trench MOSFET, there are two main technical solutions and device structures for wide bandgap semiconductor trench MOSFET in the industry. These include the "P+ semi-wrapped asymmetric trench structure" adopted by Infineon in Germany, which uses a single-side area to ensure device current conduction; and the Japanese Rohm adopts a source double trench structure constructed on both sides of the gate trench to shield the bottom of the middle gate trench, and the middle area to ensure current conduction on both sides of the device. For currently commercially available devices, the on-resistance is basically a negative temperature coefficient at negative temperatures. After passing an inflection point of about 0 to 25°C, it maintains a positive temperature coefficient, which results in the device having a lower on-resistance near the inflection point; that is, the current device is more suitable for application scenarios at room temperature, but for some higher temperature application scenarios, it is necessary to design devices with better on-resistance at higher temperatures.

[0060] The existing technical solutions are prone to damage to the gate dielectric layer under harsh conditions such as avalanche breakdown or short circuit. The main reason is that under extreme electrical stress such as current or voltage surges, the device has limited protection for the gate dielectric layer at the corners of the trench; the on-resistance has a negative temperature coefficient at negative temperatures, and after passing an inflection point of about 0 to 25°C, it maintains a positive temperature coefficient, which causes the device to have a lower on-resistance near the inflection point; that is, the current devices are more suitable for application scenarios at room temperature, but for some application scenarios with higher temperatures, it is necessary to design devices with better on-resistance at higher temperatures.

[0061] Based on this, the present invention provides a new multi-channel modulated wide bandgap semiconductor device structure.

[0062] The following embodiments of the present invention are further described in detail in conjunction with the accompanying drawings and examples. The following examples are used to illustrate the present invention but cannot be used to limit the scope of the present invention.

[0063] It should be noted that the terms "first" and "second" and the like in the specification, claims and drawings of this application are used to distinguish different objects rather than to limit a specific order.

[0064] Example 1

[0065] like Figure 1 As shown, this embodiment provides a multi-channel modulated wide bandgap semiconductor device structure, including: a substrate 1, an epitaxial layer 2, an N+ current spreading layer 3, a first source N+ region 4, a second source N+ region 5, a first source P+ region 6, a second source P+ region 7, a first P-well region 8, a second P-well region 9, a P+ masking layer 10, a gate 11, a source 14 and a drain 15.

[0066] The epitaxial layer 2 , the N+ current spreading layer 3 and the source 14 are sequentially arranged on the substrate 1 ; and the drain 15 is arranged at the bottom of the substrate 1 .

[0067] In an optional example, the substrate 1 is a wide bandgap semiconductor material, which may be SiC, GaN, Ga2O3, AlN or the like.

[0068] Specifically, the gate 11, the P+ shielding layer 10, the second P-well region 9, the second source P+ region 7 and the second source N+ region 5 are all arranged in the middle area of ​​the N+ current expansion layer 3 along the first direction, wherein the second P-well region 9, the second source P+ region 7 and the second source N+ region 5 are located between the gate 11 and the P+ shielding layer 10, and the two second source N+ regions 5 are respectively located on both sides of the second source P+ region 7 along the second direction, and the two second P-well regions 9 are respectively located on the outside of the two second source N+ regions 5; so that the second source N+ region 5, the second P-well region 9 and the N+ current expansion layer 3 form a new current path; the P+ shielding layer 10 is arranged close to the epitaxial layer 2.

[0069] The deep masking structure formed by the P+ shielding layer 10 and the second P-well region 9 can better protect the groove angle of the gate 11 and improve the gate oxide reliability of the device. The second P-well region 9 is formed by ion implantation at the bottom of the trench after trench etching, and no additional mask is required. The P+ shielding layer 10 can be formed before trench etching, or it can be directly ion implanted together with the second P-well region 9 after trench etching. At the same time, it can also be formed by using the mask of the subsequent second source N+ region 5 to form an ion implantation area. The P+ shielding layer 10 has a higher concentration, which can better protect the groove angle of the gate 11 and reduce the electric field at the groove angle.

[0070] The upper side of the P+ shielding layer 10 contacts the second source P+ region 7 , and the P+ shielding layer 10 can be kept in a grounded state through the second source P+ region 7 , thereby enhancing the protection effect of the P+ shielding layer 10 on the gate 11 and better improving the dynamic characteristics of the device.

[0071] like Figure 1 As shown, there are two first source P+ regions 6 , which are respectively arranged on both sides of the N+ current spreading layer 3 along the second direction and spaced apart from the gate 11 .

[0072] A first P-well region 8 and a first source N+ region 4 are superimposed between the first source P+ region 6 and the gate 11 on either side. That is, there are two first P-well regions 8 and two first source N+ regions 4, which are respectively arranged on the left and right sides of the gate 11.

[0073] Specifically, the first P-well region 8 and the first source N+ region 4 are stacked and specifically include: the first source N+ region 4 is located above the first P-well region 8 , and the upper surface of the first source N+ region 4 contacts the lower surface of the interlayer dielectric layer 12 .

[0074] The first direction and the second direction are arranged vertically.

[0075] In an optional embodiment, the gate 11 includes a gate trench, a gate dielectric layer 1101 and polysilicon 1102;

[0076] The trench is arranged in the N+ current spreading layer 3 along the first direction, the gate dielectric layer 1101 is arranged on the inner wall side of the gate trench, and the polysilicon 1102 is arranged in the groove formed by the gate dielectric layer 1101 .

[0077] It should be noted that the middle region of the gate 11 is a split gate; the middle region of the split gate is filled with source metal.

[0078] The ion implantation of the second source N+ region 5 is performed at the bottom of the trench, and at the same time, the second source P+ region 7 is formed at the bottom of the trench by ion implantation, so that a new channel can be formed at the bottom of the trench. Figure 3 As shown, it is a multi-channel current path diagram. Multi-channel modulation can increase the current density of the device. More channels and more current paths can improve the conduction characteristics of the device.

[0079] like Figure 2 As shown, combined with the gate polysilicon layout, it can be seen that in the first direction, the middle area of ​​the gate 11 is in a hollow state, and the gate 11 is split into a split gate structure.

[0080] The polysilicon gate in the trench is in the form of a split gate, so that a good ohmic contact area can be formed between the two split gates, so that the second source N+ region 5 and the second source P+ region 7 are kept grounded at the same time, so that the second source N+ region 5, the second P-well region 9 and the N+ current expansion layer 3 can also form a new current path, thereby using multiple channels to modulate the trench MOSFET; at the same time, Figure 2 As shown, section B is a complete gate structure, which connects the split gates in section A together, thereby keeping the split gates in section A at the same potential.

[0081] Furthermore, the multi-channel modulated wide bandgap semiconductor device structure further includes an interlayer dielectric layer 12 ; the interlayer dielectric layer 12 covers the open portion of the groove formed by the gate dielectric layer 1101 .

[0082] In addition, the multi-channel modulated wide bandgap semiconductor device structure further includes a source ohmic contact region 13;

[0083] The source 14 contacts the first source N+ region 4 , the second source N+ region 5 , the first source P+ region 6 and the second source P+ region 7 through the source ohmic contact region 13 .

[0084] Compared with the prior art, the multi-channel modulated wide bandgap semiconductor device structure provided by this embodiment has the following beneficial effects:

[0085] (1) The deep shielding structure formed by the P+ shielding layer and the second P-well region can better protect the gate groove corner and improve the gate oxide reliability of the device; further, the P+ shielding layer can be kept in a grounded state through the second source P+ region, which enhances the protection of the P+ shielding layer on the gate and can better improve the dynamic characteristics of the device;

[0086] (2) The second source N+ region, the second P-well region and the N+ current extension layer will form a new current path, thereby utilizing multiple channels to modulate the trench MOSFET; multi-channel modulation can increase the current density of the device, and more channels and more current paths can improve the conduction characteristics of the device.

[0087] (3) Multi-channels can be designed with different threshold voltages. Different threshold voltages result in different on-resistances of the channels. Therefore, multi-channel modulation can control the on-resistance of the device channel region, and further control the positive temperature coefficient portion of the device's overall on-resistance, making the inflection point of the overall on-resistance from the negative temperature coefficient to the positive temperature coefficient controllable. In other words, the device can be modulated to have a lower on-resistance at a desired higher temperature. This type of device is more suitable for high-temperature application scenarios.

[0088] Example 2

[0089] This embodiment provides a method for manufacturing a multi-channel modulated wide bandgap semiconductor device structure, such as Figure 4 As shown, the operation is as follows:

[0090] Step S1: (cross section A&B) sequentially growing an epitaxial layer and an N+ current spreading layer on a substrate;

[0091] Step S2: (cross section A & B) forming a first P-well region by ion implantation, secondary epitaxy or growing a P-type oxide; forming a first source N+ region by ion implantation;

[0092] Step S3: (cross section A & B) forming a first source P+ region by ion implantation;

[0093] Step S4: (cross section A & B) dry etching to form a gate trench;

[0094] Step S5: (cross section A & B) forming a second P-well region by ion implantation;

[0095] Step S6: (Cross-section A & B) forming a P+ masking layer by P-type ion implantation;

[0096] Step S7: (Cross-section A&B) forming a second source N+ region and a second source P+ region by ion implantation;

[0097] Step S8: (cross section A & B) growing and etching at the gate trench to form a gate;

[0098] Specifically including: gate dielectric layer growth, gate polysilicon growth and etching.

[0099] Step S9: (cross section A) etching the gate polysilicon to form a split gate; growing, depositing and etching at the gate to form an interlayer dielectric layer;

[0100] Step S10: (Section A and Section B) depositing an ohmic contact metal on the interlayer dielectric layer, the first source N+ region and the first source P+ region to form a source ohmic contact region;

[0101] Step S11: (Section A and Section B) deposit source metal to form a source; deposit drain metal at the bottom of the substrate to form a drain, thereby obtaining a wide bandgap semiconductor device structure with multi-channel modulation.

[0102] Since the manufacturing method is used to manufacture the multi-channel modulated wide bandgap semiconductor device structure provided in Example 1, the beneficial effects of the multi-channel modulated wide bandgap semiconductor device structure are also applicable to the manufacturing method. The beneficial effects can be referred to the above effect description and will not be repeated here.

[0103] Example 3

[0104] On the basis of the above-mentioned embodiments 1 and 2, the ion implantation of the P+ shielding layer 10 can be selectively performed before the formation of the second P-well region 9 in this embodiment, so that a wider P+ shielding layer 10 can be formed, and the width of the P+ shielding layer 10 is the same as the sum of the widths of the second P-well region 9, the second source P+ region 7 and the second source N+ region 5, and the obtained structure is as follows: Figure 5 As shown, this structure can better protect the gate groove angle and improve the reliability of the device. For the rest of the same structure, refer to the introduction of embodiment 1, which will not be repeated here.

[0105] Example 4

[0106] On the basis of the above-mentioned embodiment 3, this embodiment can also selectively perform ion implantation of the P+ shielding layer 10 before forming the second P-well region 9, so that a wider P+ shielding layer 10 can be formed, and the width of the P+ shielding layer 10 is greater than the sum of the widths of the second P-well region 9, the second source P+ region 7, and the second source N+ region 5. The obtained structure is as follows: Figure 6As shown, this structure can better protect the gate groove angle and improve the reliability of the device. For the rest of the same structure, refer to the introduction of embodiment 1, which will not be repeated here.

[0107] Example 5

[0108] Based on the above embodiment 1, the ion implantation of the first source P+ region 6 can be selected in this embodiment to be implanted deeper, and the obtained structure is as follows: Figure 7 As shown, in this structure, the first source P+ region 6, the P+ shielding layer 10 and the second P-well region 9 together form a better protection for the gate, reduce the gate oxide electric field, improve the device reliability, and better protect the gate groove angle to improve the device reliability. For the rest of the same structure, refer to the introduction of embodiment 1, which will not be repeated here.

[0109] Example 6

[0110] On the basis of the above-mentioned embodiments 1 and 2, this embodiment can selectively perform ion implantation of the second P-well region 9 before trench etching, so that the width of the second P-well region 9 can be greater than the trench width, which can provide better protection for the gate, reduce the gate oxide electric field, and improve device reliability. The obtained structure is as follows: Figure 8 For the rest of the same structure, refer to the introduction of embodiment 1, which will not be described here.

[0111] Example 7

[0112] On the basis of the above-mentioned embodiments 1 and 2, this embodiment can selectively implant the ions of the first source P+ region 6 and the P+ shielding layer 10 deeper at the same time, which can better protect the gate, reduce the gate oxide electric field, and improve the reliability of the device; at the same time, the electric field can be modulated to form a super junction effect, and the electrical characteristics of the device can be improved. The obtained structure is as follows Fig. 9 For the rest of the same structure, refer to the introduction of embodiment 1, which will not be described here.

[0113] In the description of this specification, the description with reference to the terms "specific example" or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the embodiments of the present invention. In this specification, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine different embodiments or examples described in this specification and the features of different embodiments or examples, unless they are contradictory.

[0114] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A multi-channel modulated wide bandgap semiconductor device structure, It is characterized in that include: Substrate, epitaxial layer, N+ current spreading layer, first source N+ region, second source N+ region, first source P+ region, second source P+ region, first P-well region, second P-well region, P+ shielding layer, gate, source and drain; The epitaxial layer, the N+ current spreading layer and the source electrode are sequentially arranged on the substrate; the drain electrode is arranged at the bottom of the substrate; The gate, the P+ shielding layer, the second P-well region, the second source P+ region and the second source N+ region are all arranged in the middle area of ​​the N+ current expansion layer along the first direction, wherein the second P-well region, the second source P+ region and the second source N+ region are located between the gate and the P+ shielding layer, and two second source N+ regions are respectively located on both sides of the second source P+ region along the second direction, and two second P-well regions are respectively located on the outside of two second source N+ regions; so that the second source N+ region, the second P-well region and the N+ current expansion layer form a new current path; the P+ shielding layer is arranged close to the epitaxial layer; Two first source P+ regions are respectively arranged on both sides of the N+ current spreading layer along the second direction and are spaced apart from the gate; the first P-well region and the first source N+ region are superimposed between the first source P+ region and the gate on either side; Wherein, the first direction and the second direction are arranged perpendicularly.

2. The multi-channel modulated wide bandgap semiconductor device structure according to claim 1, It is characterized in that The middle region of the gate is a split gate; The middle region of the split gate is filled with source metal.

3. The multi-channel modulated wide bandgap semiconductor device structure according to claim 2, It is characterized in that The gate comprises a gate trench, a gate dielectric layer and polysilicon; The trench is arranged in the N+ current spreading layer along the first direction, the gate dielectric layer is arranged on the inner wall side of the gate trench, and the polysilicon is arranged in a groove formed by the gate dielectric layer.

4. The multi-channel modulated wide bandgap semiconductor device structure according to claim 3, It is characterized in that The multi-channel modulated wide bandgap semiconductor device structure further includes an interlayer dielectric layer; The interlayer dielectric layer covers the open portion of the groove formed by the gate dielectric layer.

5. The multi-channel modulated wide bandgap semiconductor device structure according to claim 4, It is characterized in that The stacking of the first P-well region and the first source N+ region specifically includes: the first source N+ region is located above the first P-well region, and the upper surface of the first source N+ region contacts the lower surface of the interlayer dielectric layer.

6. The multi-channel modulated wide bandgap semiconductor device structure according to claim 5, It is characterized in that The multi-channel modulated wide bandgap semiconductor device structure further includes a source ohmic contact region; The source contacts the first source N+ region, the second source N+ region, the first source P+ region, and the second source P+ region through the source ohmic contact region.

7. The multi-channel modulated wide bandgap semiconductor device structure according to claim 1, It is characterized in that The substrate is a wide bandgap semiconductor material.

8. A method for manufacturing a multi-channel modulated wide bandgap semiconductor device structure as claimed in any one of claims 1 to 7, It is characterized in that include: An epitaxial layer and an N+ current spreading layer are sequentially grown on the substrate; Forming a first P-well region by ion implantation, secondary epitaxy or growing a P-type oxide; forming a first source N+ region by ion implantation; forming a first source P+ region by ion implantation; Dry etching to form a gate trench; forming a second P-well region by ion implantation; Forming a P+ masking layer by P-type ion implantation; forming a second source N+ region and a second source P+ region by ion implantation; Growing and etching to form a gate at the gate trench; Growing, depositing and etching to form an interlayer dielectric layer at the gate; Depositing source metal on the interlayer dielectric layer to form a source electrode; A drain metal is deposited at the bottom of the substrate to form a drain, thereby obtaining a multi-channel modulated wide bandgap semiconductor device structure.

9. The method according to claim 8, It is characterized in that The step of growing and etching the gate at the gate trench specifically includes: Gate dielectric layer growth, gate polysilicon growth and etching; The gate polysilicon is etched to form a split gate.

10. The method according to claim 9, It is characterized in that Before depositing the source metal on the interlayer dielectric layer, the method further includes: An ohmic contact metal is deposited on the interlayer dielectric layer, the first source N+ region and the first source P+ region to form a source ohmic contact region.

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