MOSFET device and manufacturing method of MOSFET device

Abstract

The invention provides an MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) device and a manufacturing method of the MOSFET device, and the MOSFET device comprises a substrate which is made of silicon carbide; the epitaxial layer is located on the surface of the substrate; the trench gate structure is located in the epitaxial layer; the source region is located on one side of the trench gate structure in the first direction, the first direction is perpendicular to the thickness direction of the substrate, and the doping type of the source region is the same as that of the epitaxial layer; the drain region is located on the other side of the trench gate structure in the first direction, and the doping type of the drain region is the same as that of the epitaxial layer; the doped region is at least partially located on the side, away from the trench gate structure, of the source region in the first direction, and the doping type of the doped region is different from that of the epitaxial layer; the metal layer is located on the surface, away from the substrate, of the epitaxial layer, and the metal layer comprises a source electrode metal part and a drain electrode metal part. And the MOSFET device can meet the requirement of CSP (Chip Scale Package).

Description

Technical Field

[0001] The present application relates to the field of semiconductors, and in particular to a MOSFET device and a method for manufacturing the MOSFET device. Background Art

[0002] Chip Scale Package (CSP) is an advanced packaging technology, and also a packaging technology that uses chip size as the basic unit of packaging. It reduces the size of the packaged chip to 1 / 9~1 / 16 of the traditional package. This technology has the characteristics of small size, high density, high precision, low cost and low power consumption.

[0003] Therefore, there is an urgent need for a MOSFET device that can be suitable for CSP packaging. Summary of the invention

[0004] The main purpose of the present application is to provide a MOSFET device and a method for manufacturing the MOSFET device, so as to at least solve the problem of how to adapt the MOSFET device to the requirements of CSP packaging in the prior art.

[0005] According to one aspect of the present application, a MOSFET device is provided, comprising: a substrate, wherein the material of the substrate comprises silicon carbide; an epitaxial layer, located on the surface of the substrate; a trench gate structure, located in the epitaxial layer; a source region, located in the epitaxial layer and located on one side of the trench gate structure in a first direction, wherein the first direction is perpendicular to the thickness direction of the substrate, and the doping type of the source region is the same as the doping type of the epitaxial layer; a drain region, located in the epitaxial layer and located on the other side of the trench gate structure in the first direction, and the doping type of the drain region is the same as the doping type of the epitaxial layer; a doped region, located in the epitaxial layer and located on the other side of the trench gate structure in the first direction, and the doping type of the drain region is the same as the doping type of the epitaxial layer; At least partially located upward on a side of the source region away from the trench gate structure, the doping type of the doping region is different from the doping type of the epitaxial layer; a metal layer, located on a surface of the epitaxial layer away from the substrate, the metal layer includes a source metal portion and a drain metal portion, there is a gap between the source metal portion and the drain metal portion, there is a gap between the orthographic projection of the metal layer on the substrate and the orthographic projection of the trench gate structure on the substrate, the orthographic projection of the source metal portion on the substrate at least partially overlaps with the orthographic projection of the source region on the substrate, and the orthographic projection of the drain metal portion on the substrate at least partially overlaps with the orthographic projection of the drain region on the substrate.

[0006] Optionally, the MOSFET device further includes: a doping portion located in the epitaxial layer and contactingly located on a surface of the trench gate structure close to the substrate.

[0007] Optionally, the doping region includes: a first sub-doping region, located on a side of the source region away from the trench gate structure in the first direction; a second sub-doping region, located on a side of the trench gate structure in the first direction, the first sub-doping region and the second sub-doping region are located on the same side of the trench gate structure, and in the second direction, the second sub-doping region is located on a side of the first sub-doping region close to the substrate, and the first sub-doping region and the second sub-doping region have the same doping type.

[0008] Optionally, the length of the second sub-doped region close to the substrate and the predetermined surface is a first length, the length of the trench gate structure close to the substrate and the predetermined surface is a second length, the first length is greater than the second length, the predetermined surface is the surface of the substrate close to the epitaxial layer, the surface of the source region away from the substrate, the surface of the drain region away from the substrate, the surface of the first sub-doped region away from the substrate, and the surface of the trench gate structure away from the substrate are flush.

[0009] Optionally, the MOSFET device further comprises: a dielectric layer located on a surface of the epitaxial layer away from the substrate, the dielectric layer comprising a plurality of dielectric portions, and a gap exists between two adjacent dielectric portions.

[0010] Optionally, the trench gate structure includes: at least one conductive dielectric layer located in the epitaxial layer; a gate oxide layer, located in contact with both sides of the conductive dielectric layer in a first direction, and located in contact with a side of the conductive dielectric layer close to the substrate in a second direction, the first direction is perpendicular to the thickness direction of the MOSFET device, and the second direction is perpendicular to the first direction.

[0011] Optionally, there are a plurality of conductive medium layers, and the plurality of conductive medium layers are arranged at intervals along the first direction.

[0012] Optionally, the gate oxide layer includes a first connecting portion, a second connecting portion and a third connecting portion connected in sequence, wherein the width of the first connecting portion along the first direction is a first width, the width of the second connecting portion along the second direction is a second width, the width of the third connecting portion along the first direction is a third width, the second width is greater than the first width, and the second width is greater than the third width.

[0013] Optionally, the gate oxide layer includes a first connecting portion, a second connecting portion and a third connecting portion connected in sequence, wherein the width of the first connecting portion along the first direction is a first width, the width of the second connecting portion along the second direction is a second width, and the width of the third connecting portion along the first direction is a third width, the first width is greater than the second width, and the third width is greater than the second width.

[0014] According to another aspect of the present application, a method for manufacturing a MOSFET device is provided, comprising: providing a substrate, wherein the material of the substrate comprises silicon carbide; forming a first preliminary epitaxial layer on a surface of one side of the substrate, and performing ion implantation treatment on the first preliminary epitaxial layer to obtain a preliminary doping region, and the remaining first preliminary epitaxial layer forms a second preliminary epitaxial layer, wherein the preliminary doping region is located on one side of the second preliminary epitaxial layer in a first direction, and is located on a side of the second preliminary epitaxial layer away from the substrate in a second direction; performing ion implantation on the preliminary doping region and the second preliminary epitaxial layer to form a third preliminary epitaxial layer; and sequentially removing a portion of the third preliminary epitaxial layer, the preliminary doping region, and the second preliminary epitaxial layer. A prepared epitaxial layer, the remaining third prepared epitaxial layer and the remaining prepared doped region form a source region, a drain region and a doped region, the remaining second prepared epitaxial layer forms an epitaxial layer with a groove, the doping type of the source region, the doping type of the drain region and the doping type of the first prepared epitaxial layer are the same, the doping type of the prepared doped region and the doping type of the first prepared epitaxial layer are different; a trench gate structure is formed in the groove; a prepared metal layer is formed on the surface of the trench gate structure away from the substrate and on the surface of the epitaxial layer away from the substrate, a portion of the prepared metal layer is removed, and the remaining prepared metal layer forms a metal layer, the metal layer includes a source metal portion and a drain metal portion with a gap.

[0015] By applying the technical solution of the present application, a MOSFET device is provided, comprising a silicon carbide substrate, an epitaxial layer located on the surface of the substrate, a trench gate structure located in the epitaxial layer, a source region, a drain region and a doped region, and a metal layer located on one side of the epitaxial layer; the source region is located on one side of the trench gate structure in a first direction, and the doping type of the source region is the same as the doping type of the epitaxial layer; the drain region is located on the other side of the trench gate structure in the first direction, and the doping type of the drain region is the same as the doping type of the epitaxial layer; the doped region is at least partially located on the side of the source region away from the trench gate structure in the first direction, and the doping type of the doped region is different from the doping type of the epitaxial layer; the metal layer comprises a source metal part and a drain metal part, there is a gap between the source metal part and the drain metal part, there is a gap between the orthographic projection of the metal layer on the substrate and the orthographic projection of the trench gate structure on the substrate, the orthographic projection of the source metal part on the substrate at least partially overlaps with the orthographic projection of the source region on the substrate, and the orthographic projection of the drain metal part on the substrate at least partially overlaps with the orthographic projection of the drain region on the substrate. On the one hand, by arranging the source metal part and the drain metal part on the surface of the same side of the MOSFET device, it can be ensured that the surface through-holes of the device are directly connected when CSP packaging is performed. On the other hand, by isolating the source metal part and the drain metal part through the trench gate structure, the current path length between the source and the drain can be increased, and the length of the voltage-resistant layer between the source and the drain can be increased in disguise, which can avoid the problem of increased device size caused by increased thickness of the voltage-resistant layer of the MOSFET device, and further meet the requirements of small size of CSP packaging. The problem of how MOSFET devices in the prior art are suitable for CSP packaging requirements is solved. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The drawings constituting part of the present application are used to provide a further understanding of the present application. The illustrative embodiments and descriptions of the present application are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0017] Figure 1 A schematic structural diagram of a MOSFET device provided in an embodiment of the present application is shown;

[0018] Figure 2 A schematic structural diagram of another MOSFET device provided according to an embodiment of the present application is shown;

[0019] Figure 3 A schematic structural diagram of another MOSFET device provided according to an embodiment of the present application is shown;

[0020] Figure 4 A schematic structural diagram of another MOSFET device provided in an embodiment of the present application is shown;

[0021] Figure 5A schematic structural diagram of another MOSFET device provided according to an embodiment of the present application is shown;

[0022] Figure 6 A schematic structural diagram of another MOSFET device provided according to an embodiment of the present application is shown;

[0023] Figure 7 A schematic structural diagram of another MOSFET device provided in an embodiment of the present application is shown;

[0024] Figure 8 A schematic structural diagram of another MOSFET device provided according to an embodiment of the present application is shown;

[0025] Fig. 9 A schematic flow chart of a method for manufacturing a MOSFET device provided according to an embodiment of the present application is shown;

[0026] Fig.10 A schematic diagram of a process of sequentially forming a first preliminary epitaxial layer, a preliminary doped region, a third preliminary epitaxial layer, forming a groove, a trench gate structure and a preliminary metal layer on a substrate according to an embodiment of the present application is shown;

[0027] Fig.11 Shown in Fig.10 (d) A schematic diagram of a structure in which a doping portion is formed on the basis of the above;

[0028] Fig.12 Shown in Fig.11 A schematic diagram of a structure in which a gate oxide layer is formed on the basis of

[0029] Fig.13 Shown in Fig.13 A schematic diagram of a structure in which a conductive dielectric layer is formed on the basis of the conductive dielectric layer;

[0030] Fig.14 Shown in Fig.13 Schematic diagram of the structure in which two conductive dielectric layers are formed on the basis of.

[0031] The above drawings include the following reference numerals:

[0032] 100, substrate; 101, epitaxial layer; 102, trench gate structure; 103, source region; 104, drain region; 105, doping region; 106, metal layer; 107, doping portion; 108, first sub-doping region; 109, second sub-doping region; L1, first length; L2, second length; D1, first direction; D2, second direction; 110, dielectric layer; 112, conductive dielectric layer; 113, gate oxide layer; 114, first connecting portion; 115, second connecting portion; 116, third connecting portion; 117, first preliminary epitaxial layer; 118, preliminary doping region; 119, second preliminary epitaxial layer; 120, third preliminary epitaxial layer; 121, groove; 122, preliminary metal layer. DETAILED DESCRIPTION

[0033] It should be noted that the following detailed descriptions are illustrative and are intended to provide further explanation of the present application. Unless otherwise specified, all technical and scientific terms used herein have the same meanings as those commonly understood by those skilled in the art to which the present application belongs.

[0034] It should be noted that the terms used herein are only for describing specific embodiments and are not intended to limit the exemplary embodiments according to the present application. As used herein, unless the context clearly indicates otherwise, the singular form is also intended to include the plural form. In addition, it should be understood that when the terms "comprise" and / or "include" are used in this specification, it indicates the presence of features, steps, operations, devices, components and / or combinations thereof.

[0035] It should be understood that when an element (such as a layer, film, region, or substrate) is described as being "on" another element, the element may be directly on the other element, or there may be intermediate elements. Moreover, in the specification and claims, when it is described that an element is "connected" to another element, the element may be "directly connected" to the other element, or "connected" to the other element through a third element.

[0036] It should be clear that the described embodiments are only part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0037] It should be understood that the term "and / or" used in this article is only a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship.

[0038] As introduced in the background technology, the prior art lacks MOSFET devices suitable for CSP packaging. To solve the above problem, the embodiments of the present application provide a MOSFET device and a method for manufacturing the MOSFET device.

[0039] The technical solutions in the embodiments of the present invention will be described clearly and completely below in conjunction with the accompanying drawings in the embodiments of the present invention.

[0040] Figure 1 Schematic diagram of the structure of a MOSFET device according to an embodiment of the present application. Figure 1 As shown, the MOSFET device includes:

[0041] A substrate 100, wherein the material of the substrate 100 includes silicon carbide;

[0042] The epitaxial layer 101 is located on the surface of the substrate 100;

[0043] A trench gate structure 102 is located in the epitaxial layer 101;

[0044] A source region 103, located in the epitaxial layer and on one side of the trench gate structure in a first direction D1, wherein the first direction D1 is perpendicular to the thickness direction of the substrate, and the doping type of the source region 103 is the same as the doping type of the epitaxial layer;

[0045] A drain region 104, located in the epitaxial layer and on the other side of the trench gate structure in the first direction D1, wherein the doping type of the drain region 104 is the same as the doping type of the epitaxial layer;

[0046] a doping region 105 located in the epitaxial layer and at least partially located on a side of the source region 103 away from the trench gate structure 102 in the first direction D1, wherein the doping type of the doping region 105 is different from the doping type of the epitaxial layer;

[0047] The metal layer 106 is located on the surface of the epitaxial layer away from the substrate. The metal layer 106 includes a source metal portion and a drain metal portion. There is a gap between the source metal portion and the drain metal portion. There is a gap between the orthographic projection of the metal layer 106 on the substrate and the orthographic projection of the trench gate structure on the substrate. The orthographic projection of the source metal portion on the substrate at least partially overlaps with the orthographic projection of the source region 103 on the substrate. The orthographic projection of the drain metal portion on the substrate at least partially overlaps with the orthographic projection of the drain region 104 on the substrate.

[0048] In practical applications, the epitaxial layer can be a single-layer structure or a multi-layer structure. The trench gate structure is actually a trench gate, which can reduce the on-resistance of the MOSFET device and reduce the area of ​​the chip. The specific positions of the source metal part and the drain metal part can be set arbitrarily, and can be set on the left or right side. The bottom surface of the metal layer is in direct contact with the top surface of the epitaxial layer.

[0049] Through this embodiment, a MOSFET device is provided, including a silicon carbide substrate, an epitaxial layer located on the surface of the substrate, a trench gate structure located in the epitaxial layer, a source region, a drain region and a doped region, and a metal layer located on one side of the epitaxial layer; the source region is located on one side of the trench gate structure in a first direction, and the doping type of the source region is the same as the doping type of the epitaxial layer; the drain region is located on the other side of the trench gate structure in the first direction, and the doping type of the drain region is the same as the doping type of the epitaxial layer; the doped region is at least partially located on the side of the source region away from the trench gate structure in the first direction, and the doping type of the doped region is different from the doping type of the epitaxial layer; the metal layer includes a source metal part and a drain metal part, there is a gap between the source metal part and the drain metal part, there is a gap between the orthographic projection of the metal layer on the substrate and the orthographic projection of the trench gate structure on the substrate, the orthographic projection of the source metal part on the substrate at least partially overlaps with the orthographic projection of the source region on the substrate, and the orthographic projection of the drain metal part on the substrate at least partially overlaps with the orthographic projection of the drain region on the substrate. On the one hand, by arranging the source metal part and the drain metal part on the surface of the same side of the MOSFET device, it can be ensured that the surface through-holes of the device are directly connected when CSP packaging is performed. On the other hand, by isolating the source metal part and the drain metal part through the trench gate structure, the current path length between the source and the drain can be increased, and the length of the voltage-resistant layer between the source and the drain can be increased in disguise, which can avoid the problem of increased device size caused by increased thickness of the voltage-resistant layer of the MOSFET device, and further meet the requirements of small size of CSP packaging. The problem of how MOSFET devices in the prior art are suitable for CSP packaging requirements is solved.

[0050] In a specific embodiment, Figure 2 As shown, the MOSFET device further includes: a doping portion 107, which is located in the epitaxial layer 101 and is located on the surface of the trench gate structure 102 close to the substrate 100. The remaining source region 103, drain region 104, doping region 105 and metal layer 106 are located at the same position as the source region 103, drain region 104, doping region 105 and metal layer 106. Figure 1 By providing the above-mentioned doping part, the problem of easy breakdown of the bottom of the trench gate structure can be prevented, and the performance of the MOSFET device can be further improved.

[0051] In the prior art, since the oxidation rate of the bottom of the trench of the trench MOSFET device is much lower than the oxidation rate of the trench sidewall during the gate oxide preparation process, the gate oxide quality of the bottom of the trench is poor, the electric field concentration is prone to occur at the corner of the bottom of the trench, and the device breakdown characteristics are deteriorated. By providing a doping portion at the bottom of the trench gate structure, the doping concentration of the channel region can be increased, the electrical characteristics of the bottom of the trench can be improved, the current concentration at the bottom of the channel can be reduced, and the intensity of the electric field can be reduced, and the breakdown voltage of the channel can be increased, thereby reducing the breakdown risk.

[0052] In order to further improve the bidirectional conduction capability of the MOSFET device in the first direction, as Figure 3 As shown, the doping region 105 includes: a first sub-doping region 108, which is located on the side of the source region 103 away from the trench gate structure 102 in the first direction D1; a second sub-doping region 109, which is located on the side of the trench gate structure in the first direction D1, the first sub-doping region 108 and the second sub-doping region 109 are located on the same side of the trench gate structure, and in the second direction D2, the second sub-doping region 109 is located on the side of the first sub-doping region 108 close to the substrate, and the first sub-doping region 108 and the second sub-doping region 109 have the same doping type. The positions of the remaining drain region 104, the metal layer 106 and the doping portion 107 are arranged in the same manner as above. Figure 2 , I will not go into details here.

[0053] Specifically, the epitaxial layer wraps the bottom and the sidewall of one side of the trench gate structure, the second sub-doping region is formed on the side of the trench gate structure, and the first sub-doping region is formed on the surface of the second sub-doping region. In an N-channel MOSFET device, the P-type second sub-doping region can form a PN junction with the source metal part and the drain metal part, so that the current can flow bidirectionally between the source metal part and the drain metal part. Similarly, in a P-channel MOSFET device, the N-type second sub-doping region can form a PN junction with the source metal part and the drain metal part, further realizing the bidirectional conduction capability.

[0054] like Figure 3As shown, the length of the surface of the second sub-doping region 109 close to the substrate 100 from the predetermined surface is a first length L1, the length of the surface of the trench gate structure 102 close to the substrate 100 from the predetermined surface is a second length L2, the first length L1 is greater than the second length L2, the predetermined surface is the surface of the substrate 100 close to the epitaxial layer 101, the surface of the source region away from the substrate 100, the surface of the drain region 104 away from the substrate 100, the surface of the first sub-doping region 108 away from the substrate 100, and the surface of the trench gate structure 102 away from the substrate 100 are flush. The above arrangement can further reduce the size of the MOSFET device, thereby improving the integration of the device.

[0055] Specifically, L1 being greater than L2 indicates that the depth of the second sub-doping region is less than the depth of the trench. When the depth of the well region is small, the distance between the channel region and the source and drain increases, thereby reducing the leakage current, and also helping to reduce the size of the MOSFET device, thereby improving the integration. In addition, the upper surface of the trench gate is flush with the upper surface of the epitaxial layer, and the parasitic capacitance between the gate metal part and the drain metal part is reduced, especially in high-frequency applications, because lower parasitic capacitance can improve speed and performance. In addition, the flush surface can also ensure that the channel is formed more evenly around the trench gate, thereby providing better channel control.

[0056] like Figure 4 As shown, the MOSFET device further includes: a dielectric layer 110, which is located on the surface of the epitaxial layer 101 away from the substrate 100, and the dielectric layer 110 includes a plurality of dielectric parts, and there is a gap between two adjacent dielectric parts. The positions of the remaining source region 103, drain region 104, doped region 105, metal layer 106, doped part 107, first sub-doped region 108 and second sub-doped region 109 are arranged in the same manner as Figure 3 The above arrangement can further realize effective isolation of the source metal portion and the drain metal portion.

[0057] Specifically, the dielectric layer is used to isolate adjacent source metal parts and drain metal parts.

[0058] In some other embodiments, Figure 5As shown, the trench gate structure 102 includes: at least one conductive dielectric layer 112, located in the epitaxial layer 101; a gate oxide layer 113, located on both sides of the conductive dielectric layer 112 in a first direction D1, and located on a side of the conductive dielectric layer 112 close to the substrate 100 in a second direction D2. The first direction D1 is perpendicular to the thickness direction of the MOSFET device, and the second direction D2 is perpendicular to the first direction. The remaining source region 103, drain region 104, doped region 105, metal layer 106, doped portion 107, first sub-doped region 108, second sub-doped region 109 and dielectric layer 110 are connected to the substrate 100. Figure 4 The above-mentioned trench gate structure can further realize the transmission of gate signals.

[0059] Specifically, the conductive dielectric layer is used to transmit gate signals, and the material of the conductive dielectric layer can be polysilicon. Since polysilicon has good conductivity, it is very suitable as a conductive path for transmitting gate signals. In addition, compared with other possible gate materials (such as metal materials), polysilicon has a lower cost, which helps to reduce the production cost of MOSFET devices.

[0060] In other embodiments, Figure 6 As shown, there are a plurality of the conductive dielectric layers 112, and the plurality of the conductive dielectric layers 112 are arranged at intervals along the first direction D1. The remaining substrate 100, epitaxial layer 101, trench gate structure 102, source region 103, drain region 104, doped region 105, metal layer 106, doped portion 107, first sub-doped region 108, second sub-doped region 109 and dielectric layer 110 are connected to the substrate 100. Figure 5 The above split gate setting can further adjust the capacitance and dynamic characteristics of the MOSFET device.

[0061] In practical applications, of the two conductive dielectric layers, only the left conductive dielectric layer can be used as the actual gate, and the right conductive dielectric layer can be used as a dummy gate to connect the source signal or float to adjust the capacitance and dynamic characteristics of the MOSFET device. In addition, the number of the conductive dielectric layers is not limited to Figure 6 The number of the conductive medium layers may be two or more than two. The sizes of the intervals between the conductive medium layers may be the same or different.

[0062] like Figure 7As shown, the gate oxide layer 113 includes a first connection portion 114, a second connection portion 115 and a third connection portion 116 connected in sequence, wherein the width of the first connection portion 114 along the first direction D1 is a first width, the width of the second connection portion 115 along the second direction D2 is a second width, the width of the third connection portion 116 along the first direction D1 is a third width, the second width is greater than the first width, and the second width is greater than the third width. The remaining substrate 100, epitaxial layer 101, trench gate structure 102, source region 103, drain region 104, doping region 105, metal layer 106, doping portion 107, first sub-doping region 108, second sub-doping region 109 and dielectric layer 110 and Figure 5 By setting the width of the second connection portion to be greater than the width of the first connection portion, and the width of the second connection portion to be greater than the width of the third connection portion, the problem of easy breakdown of the bottom of the trench gate structure can be prevented, and the performance of the MOSFET device can be further improved.

[0063] In the prior art, since the oxidation rate of the bottom of the trench of the trench MOSFET device is much lower than the oxidation rate of the sidewall of the trench during the gate oxide preparation process, the gate oxide quality of the bottom of the trench is poor, and the electric field concentration is prone to occur at the corner of the bottom of the trench, and the device breakdown characteristics are deteriorated. By providing a thicker gate oxide layer at the bottom of the trench gate structure, the trench gate structure is protected, thereby reducing the risk of breakdown. In addition, the width of the first connecting portion may be the same as or different from the width of the third connecting portion.

[0064] In another embodiment, Figure 8 As shown, the gate oxide layer 113 includes a first connection portion 114, a second connection portion 115 and a third connection portion 116 connected in sequence, wherein the width of the first connection portion 114 along the first direction D1 is a first width, the width of the second connection portion 115 along the second direction D2 is a second width, the width of the third connection portion 116 along the first direction D1 is a third width, the first width is greater than the second width, and the third width is greater than the second width. The remaining substrate 100, epitaxial layer 101, trench gate structure 102, source region 103, drain region 104, doping region 105, metal layer 106, doping portion 107, first sub-doping region 108, second sub-doping region 109, dielectric layer 110 and conductive dielectric layer 112 are connected to the ... Figure 5 By setting the width of the first connection portion to be greater than the width of the second connection portion, and the width of the third connection portion to be greater than the width of the second connection portion, the capacitance and dynamic characteristics of the MOSFET device can be further adjusted.

[0065] Specifically, the width of the first connection portion may be the same as or different from the width of the third connection portion.

[0066] The present application also provides a method for manufacturing a MOSFET device. Fig. 9 FIG. 1 is a flow chart of a method for manufacturing a MOSFET device according to an embodiment of the present application. Fig. 9 As shown, the method includes:

[0067] Step S201, providing a substrate 100, wherein the material of the substrate 100 includes silicon carbide;

[0068] Step S202, forming a first preliminary epitaxial layer 117 on the surface of one side of the substrate 100, Fig.10 (a), and the first preliminary epitaxial layer 117 is ion-implanted to obtain a preliminary doped region 118, and the remaining first preliminary epitaxial layer 117 forms a second preliminary epitaxial layer 119, and the preliminary doped region 118 is located on one side of the second preliminary epitaxial layer 119 in the first direction D1, and is located on the side of the second preliminary epitaxial layer 119 away from the substrate 100 in the second direction D2, to obtain Fig.10 (b) The structure shown;

[0069] Specifically, the first preliminary epitaxial layer can be formed by epitaxial growth, and the thickness and doping concentration of the first preliminary epitaxial layer can be determined by the specific specifications of the MOSFET device. The first preliminary epitaxial layer can be a single-layer structure or a multi-layer structure.

[0070] Step S203, ion implantation is performed on the above-mentioned preliminary doping region 118 and the above-mentioned second preliminary epitaxial layer 119 to form a third preliminary epitaxial layer 120, thereby obtaining Fig.10 (c) The structure shown;

[0071] Step S204, sequentially removing a portion of the third preliminary epitaxial layer 120, the preliminary doped region 118, and the second preliminary epitaxial layer 119, the remaining third preliminary epitaxial layer 120 and the remaining preliminary doped region 118 form a source region 103, a drain region 104, and a doped region 105, the remaining second preliminary epitaxial layer 119 forms an epitaxial layer 101 having a groove 121, the doping type of the source region 103, the doping type of the drain region 104, and the doping type of the first preliminary epitaxial layer 117 are the same, the doping type of the preliminary doped region 118 is different from the doping type of the first preliminary epitaxial layer 117, and the epitaxial layer 101 having a groove 121 is formed. Fig.10 (d) The structure shown;

[0072] Step S205, forming a trench gate structure 102 in the groove 121, obtaining Fig.10 (e) The structure shown;

[0073] Specifically, the above trench gate structure is actually a trench gate, and the trench gate structure can reduce the on-resistance of the MOSFET device and reduce the area of ​​the chip.

[0074] Step S206, forming a preliminary metal layer 122 on the surface of the trench gate structure 102 away from the substrate 100 and on the surface of the epitaxial layer 101 away from the substrate 100, to obtain Fig.10 (f) The structure shown in FIG. 1 is obtained by removing part of the above-mentioned preliminary metal layer 122, and the remaining above-mentioned preliminary metal layer 122 forms a metal layer 106, and the above-mentioned metal layer 106 includes a source metal portion and a drain metal portion with a gap, so as to obtain Figure 1 The structure shown.

[0075] Specifically, the specific positions of the source metal part and the drain metal part can be set arbitrarily, and can be set on the left side or the right side. The bottom surface of the metal layer is in direct contact with the top surface of the epitaxial layer.

[0076] In this embodiment, a method for manufacturing a MOSFET device is provided. First, a substrate is provided, wherein the material of the substrate includes silicon carbide; a first preliminary epitaxial layer is formed on a surface of one side of the substrate, and the first preliminary epitaxial layer is ion-implanted to obtain a preliminary doping region, and the remaining first preliminary epitaxial layer forms a second preliminary epitaxial layer, wherein the preliminary doping region is located on one side of the second preliminary epitaxial layer in a first direction, and is located on a side of the second preliminary epitaxial layer away from the substrate in a second direction; ion implantation is then performed on the preliminary doping region and the second preliminary epitaxial layer to form a third preliminary epitaxial layer; and then, a portion of the third preliminary epitaxial layer, the preliminary doping region, and the first preliminary epitaxial layer are sequentially removed. The second prepared epitaxial layer, the remaining third prepared epitaxial layer and the remaining prepared doped region form a source region, a drain region and a doped region, the remaining second prepared epitaxial layer forms an epitaxial layer with a groove, the doping type of the source region, the doping type of the drain region and the doping type of the first prepared epitaxial layer are the same, and the doping type of the prepared doped region is different from the doping type of the first prepared epitaxial layer; a trench gate structure is formed in the groove; finally, a prepared metal layer is formed on the surface of the trench gate structure away from the substrate and on the surface of the epitaxial layer away from the substrate, a part of the prepared metal layer is removed, and the remaining prepared metal layer forms a metal layer, and the metal layer includes a source metal part and a drain metal part with an interval. In the above method, on the one hand, by arranging the source metal part and the drain metal part on the surface of the same side of the MOSFET device, it can be ensured that the surface through hole of the device is directly connected when the CSP package is performed. On the other hand, by isolating the source metal part and the drain metal part through the trench gate structure, the current path length between the source and the drain can be increased, and the length of the voltage-resistant layer between the source and the drain can be increased in disguise, which can avoid the problem of increased device size caused by the increase in the thickness of the voltage-resistant layer of the MOSFET device, and further meet the demand for small size of CSP packaging. The problem of how to adapt MOSFET devices to the requirements of CSP packaging in the prior art is solved.

[0077] As an optional solution, after the above step S204 and before the step S205, the above method further includes: step S206, forming a doping portion 107 in the above groove 121, so as to obtain Fig.11 The remaining substrate 100, epitaxial layer 101, source region 103, drain region 104, and doped region 105 are arranged in the same position as Figure 1 The method can prevent the problem of easy breakdown of the bottom of the trench gate structure by setting the above-mentioned doping part, and further improve the performance of the MOSFET device.

[0078] In the prior art, since the oxidation rate of the bottom of the trench of the trench MOSFET device is much lower than the oxidation rate of the trench sidewall during the gate oxide preparation process, the gate oxide quality of the bottom of the trench is poor, the electric field concentration is prone to occur at the corner of the bottom of the trench, and the device breakdown characteristics are deteriorated. By providing a doping portion at the bottom of the trench gate structure, the doping concentration of the channel region can be increased, the electrical characteristics of the bottom of the trench can be improved, the current concentration at the bottom of the channel can be reduced, and the intensity of the electric field can be reduced, and the breakdown voltage of the channel can be increased, thereby reducing the breakdown risk.

[0079] In another embodiment, the above step S205 can also be implemented by the following steps: Step S2051, forming a gate oxide layer 113 on the exposed surface of the above groove 121, Fig.12 Step S2052, forming a conductive dielectric layer 112 on the exposed surface of the gate oxide layer 113, and obtaining Fig.13 The positions of the substrate 100, the epitaxial layer 101, the source region 103, the drain region 104, the first sub-doping region 108 and the second sub-doping region 109 are arranged in the same manner as Figure 1 This method can further realize the transmission of gate signals.

[0080] Specifically, the conductive dielectric layer is used to transmit gate signals, and the material of the conductive dielectric layer can be polysilicon. Since polysilicon has good conductivity, it is very suitable as a conductive path for transmitting gate signals. In addition, compared with other possible gate materials (such as metal materials), the cost of polysilicon is lower, which helps to reduce the production cost of MOSFET devices. In addition, the number of the conductive dielectric layer 112 can also be multiple, such as Fig.14 As shown, the sizes of the intervals between the multiple conductive medium layers 112 can be the same or different.

[0081] From the above description, it can be seen that the above embodiments of the present application achieve the following technical effects:

[0082] 1) The MOSFET device of the present application comprises a silicon carbide substrate, an epitaxial layer located on the surface of the substrate, a trench gate structure located in the epitaxial layer, a source region, a drain region and a doped region, and a metal layer located on one side of the epitaxial layer; the source region is located on one side of the trench gate structure in a first direction, and the doping type of the source region is the same as the doping type of the epitaxial layer; the drain region is located on the other side of the trench gate structure in the first direction, and the doping type of the drain region is the same as the doping type of the epitaxial layer; the doped region is at least partially located between the trench gate structure and the source region in the first direction, and the doping type of the doped region is different from the doping type of the epitaxial layer; the metal layer comprises a source metal portion and a drain metal portion, there is a gap between the source metal portion and the drain metal portion, there is a gap between the orthographic projection of the metal layer on the substrate and the orthographic projection of the trench gate structure on the substrate, the orthographic projection of the source metal portion on the substrate at least partially overlaps with the orthographic projection of the source region on the substrate, and the orthographic projection of the drain metal portion on the substrate at least partially overlaps with the orthographic projection of the drain region on the substrate. On the one hand, by arranging the source metal part and the drain metal part on the surface of the same side of the MOSFET device, it can be ensured that the surface through-holes of the device are directly connected when CSP packaging is performed. On the other hand, by isolating the source metal part and the drain metal part through the trench gate structure, the current path length between the source and the drain can be increased, and the length of the voltage-resistant layer between the source and the drain can be increased in disguise, which can avoid the problem of increased device size caused by increased thickness of the voltage-resistant layer of the MOSFET device, and further meet the requirements of small size of CSP packaging. The problem of how MOSFET devices in the prior art are suitable for CSP packaging requirements is solved.

[0083] 2) A method for manufacturing a MOSFET device of the present application, first, providing a substrate, wherein the material of the substrate includes silicon carbide; forming a first preliminary epitaxial layer on a surface of one side of the substrate, and performing ion implantation on the first preliminary epitaxial layer to obtain a preliminary doped region, and the remaining first preliminary epitaxial layer forms a second preliminary epitaxial layer, wherein the preliminary doped region is located on one side of the second preliminary epitaxial layer in a first direction, and is located on a side of the second preliminary epitaxial layer away from the substrate in a second direction; then performing ion implantation on the preliminary doped region and the second preliminary epitaxial layer to form a third preliminary epitaxial layer; then, removing part of the third preliminary epitaxial layer, the preliminary doped region, and the second preliminary epitaxial layer in sequence; A preparation epitaxial layer is prepared, the remaining third preparation epitaxial layer and the remaining preparation doping region form a source region, a drain region and a doping region, the remaining second preparation epitaxial layer forms an epitaxial layer with a groove, the doping type of the source region, the doping type of the drain region and the doping type of the first preparation epitaxial layer are the same, and the doping type of the preparation doping region is different from the doping type of the first preparation epitaxial layer; a trench gate structure is formed in the groove; finally, a preparation metal layer is formed on the surface of the trench gate structure away from the substrate and on the surface of the epitaxial layer away from the substrate, a part of the preparation metal layer is removed, and the remaining preparation metal layer forms a metal layer, and the metal layer includes a source metal part and a drain metal part with an interval. In the above method, on the one hand, by arranging the source metal part and the drain metal part on the surface of the same side of the MOSFET device, it can be ensured that the surface through hole of the device is directly connected when the CSP package is performed. On the other hand, by isolating the source metal part and the drain metal part through the trench gate structure, the current path length between the source and the drain can be increased, and the length of the voltage-resistant layer between the source and the drain can be increased in disguise, which can avoid the problem of increased device size caused by the increase in the thickness of the voltage-resistant layer of the MOSFET device, and further meet the demand for small size of CSP packaging. The problem of how to adapt MOSFET devices to the requirements of CSP packaging in the prior art is solved.

[0084] The above description is only the preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A MOSFET device, characterized in that: include: A substrate, wherein the material of the substrate comprises silicon carbide; an epitaxial layer located on the surface of the substrate; A trench gate structure is located in the epitaxial layer; a source region, located in the epitaxial layer and on one side of the trench gate structure in a first direction, the first direction being perpendicular to a thickness direction of the substrate, the doping type of the source region being the same as the doping type of the epitaxial layer; a drain region, located in the epitaxial layer and on the other side of the trench gate structure in the first direction, the drain region having a doping type that is the same as the doping type of the epitaxial layer; a doped region located in the epitaxial layer and at least partially located on a side of the source region away from the trench gate structure in the first direction, wherein the doping type of the doped region is different from the doping type of the epitaxial layer; A metal layer is located on the surface of the epitaxial layer away from the substrate, the metal layer includes a source metal portion and a drain metal portion, there is a gap between the source metal portion and the drain metal portion, there is a gap between the orthographic projection of the metal layer on the substrate and the orthographic projection of the trench gate structure on the substrate, the orthographic projection of the source metal portion on the substrate at least partially overlaps with the orthographic projection of the source region on the substrate, and the orthographic projection of the drain metal portion on the substrate at least partially overlaps with the orthographic projection of the drain region on the substrate.

2. The MOSFET device according to claim 1, characterized in that The MOSFET device further comprises: The doped portion is located in the epitaxial layer and is contactingly located on a surface of the trench gate structure close to the substrate.

3. The MOSFET device according to claim 1, characterized in that: The doped region comprises: A first sub-doped region, located on a side of the source region away from the trench gate structure in the first direction; A second sub-doping region is located on one side of the trench gate structure in the first direction, the first sub-doping region and the second sub-doping region are located on the same side of the trench gate structure, and in the second direction, the second sub-doping region is located on a side of the first sub-doping region close to the substrate, and the first sub-doping region and the second sub-doping region have the same doping type.

4. The MOSFET device according to claim 3, characterized in that: The length from the surface of the second sub-doped region close to the substrate to the predetermined surface is a first length, the length from the surface of the trench gate structure close to the substrate to the predetermined surface is a second length, the first length is greater than the second length, the predetermined surface is the surface of the substrate close to the epitaxial layer, the surface of the source region away from the substrate, the surface of the drain region away from the substrate, the surface of the first sub-doped region away from the substrate, and the surface of the trench gate structure away from the substrate are flush.

5. The MOSFET device according to claim 1, characterized in that: The MOSFET device further comprises: The dielectric layer is located on the surface of the epitaxial layer away from the substrate. The dielectric layer includes a plurality of dielectric parts, and a gap is provided between two adjacent dielectric parts.

6. The MOSFET device according to claim 1, characterized in that: The trench gate structure comprises: at least one conductive dielectric layer located within the epitaxial layer; The gate oxide layer is located on both sides of the conductive dielectric layer in a first direction and in contact with the conductive dielectric layer on a side close to the substrate in a second direction. The first direction is perpendicular to the thickness direction of the MOSFET device, and the second direction is perpendicular to the first direction.

7. The MOSFET device according to claim 6, characterized in that: There are a plurality of conductive medium layers, and the plurality of conductive medium layers are arranged at intervals along the first direction.

8. The MOSFET device according to claim 6, characterized in that: The gate oxide layer includes a first connection portion, a second connection portion and a third connection portion connected in sequence, wherein the width of the first connection portion along the first direction is a first width, the width of the second connection portion along the second direction is a second width, the width of the third connection portion along the first direction is a third width, the second width is greater than the first width, and the second width is greater than the third width.

9. The MOSFET device according to claim 6, characterized in that: The gate oxide layer includes a first connection portion, a second connection portion and a third connection portion connected in sequence, wherein the width of the first connection portion along the first direction is a first width, the width of the second connection portion along the second direction is a second width, and the width of the third connection portion along the first direction is a third width, the first width is greater than the second width, and the third width is greater than the second width.

10. A method for manufacturing a MOSFET device, characterized in that: include: Providing a substrate, wherein the material of the substrate includes silicon carbide; Forming a first preliminary epitaxial layer on a surface of one side of the substrate, and performing ion implantation on the first preliminary epitaxial layer to obtain a preliminary doping region, the remaining first preliminary epitaxial layer forming a second preliminary epitaxial layer, the preliminary doping region being located on one side of the second preliminary epitaxial layer in a first direction, and on a side of the second preliminary epitaxial layer away from the substrate in a second direction; Performing ion implantation on the preliminary doping region and the second preliminary epitaxial layer to form a third preliminary epitaxial layer; Sequentially removing a portion of the third prepared epitaxial layer, the prepared doped region, and the second prepared epitaxial layer, the remaining third prepared epitaxial layer and the remaining prepared doped region form a source region, a drain region, and a doped region, the remaining second prepared epitaxial layer forms an epitaxial layer with a groove, the doping type of the source region, the doping type of the drain region, and the doping type of the first prepared epitaxial layer are the same, and the doping type of the prepared doped region is different from the doping type of the first prepared epitaxial layer; forming a trench gate structure in the groove; A preliminary metal layer is formed on the surface of the trench gate structure away from the substrate and on the surface of the epitaxial layer away from the substrate, a portion of the preliminary metal layer is removed, and the remaining preliminary metal layer forms a metal layer, the metal layer including a source metal portion and a drain metal portion with a gap.

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