Preparation method of TBC solar cell with edge winding plating layer

Abstract

The invention relates to the field of solar cells, and discloses a preparation method of a TBC solar cell with an edge winding plating layer. According to the method, an insulating dielectric film is pre-constructed at the edge of a silicon wafer through a special combined process of'direct oxidation-indirect deposition-high-temperature annealing '+ 'high-temperature densification + boron doping', so that an edge winding and plating area is insulated and isolated from a silicon wafer substrate, and therefore, even if a winding and plating layer exists at the edge of a finished TBC solar cell, the winding and plating part does not generate relatively large electric leakage; and secondly, the insulating dielectric film also has an excellent passivation effect, can further passivate the side surface area of the silicon wafer, and is beneficial to improving the electrical property of the battery. And finally, compared with a conventional TBC solar cell with all edges being pyramid suede surfaces, the edge part of the silicon wafer is the pyramid suede surface, the edge part of the silicon wafer is the polished surface, the edge suede-shaped silicon wafer is easier to cause silicon wafer fragments under the action of external force, and the polished surface is more beneficial to improving the yield of the cell.

Description

Technical Field

[0001] The invention relates to the field of solar cells, and in particular to a method for preparing a TBC solar cell with an edge wrap coating. Background Art

[0002] TBC solar cells combine the excellent tunneling oxide layer / doped polysilicon passivation contact technology and back electrode contact characteristics of mainstream TOPCon solar cells. They are the representative of the next generation of mainstream crystalline silicon solar cells and have the characteristics of high efficiency and strong aesthetics.

[0003] At present, in the preparation process of TBC solar cells, since it is necessary to use tubular vacuum equipment to deposit poly-Si on the back of the silicon wafer many times, it is inevitable that a wrap-around coating will be produced on the front and edge of the silicon wafer. In order to reduce the leakage effect caused by the wrap-around coating, a wet process is often required to remove the wrap-around coating on the front and edge of the silicon wafer to reduce the leakage value of the solar cell. At present, the common way to remove the wrap-around coating on the edge of TBC solar cells is the chain acid polishing process. However, since the rollers of the chain machine are difficult to keep horizontal during long-term use, the silicon wafer shakes up and down during the acid polishing process, and it is impossible to effectively ensure that the wrap-around coating on the edge of the silicon wafer is effectively removed. Therefore, there are still more or less wrap-around coating areas on the edge of the actual battery, which will undoubtedly lead to an increase in the battery leakage value and affect the final performance of the battery. Summary of the invention

[0004] In order to solve the above technical problems, the present invention provides a method for preparing a TBC solar cell with an edge wrapping layer. The present invention pre-constructs an insulating dielectric film at the edge of the silicon wafer through a special "direct oxidation-indirect deposition" + "high temperature densification + boron doping" combined process to insulate and isolate the edge wrapping area from the silicon wafer substrate. Therefore, even if there is a wrapping layer at the edge of the finished TBC solar cell, there will be no large leakage in the wrapping part. Secondly, the insulating dielectric film also has an excellent passivation effect, which can further passivate the side area of ​​the silicon wafer, which is beneficial to improving the electrical performance of the battery. In addition, compared with the conventional TBC solar cell whose edges are all pyramid velvet, the edge of the silicon wafer of the present invention is partially pyramid velvet and partially polished. The edge velvet-like silicon wafer is more likely to cause silicon wafer fragments under the action of external force, while the polished surface is more helpful to improve the cell yield.

[0005] The specific technical solution of the present invention is: a method for preparing a TBC solar cell with an edge wrap coating, specifically comprising the following steps: S1. Polishing both sides of the N-type silicon wafer.

[0006] S2. Stack several silicon wafers in layers to form a cubic silicon wafer combination.

[0007] Since the thickness of a single silicon wafer is relatively thin, it is difficult to directly deposit an insulating dielectric film on its edge. Therefore, the present invention ingeniously stacks multiple silicon wafers into a cubic silicon wafer combination, which can effectively increase the deposition area, facilitate deposition operation, and improve efficiency.

[0008] S3. Forming a first silicon oxide layer and a second silicon oxide layer on the edge of the silicon wafer in sequence by direct oxidation and indirect deposition, the combination of the two constitutes an insulating dielectric film.

[0009] After depositing the insulating dielectric film on the four sides of the edge of the silicon wafer, the silicon wafer substrate and the subsequent winding coating can be isolated to prevent leakage. Among them, the first silicon oxide layer is formed by in-situ oxidation of the shallow silicon atoms at the edge of the N-type silicon wafer through direct oxidation. Since the atoms on the surface of the silicon wafer substrate are arranged more closely, a relatively dense first silicon oxide layer can be directly generated; but since the silicon wafer substrate is N-type doped, the number of movable electrons in the substrate is more than that of intrinsic silicon oxide, so that the dielectric constant of the formed first silicon oxide layer is smaller and the insulation performance is weaker. For this reason, the present invention further deposits a second silicon oxide layer on its surface by indirect deposition. Different from direct oxidation to convert the shallow layer at the edge of the silicon wafer into the first silicon oxide layer, the deposition method can add a layer of intrinsic silicon oxide film (i.e., the second silicon oxide layer) on the surface of the first silicon oxide layer, which has fewer movable electrons in the substrate and better insulation performance. The above two steps can be performed sequentially in the same tubular PECVD equipment, effectively reducing the process time. In summary, the present invention can effectively form an insulating dielectric film on the four sides of the edge of the silicon wafer through a special "direct oxidation-indirect deposition" process, and even if there is a coating around the edge, there will be no obvious negative impact.

[0010] S4. Remove the silicon oxide layer on the back of the silicon wafer.

[0011] During the S3 high-temperature deposition process, a partial silicon oxide layer will inevitably be produced on the back of the silicon wafer, so the back silicon oxide layer needs to be removed.

[0012] S5. Depositing a tunneling oxide layer and an intrinsic polysilicon layer in sequence on the back side of the silicon wafer.

[0013] While the tunneling oxide layer and the intrinsic polysilicon layer are deposited in sequence on the back of the silicon wafer, a wrap-around layer (i.e., the tunneling oxide layer and the intrinsic polysilicon layer located at the edge of the silicon wafer) will inevitably be produced on the front and edge areas of the silicon wafer.

[0014] S6. Two-step through-source boron diffusion is performed to convert the inner layer and the outer layer of the intrinsic polysilicon layer into a boron diffusion layer and a BSG layer respectively, and the insulating dielectric film is densified at high temperature and doping of boron atoms is achieved.

[0015] In the above two-step boron diffusion process, in addition to converting the inner and outer layers of the intrinsic polysilicon layer into a boron diffusion layer and a BSG layer respectively, the insulating dielectric film is also annealed and doped with boron at the same time. The effects are as follows: (1) The intrinsic silicon oxide film (i.e., the second silicon oxide layer) deposited by PECVD in S3 has a high porosity, which will reduce the effective density of the material and thus reduce the dielectric constant (reduced insulation); high-temperature annealing can reduce the porosity in the intrinsic silicon oxide film, making the film denser, thereby increasing the dielectric constant; (2) The introduction of boron atoms will change the microstructure and charge distribution of the insulating dielectric film, thereby affecting its dielectric properties; specifically: (a) Regarding charge distribution: the presence of boron atoms in the insulating dielectric film will introduce additional charges, which will respond to the electric field, thereby increasing the polarization ability of the material and increasing the dielectric constant; (b) Regarding microstructure: the introduction of boron atoms will change the microstructure of the insulating medium and increase the inhomogeneity of the material, which will also increase its dielectric constant.

[0016] S7. Laser one-time patterning and grooving to remove the BSG layer in the phosphorus diffusion area and isolation area design area.

[0017] Removing the BSG layer on the surface of the phosphorus diffusion area and the isolation area design area can pave the way for subsequent alkaline cleaning.

[0018] S8, alkaline cleaning. During the alkaline cleaning process, since the BSG layer on the surface of the slotted area in S7 is removed, the deposited layers at the bottom thereof will be corroded and removed by the alkaline solution, exposing the silicon wafer substrate; and since the surface of the non-slotted area is protected by the BSG layer, the deposited layers at the bottom thereof are retained.

[0019] S9, secondary deposition of a tunnel oxide layer and an intrinsic polysilicon layer on the back side.

[0020] While the tunnel oxide layer and the intrinsic polysilicon layer are deposited on the back of the silicon wafer for the second time, a wrap-around layer will inevitably be produced again on the front and edge areas of the silicon wafer.

[0021] S10. Phosphorus diffusion, so that the inner layer and the outer layer of the intrinsic polysilicon layer are converted into a phosphorus diffusion layer and a PSG layer respectively.

[0022] S11, back-side laser secondary patterning and grooving to remove the PSG layer in the boron diffusion area and isolation area design area.

[0023] Removing the PSG layer on the surface of the boron diffusion area and the isolation area design area can pave the way for subsequent cleaning and texturing.

[0024] S12, de-coating: Use a chain machine to acid polish the silicon wafer to remove the coating on the front and edge of the silicon wafer. However, since the roller of the chain machine is difficult to keep horizontal during long-term use, the silicon wafer shakes up and down during the acid polishing process. The coating on the front side can be basically removed, but the coating on the edge of the silicon wafer cannot be effectively removed. Therefore, there is a partial coating area on the edge of the battery.

[0025] S13, cleaning and texturing: put the silicon wafers that have been stripped of the plating into the alkaline texturing tank for wet cleaning and integrated texturing. Since the plating layer on the front of the silicon wafer has been stripped and there is no oxidation area, a pyramid velvet surface can be formed during the texturing process (the part of the plating layer on the edge of the silicon wafer that has been completely removed will also generate a pyramid velvet surface); for the phosphorus diffusion layer on the back of the silicon wafer, since the surface is protected by the PSG layer, its bottom deposition layer can be retained. For the isolation area design area on the back of the silicon wafer, since the surface PSG layer has been removed, the alkaline solution can effectively corrode the bottom deposition layer, making the silicon wafer substrate lose protection, forming an isolation area and generating a pyramid velvet surface; for the boron diffusion layer, since its surface PSG layer has also been removed, the phosphorus diffusion layer and tunneling oxide layer at its bottom will be corroded and removed by the alkaline solution until the bottom BSG layer is exposed. The BSG layer will block the erosion of the alkaline solution and protect its bottom deposition layer. The subsequent acid (HF / HCl) cleaning tank of the texturing tank can further remove the residual PSG layer and BSG layer on the back of the silicon wafer.

[0026] S14, double-sided coating.

[0027] S15, screen printing, sintering, light injection, to produce a TBC solar cell with an edge-wrap coating.

[0028] Preferably, in S2, the number of silicon wafers stacked each time is 100 to 300, and after stacking, the front and back sides of adjacent silicon wafers are attached to each other, and the four edge sides are flush.

[0029] Preferably, in S3, insulating dielectric films are sequentially constructed on four edge sides of the stacked silicon wafers.

[0030] Preferably, in S3, the thickness of the first silicon oxide layer is 5-30 nm; the thickness of the second silicon oxide layer is 10-200 nm.

[0031] Preferably, in S3, the direct oxidation comprises: introducing N2O to oxidize the shallow surface of the edge of the silicon wafer into a first silicon oxide layer.

[0032] Further preferably, the conditions for the direct oxidation are: N2O flow rate 100-500 sccm, RF power 1000-10000 W, pressure 10-200 Torr, temperature 300-500°C, and time 5-30 min.

[0033] Preferably, in S3, the indirect deposition includes: introducing SiH4 and N2O to deposit a second silicon oxide layer on the surface of the first oxide layer.

[0034] Further preferably, the conditions for the indirect deposition are: flow ratio of SiH4 and N2O = 1:5~1:10, RF power 1000~10000 W, pressure 100~500 Torr, temperature 300~500°C, time 10~80 min.

[0035] Preferably, in S4, a chain machine is used to acid-etch and remove the silicon oxide layer on the back of the silicon wafer, with a 20-60 wt% HF aqueous solution as the etching solution and a belt speed of 1-10 m / min.

[0036] Preferably, in S5 and S9, the deposition conditions of the tunnel oxide layer are: O2 flow rate 10000~80000 sccm, reaction temperature 400~800℃, time 200~1000 s, and tunnel oxide layer thickness 2~10 nm; the deposition conditions of the intrinsic polysilicon layer are: SiH4 flow rate 300~2000 sccm, reaction temperature 500~700℃, time 2~4 h, working gas pressure 100~500mTorr, and intrinsic polysilicon layer thickness 100~300 nm.

[0037] Preferably, in S6, the conditions for the two-step source diffusion of boron are: one-step source: introducing a mixed gas of BCl3 and O2, temperature 800~950℃, diffusion time 5~50 min, BCl3 gas flow rate 50~500 sccm, O2 flow rate 500~2000 sccm; oxidation advancement: temperature 900~1050℃, advancement time 30~80 min, O2 flow rate 5000~30000 sccm; two-step source: introducing a mixed gas of BCl3 and O2, temperature 800~950℃, diffusion time 2~30 min, BCl3 flow rate 20~100 sccm, O2 flow rate 200~1000 sccm.

[0038] Since the concentration of boron atoms in the conventional one-step boron diffusion process is relatively low, the concentration of boron atoms introduced into the insulating dielectric film in this process is relatively low. In order to increase the boron atom concentration of the edge insulating dielectric film, the present invention deliberately adds a post-source process (i.e., the last step of the re-source process) on the basis of conventional boron diffusion, aiming to increase the boron atom concentration of the insulating dielectric film and improve the dielectric constant of this layer; at the same time, since there is a BSG layer blocking the back boron diffusion surface, the post-source will not affect the initial performance of the back boron diffusion layer.

[0039] Preferably, in S10, the phosphorus diffusion conditions are: temperature 750~850°C, diffusion time 5~30 min, POCl3 is carried by nitrogen with a flow rate of 500~1200 sccm, O2 flow rate 500~1000 sccm, oxidation advancement temperature 850~950°C, O2 flow rate 1000~10000 sccm, and advancement time 20~60 min.

[0040] Compared with the prior art, the beneficial effects of the present invention are: (1) The present invention pre-deposits an insulating dielectric film on the edge of the silicon wafer to insulate the edge plating area from the silicon wafer substrate. Therefore, even if there is a plating layer on the edge of the finished TBC solar cell, no significant leakage will occur in the plating part.

[0041] (2) The insulating dielectric film formed by the special "direct oxidation-indirect deposition" + "high temperature densification + boron doping" combined process of the present invention has high density and high dielectric constant, so it has excellent insulation performance and can effectively isolate the edge winding coating from the silicon wafer substrate.

[0042] (3) The silicon oxide dielectric film of the present invention also has an excellent passivation effect, which can further passivate the side area of ​​the silicon wafer, thereby improving the electrical performance of the battery.

[0043] (4) Compared with the conventional TBC solar cells with pyramid velvet edges, the silicon wafers of the present invention have a pyramid velvet edge in part and a polished surface in part. Silicon wafers with velvet edges are more likely to cause silicon wafer fragments under the action of external forces, while polished surfaces are more helpful in improving the yield of solar cells. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] Figure 1 Schematic diagram of the structure of the silicon wafer after double-sided polishing.

[0045] Figure 2 Schematic diagram of the structure after the insulating layer is deposited on the side of the silicon wafer.

[0046] Figure 3 This is a schematic diagram of the structure after the first tunneling oxide layer and the first intrinsic polysilicon layer are deposited on the silicon wafer at one time.

[0047] Figure 4 Schematic diagram of the structure after boron diffusion of silicon wafer.

[0048] Figure 5 This is a schematic diagram of the structure after the BSG layer of the silicon wafer is patterned and grooved by laser once and cleaned.

[0049] Figure 6 This is a schematic diagram of the structure after the second tunneling oxide layer and the second intrinsic polysilicon layer are deposited on the silicon wafer for the second time.

[0050] Figure 7 Schematic diagram of the structure of the silicon wafer after phosphorus diffusion.

[0051] Figure 8 This is a schematic diagram of the structure of the silicon wafer after chain de-coating.

[0052] Fig. 9 This is a schematic diagram of the structure of the silicon wafer after laser secondary patterning of the PSG layer + cleaning and texturing (the thickness of the pyramid velvet surface at the edge of the silicon wafer is relatively thin, so it is not shown in the figure).

[0053] Fig.10 This is a schematic diagram of the structure of a finished TBC solar cell (the pyramid velvet surface at the edge of the silicon wafer is relatively thin and is not shown in the figure).

[0054] The reference numerals in the figure are: N-type single crystal silicon wafer 1; insulating dielectric film 2; first tunneling oxide layer 3; first intrinsic polysilicon layer 4; boron diffusion layer 5; BSG layer 6; second tunneling oxide layer 7; second intrinsic polysilicon layer 8; phosphorus diffusion layer 9; PSG layer 10; pyramid velvet surface 11; passivation anti-reflection layer 12; electrode layer 13. DETAILED DESCRIPTION

[0055] The present invention will be further described below in conjunction with the embodiments.

[0056] A method for preparing a TBC solar cell with an edge wrap coating comprises the following steps: S1. Polishing both sides of the N-type silicon wafer.

[0057] In some preferred implementation cases, the N-type single crystal silicon wafer 1 is immersed in an alkali polishing tank containing alkali solution, and double-sided polishing is performed at 75-85° C. for 6-8 min, the polishing thickness is 3-7 μm, and the thinning amount is 0.35-0.45 g. Figure 1 shown.

[0058] S2. Stack several silicon wafers in layers to form a cubic silicon wafer combination.

[0059] In some preferred implementation cases, silicon wafers are stacked in "layers" with 100 to 300 wafers as a group. After stacking, the front and back sides of adjacent silicon wafers are attached to each other, and the four edge sides are flush with the sides facing upward, in preparation for the subsequent deposition of insulating dielectric films on the four edges of the silicon wafers.

[0060] S3, sequentially forming a first silicon oxide layer and a second silicon oxide layer on the four edges of the silicon wafer assembly by direct oxidation and indirect deposition, and the two layers are combined to form an insulating dielectric film 2, such as Figure 2 shown.

[0061] In some preferred implementation cases, in S3, the thickness of the first silicon oxide layer is 5-30 nm; the thickness of the second silicon oxide layer is 10-200 nm.

[0062] In some preferred implementation cases, in S3, the direct oxidation includes: introducing N2O to oxidize the shallow surface of the edge of the silicon wafer into a first silicon oxide layer. Further preferably, the conditions of the direct oxidation are: N2O flow rate 100-500 sccm, RF power 1000-10000 W, pressure 10-200 Torr, temperature 300-500°C, time 5-30 min.

[0063] In some preferred implementation cases, in S3, the indirect deposition includes: introducing SiH4 and N2O to deposit a second silicon oxide layer on the surface of the first oxide layer. Further preferably, the indirect deposition conditions are: flow ratio of SiH4 and N2O = 1:5~1:10, RF power 1000~10000 W, pressure 100~500 Torr, temperature 300~500°C, time 10~80 min. S4, removing the silicon oxide layer on the back of the silicon wafer.

[0064] In some preferred implementation cases, a chain machine is used to acid-etch and remove the silicon oxide layer on the back of the silicon wafer, using a 20-60 wt % HF aqueous solution as the etching solution, and a belt speed of 1-10 m / min.

[0065] S5. Depositing a tunneling oxide layer and an intrinsic polysilicon layer in sequence on the back side of the silicon wafer.

[0066] In some preferred implementation cases, the first tunneling oxide layer 3 is deposited once on the back of the silicon wafer using LPCVD, wherein the gas flow rate of O2 is 10000~80000 sccm, the reaction temperature is 400~800℃, the time is 200~1000 s, and the thickness of the first tunneling oxide layer is 2~10 nm. Then, the first intrinsic polysilicon layer 4 is deposited on the first tunneling oxide layer, the gas flow rate of SiH4 is 300~2000 sccm, the reaction temperature is 500~700℃, the time is 2~4 h, the working gas pressure is 100~500 mTorr, and the thickness of the first intrinsic polysilicon layer is 100~300 nm. Because tubular vacuum equipment is used, it is inevitable that a wrap-around coating will be generated on the front / back and edge areas of the silicon wafer (i.e., the first tunneling oxide layer 3 and the first intrinsic polysilicon layer 4 located at the edge of the silicon wafer), and its structural schematic diagram is shown as follows. Figure 3 shown.

[0067] S6, two-step source boron diffusion, so that the inner layer and outer layer of the first intrinsic polysilicon layer are converted into a boron diffusion layer 5 and a BSG layer 6 respectively, and at the same time, the insulating dielectric film is densified and doped with boron. The schematic diagram of the silicon wafer structure is shown in FIG. Figure 4 shown.

[0068] In some preferred implementation cases, the two-step source boron diffusion conditions are: first, a mixed gas of BCl3 and O2 is introduced at a temperature of 800~950°C, a diffusion time of 5~50 min, a BCl3 gas flow rate of 50~500 sccm, and an O2 flow rate of 500~2000 sccm; then, O2 is introduced for oxidation advancement at a temperature of 900~1050°C, a advancement time of 30~80 min, and an O2 flow rate of 5000~30000 sccm; finally, a mixed gas of BCl3 and O2 is introduced at a temperature of 800~950°C, a diffusion time of 2~30 min, a BCl3 flow rate of 20~100 sccm, and an O2 flow rate of 200~1000 sccm, to generate a BSG layer with a thickness of 30~70 nm.

[0069] S7. Laser one-time patterning and grooving to remove the BSG layer in the phosphorus diffusion area and isolation area design area.

[0070] In some preferred implementation cases, a picosecond laser is used to pattern the BSG layer, and the laser wavelength used is 200-600 nm, the frequency is 400-800 KHz, the marking speed is 40000-60000 mm / s, the power is 10-50 W, and the processing time is 1-20 s.

[0071] S8, alkali cleaning. In the alkali cleaning process, since the BSG layer on the surface of the slotted area in S7 is removed, the deposited layers at the bottom will be corroded and removed by the alkali solution, exposing the silicon wafer base; and since the surface of the non-slotted area is protected by the BSG layer 6, the deposited layers at the bottom are retained. The schematic diagram of the silicon wafer structure is shown in FIG. Figure 5 shown.

[0072] In some preferred implementation cases, the silicon wafer after laser primary patterning and grooving is placed in an alkaline solution for cleaning, with an alkali concentration of 1.5-2.5 wt%, a temperature of 70-85° C., a time of 100-400 s, and an etching depth of 1-5 μm.

[0073] S9, secondary deposition of a tunnel oxide layer and an intrinsic polysilicon layer on the back side.

[0074] In some preferred implementation cases, the second tunnel oxide layer 7 is grown on the back surface of the silicon wafer by LPCVD, the gas flow rate of O2 is 10000~80000 sccm, the temperature is 400~800℃, the time is 200~1000 s, and the thickness of the grown second tunnel oxide layer is 2~10 nm; then the second intrinsic polysilicon layer 8 is grown again on the basis of the second tunnel oxide layer, wherein the gas flow rate of SiH4 is 300~2000 sccm, the reaction temperature is 500~700℃, the time is 2~4 h, the working pressure is 100~500 mTorr, and the thickness of the second intrinsic polysilicon layer is 100~300 nm. When using tubular vacuum equipment, it is inevitable to produce a wrap-around coating on the front / back and edge areas of the silicon wafer, and its structural schematic diagram is shown as follows Figure 6 shown.

[0075] S10, phosphorus diffusion, so that the inner layer and the outer layer of the second intrinsic polysilicon layer are converted into a phosphorus diffusion layer 9 and a PSG layer 10 respectively. The schematic diagram of the silicon wafer structure is shown in FIG. Figure 7 shown.

[0076] In some preferred implementation cases, the phosphorus diffusion conditions are: phosphorus diffusion temperature 750~850℃, diffusion time 5~30 min, POCl3 is carried by nitrogen with a flow rate of 500~1200 sccm, O2 flow rate is 500~1000 sccm, oxidation advancement temperature 850~950℃, O2 flow rate is 1000~10000 sccm, advancement time is 20~60 min, and PSG layer thickness is 30~70 nm.

[0077] S11, back-side laser secondary patterning and grooving to remove the PSG layer in the boron diffusion area and isolation area design area.

[0078] In some preferred implementation cases, the conditions for laser secondary patterning grooving are: laser wavelength of 200-600 nm, frequency of 400-800 KHz, marking speed of 40000-60000 mm / s, power of 10-50 W, and processing time of 1-20 s.

[0079] S12, De-coating: Use a chain machine to acid polish the silicon wafer to remove the coating on the front and edge of the silicon wafer. However, since the roller of the chain machine is difficult to keep horizontal during long-term use, the silicon wafer shakes up and down during the acid polishing process. The coating on the front side can be basically removed, but the coating on the edge of the silicon wafer cannot be effectively removed. Therefore, there is a partial coating area on the edge of the battery, such as Figure 8 shown.

[0080] In some preferred implementation cases, the chain machine acid polishing process conditions are: the volume ratio of hydrofluoric acid solution and nitric acid solution in the acid tank is 1:1~1:10 (the concentration of hydrofluoric acid solution is 49 wt%, and the concentration of nitric acid solution is 69 wt%), and the belt speed is 1~10m / min.

[0081] S13, cleaning and texturing: The silicon wafers that have been stripped of the wrapping coating are placed in an alkaline texturing tank for wet cleaning and integrated texturing treatment. Since the wrapping coating on the front of the silicon wafer has been stripped and there is no oxidized area, a pyramid velvet surface 11 can be formed during the texturing process (the part of the silicon wafer edge where the wrapping coating is completely removed will also generate a pyramid velvet surface); for the phosphorus diffusion layer on the back of the silicon wafer, since the surface is protected by the PSG layer, its bottom deposition layer can be retained. For the isolation area design area on the back of the silicon wafer, since the surface PSG layer has been removed, the alkaline solution can effectively corrode the bottom deposition layer, causing the silicon wafer substrate to lose protection, forming an isolation area and generating a pyramid velvet surface 11; for the boron diffusion layer, since the surface PSG layer has also been removed, the phosphorus diffusion layer and tunneling oxide layer at the bottom will be corroded and removed by the alkaline solution until the bottom BSG layer is exposed. The BSG layer will block the erosion of the alkaline solution and protect its bottom deposition layer. Subsequently, the subsequent acid (HF / HCl) cleaning tank of the texturing tank can further remove the PSG layer and BSG layer remaining on the back of the silicon wafer. The schematic diagram of the silicon wafer structure is shown in the figure. Fig. 9 shown.

[0082] In some preferred implementation cases, the concentration of KOH solution in the alkaline texturing tank is 1.5-2.2 wt%, the temperature is maintained at 75-85°C, the time is 6-12 min, and the weight loss is 0.30-0.50 g.

[0083] S14, double-sided coating to form a passivation anti-reflection layer 12 on the front and back sides of the silicon wafer.

[0084] In some preferred implementation cases, AlO is deposited on both sides of the processed silicon wafer by ALD deposition. x The layer is generated by the reaction of Al(CH3)3 and water vapor, with a thickness of 5~10 nm and a process temperature of 200~300℃. Then, SiN is deposited on both sides of the silicon wafer using a tubular PECVD device. x layer with a thickness of 80~120 nm and a refractive index of 1.9~2.2; the reaction gases in the tubular cavity are SiH4 and NH3, the working pressure is 1000~2000 mTorr, the power is 10000~20000 W, the temperature is 400~600℃, the SiH4 gas flow rate is 500~2000 sccm, the NH3 gas flow rate is 5000~10000 sccm, and the deposition time is 5~20 min.

[0085] S15, screen printing, sintering, light injection, to produce a TBC solar cell with an edge-wrap coating.

[0086] In some preferred implementation cases, the coated silicon wafer is screen-printed on the back to form a metal contact, and then sintered at 700-800°C to form an Ag-Si ohmic contact (i.e., electrode layer 13), and finally repaired by light injection to obtain a finished TBC solar cell, the structural schematic diagram of which is shown in FIG. Fig.10 shown.

[0087] Specific examples and comparative examples.

[0088] Example 1 A method for preparing a TBC solar cell with an edge wrap coating comprises the following steps: S1. Immerse the diamond wire-cut N-type single crystal silicon wafer 1 in an alkali polishing tank containing alkali solution, and polish both sides at 75°C for 6 minutes. The polishing thickness is 4 μm, and the thinning amount is 0.42 g. Figure 1 shown.

[0089] S2. Stack the silicon wafers in layers into a cubic silicon wafer combination, with 200 wafers as a group. After stacking, the front and back sides of adjacent silicon wafers are attached to each other, and the four edge sides are flush with the sides facing upwards, in preparation for the subsequent deposition of an insulating layer on the four edges of the silicon wafer.

[0090] S3, the stacked silicon wafers are placed sideways upwards, and the PECVD process is used. The specific process is: the first silicon oxide layer and the second silicon oxide layer are formed on the four edges of the silicon wafer combination by direct oxidation and indirect deposition in sequence, and the two layers are combined to form an insulating dielectric film 2. The structural diagram is shown in FIG. Figure 2 As shown. The direct oxidation conditions are: N2O flow rate 300sccm, RF power 3000 W, pressure 120 Torr, temperature 450℃, time 20 min, and the thickness of the first silicon oxide layer is about 12 nm. The indirect deposition conditions are: SiH4 and N2O flow ratio = 1:7, RF power 7800 W, pressure 230 Torr, temperature 470℃, time 50 min, and the thickness of the second silicon oxide layer is about 180 nm.

[0091] S4. Use a chain machine to acid-etch and remove the silicon oxide layer on the back of the silicon wafer, using a 40 wt% HF aqueous solution as the etching solution and a belt speed of 1.6 m / min.

[0092] S5. The first tunnel oxide layer 3 is deposited once on the back of the silicon wafer using LPCVD, wherein the gas flow rate of O2 is 40,000 sccm, the reaction temperature is 600°C, the time is 600 s, and the thickness of the first tunnel oxide layer is about 3 nm. Next, the first intrinsic polysilicon layer 4 is deposited on the first tunnel oxide layer, wherein the gas flow rate of SiH4 is 920 sccm, the reaction temperature is 550°C, the time is 3.3 h, the working gas pressure is 300 mTorr, and the thickness of the first intrinsic polysilicon layer is about 290 nm. When a tubular vacuum device is used, it is inevitable that a wrap-around layer will be generated on the front / back and edge areas of the silicon wafer (i.e., the first tunnel oxide layer 3 and the first intrinsic polysilicon layer 4 located at the edge of the silicon wafer). The schematic diagram of the structure is shown in the figure below. Figure 3 shown.

[0093] S6, two-step source boron diffusion, so that the inner layer and the outer layer of the first intrinsic polysilicon layer are converted into a boron diffusion layer 5 and a BSG layer 6 respectively, and at the same time, the insulating dielectric film is densified and doped with boron. The schematic diagram of the silicon wafer structure is shown in FIG. Figure 4 Specifically, the two-step source boron diffusion conditions are: first, a mixed gas of BCl3 and O2 is introduced, the temperature is 850℃, the diffusion time is 10 min, the BCl3 gas flow rate is 200 sccm, and the O2 flow rate is 1200 sccm; then O2 is introduced for oxidation advancement, the temperature is 950℃, the advancement time is 30 min, and the O2 flow rate is 7000 sccm. Finally, a mixed gas of BCl3 and O2 is introduced, the temperature is 860℃, the diffusion time is 25min, the BCl3 flow rate is 70 sccm, and the O2 flow rate is 500 sccm, to generate a BSG layer with a thickness of about 45 nm.

[0094] S7. Use picosecond laser to pattern and groove to remove the BSG layer in the phosphorus diffusion area and isolation area design area. The laser wavelength used is 532 nm, the frequency is 600 KHz, the marking speed is 45000 mm / s, the power is 50 W, and the processing time is 3s.

[0095] S8, the silicon wafer after laser patterning is placed in an alkaline solution for cleaning, the alkaline concentration is 2.0 wt%, and the temperature is 75°C. During the alkaline cleaning process, since the BSG layer on the surface of the grooved area in S7 is removed, the deposited layers at the bottom will be corroded and removed by the alkaline solution, exposing the silicon wafer base; and since the surface of the non-grooved area is protected by the BSG layer 6, the deposited layers at the bottom are retained. The schematic diagram of the silicon wafer structure is shown in FIG. Figure 5 shown.

[0096] S9. A second tunnel oxide layer 7 is grown on the back surface of the silicon wafer by LPCVD. The gas flow rate of O2 is 30,000 sccm, the temperature is 600°C, and the time is 450 s. The thickness of the grown second tunnel oxide layer is about 2.5 nm. Then, a second intrinsic polysilicon layer 8 is grown again on the basis of the second tunnel oxide layer. The gas flow rate of SiH4 is 920 sccm, the reaction temperature is 550°C, the time is 1.5 h, the working pressure is 300 mTorr, and the thickness of the second intrinsic polysilicon layer is about 180 nm. When using a tubular vacuum device, it is inevitable that a wrap-around coating will be generated on the front / back and edge areas of the silicon wafer. The schematic diagram of its structure is shown in the figure below. Figure 6 shown.

[0097] S10, phosphorus diffusion, so that the inner layer and the outer layer of the second intrinsic polysilicon layer are converted into a phosphorus diffusion layer 9 and a PSG layer 10 respectively. The schematic diagram of the silicon wafer structure is shown in FIG. Figure 7 Specifically, the phosphorus diffusion conditions are as follows: phosphorus diffusion temperature 790°C, diffusion time 15 min, POCl3 carried by nitrogen with a flow rate of 1000 sccm, O2 flow rate 650 sccm, oxidation advancement temperature 890°C, O2 flow rate 3000 sccm, advancement time 20 min, and PSG layer thickness of about 39 nm.

[0098] S11. Picosecond laser secondary patterning and grooving is used on the back of the silicon wafer to remove the PSG layer in the boron diffusion area and the isolation area design area. Specifically, the conditions of laser secondary patterning and grooving are: laser wavelength of 532 nm, frequency of 600 KHz, marking speed of 45000 mm / s, power of 25 W, and processing time of 2.7 s.

[0099] S12, Remove wrap-around plating: Use a chain machine to acid polish the silicon wafer to remove the wrap-around plating layer on the front and edge of the silicon wafer. The process conditions of the chain machine acid polishing are: the volume ratio of hydrofluoric acid solution and nitric acid solution in the acid tank is 1:4 (the concentration of hydrofluoric acid solution is 49 wt%, and the concentration of nitric acid solution is 69 wt%), and the belt speed is 1.3 m / min. However, since it is difficult for the roller of the chain machine to remain horizontal during long-term use, the silicon wafer will shake up and down during the acid polishing process. The wrap-around plating part on the front side can be basically removed, but the wrap-around plating on the edge of the silicon wafer cannot be effectively removed. As a result, there are some wrap-around plating areas on the edge of the battery, such as Figure 8 shown.

[0100] S13, cleaning and texturing: the silicon wafer after the de-plating is placed in an alkaline texturing tank for wet cleaning and integrated texturing. The concentration of KOH solution in the alkaline texturing tank is 1.7 wt%, the temperature is maintained at 82°C, and the time is 7 min. Since the de-plating layer on the front of the silicon wafer has been completely removed and there is no oxidation area, a pyramid velvet surface 11 can be formed during the texturing process (the part of the de-plating layer on the edge of the silicon wafer will also generate a pyramid velvet surface); for the phosphorus diffusion layer on the back of the silicon wafer, since the surface is protected by the PSG layer, its bottom deposition layer is retained. For the isolation area design area on the back of the silicon wafer, since the surface PSG layer has been removed, the alkali solution can effectively corrode the bottom deposition layer, so that the silicon wafer substrate loses protection, forming an isolation area and generating a pyramid velvet surface 11; for the boron diffusion layer, since its surface PSG layer is also removed, the phosphorus diffusion layer and tunneling oxide layer at its bottom will be corroded and removed by the alkali solution until the bottom BSG layer is exposed. The BSG layer will block the erosion of the alkali solution and protect its bottom deposition layer. The subsequent acid (HF / HCl) cleaning tank of the texturing tank can further remove the PSG layer and BSG layer remaining on the back of the silicon wafer. The schematic diagram of the silicon wafer structure is shown in Fig. 9 shown.

[0101] S14, depositing a passivation anti-reflection layer 12 on both sides of the processed silicon wafer by ALD deposition, wherein the passivation anti-reflection layer comprises AlO x Layer and SiN x Layer. Among them, AlO x The layer is generated by the reaction of Al(CH3)3 and water vapor, with a thickness of about 8 nm and a process temperature of 250°C. Subsequently, SiN is deposited on both sides of the silicon wafer using a tubular PECVD device. x layer with a thickness of about 82 nm and a refractive index of about 2.0; the reaction gases in the tubular cavity are SiH4 and NH3, the working pressure is 1600 mTorr, the power is 12000 W, the temperature is 440℃, the SiH4 gas flow rate is 980 sccm, the NH3 gas flow rate is 8000 sccm, and the deposition time is 10 min.

[0102] S15, the coated silicon wafer is screen-printed on the back to form a metal contact, and then sintered at 770°C to form an Ag-Si ohmic contact (i.e., electrode layer 13), and finally repaired by light injection to obtain a TBC solar cell with a wire around the edge of the coating. The schematic diagram of its structure is shown in FIG. Fig.10 shown.

[0103] Example 2 The difference between Example 2 and Example 1 is that in S4 (the rest of the steps are the same), the oxide layer plated on the back of the silicon wafer is removed by laser treatment + alkali cleaning. The specific conditions are: S4. The oxide layer on the back of the silicon wafer was processed by laser grooving, wherein the laser conditions were: picosecond laser, laser wavelength 532 nm, frequency 600 KHz, marking speed 45000 mm / s, power 50 W, and processing time 3 s. The processed silicon wafer was then cleaned with alkali to remove the oxide layer on the back of the silicon wafer, and the alkali cleaning conditions were: alkali concentration 2.0 wt%, temperature 75°C.

[0104] Comparative Example 1 The main difference between Comparative Example 1 and Example 1 is that no insulating dielectric film is pre-constructed on the edge of the silicon wafer, that is, S2-S4 is not included.

[0105] S1. Immerse the diamond wire-cut N-type single crystal silicon wafer in an alkaline polishing tank containing alkaline solution, and polish both sides at 75°C for 6 minutes. The polishing thickness is 4 μm and the thinning amount is 0.42 g.

[0106] S2. The first tunnel oxide layer was deposited on the back of the silicon wafer by LPCVD, wherein the gas flow rate of O2 was 40000 sccm, the reaction temperature was 600℃, the time was 600 s, and the thickness of the first tunnel oxide layer was about 3 nm. Then, the first intrinsic polysilicon layer was deposited on the first tunnel oxide layer, wherein the gas flow rate of SiH4 was 920 sccm, the reaction temperature was 550℃, the time was 3.3 h, the working pressure was 300 mTorr, and the thickness of the first intrinsic polysilicon layer was about 290 nm.

[0107] S3, boron diffusion, so that the inner layer and outer layer of the first intrinsic polysilicon layer are converted into a boron diffusion layer and a BSG layer respectively. Specifically, the boron diffusion conditions are: firstly, a mixed gas of BCl3 and O2 is introduced, the temperature is 850℃, the diffusion time is 10 min, the BCl3 gas flow rate is 200 sccm, and the O2 flow rate is 1200 sccm; then, O2 is introduced for oxidation advancement, the temperature is 950℃, the advancement time is 30 min, and the O2 flow rate is 7000 sccm, generating a BSG layer with a thickness of about 45 nm.

[0108] S4. Use picosecond laser to pattern and groove to remove the BSG layer in the phosphorus diffusion area and isolation area design area. The laser wavelength used is 532 nm, the frequency is 600 KHz, the marking speed is 45000 mm / s, the power is 50 W, and the processing time is 3s.

[0109] S5. The silicon wafer after laser patterning is placed in an alkaline solution for cleaning, with an alkaline concentration of 2.0 wt% and a temperature of 75°C. During the alkaline cleaning process, since the BSG layer on the surface of the S4 slotted area is removed, the deposited layers at the bottom will be corroded and removed by the alkaline solution, exposing the silicon wafer substrate; and since the surface of the non-slotted area is protected by the BSG layer, the deposited layers at the bottom are retained.

[0110] S6. A second tunneling oxide layer is grown on the back surface of the silicon wafer by LPCVD, with an O2 gas flow rate of 30,000 sccm, a temperature of 600°C, and a time of 450 s. The thickness of the grown second tunneling oxide layer is about 2.5 nm. Then, a second intrinsic polysilicon layer is grown again on the basis of the second tunneling oxide layer, with an SiH4 gas flow rate of 920 sccm, a reaction temperature of 550°C, a time of 1.5 h, a working gas pressure of 300 mTorr, and a thickness of the second intrinsic polysilicon layer of about 180 nm.

[0111] S7, phosphorus diffusion, so that the inner layer and outer layer of the second intrinsic polysilicon layer are converted into a phosphorus diffusion layer and a PSG layer respectively. Specifically, the phosphorus diffusion conditions are: phosphorus diffusion temperature 790 ° C, diffusion time 15 min, POCl3 is carried by nitrogen with a flow rate of 1000 sccm, O2 flow rate 650 sccm, oxidation advancement temperature 890 ° C, O2 flow rate 3000 sccm, advancement time 20 min, PSG layer thickness is about 39 nm.

[0112] S8. Picosecond laser secondary patterning and grooving is used on the back of the silicon wafer to remove the PSG layer in the boron diffusion area and the isolation area design area. Specifically, the conditions for laser secondary patterning and grooving are: laser wavelength of 532 nm, frequency of 600 KHz, marking speed of 45000 mm / s, power of 25 W, and processing time of 2.7 s.

[0113] S9, De-coating: Use chain machine acid polishing to remove the coating on the front and edge of the silicon wafer. The chain machine acid polishing process conditions are: the volume ratio of hydrofluoric acid solution and nitric acid solution in the acid tank is 1:4 (the concentration of hydrofluoric acid solution is 49 wt%, and the concentration of nitric acid solution is 69 wt%), and the belt speed is 1.3 m / min.

[0114] S10, cleaning and texturing: put the silicon wafer that has been stripped of the winding plating into the alkaline texturing tank for wet cleaning and integrated texturing treatment. Among them, the concentration of KOH solution in the alkaline texturing tank is 1.7 wt%, the temperature is maintained at 82℃, and the time is 7 min. Since the front side of the silicon wafer has been stripped of the winding plating layer and there is no oxidation area, a pyramid velvet surface can be formed during the texturing process. For the phosphorus diffusion layer on the back side of the silicon wafer, since the surface is protected by the PSG layer, its bottom deposition layer can be retained. For the isolation area design area on the back side of the silicon wafer, since the surface PSG layer has been removed, the alkaline solution can effectively corrode the bottom deposition layer, so that the silicon wafer substrate loses protection, forming an isolation area and generating a pyramid velvet surface; for the boron diffusion layer, since its surface PSG layer is also removed, the phosphorus diffusion layer and tunneling oxide layer at its bottom will be corroded and removed by the alkaline solution until the bottom BSG layer is exposed. The BSG layer will block the erosion of the alkaline solution and protect its bottom deposition layer. Then the subsequent acid (HF / HCl) cleaning tank of the texturing tank body can further remove the residual PSG layer and BSG layer on the back side of the silicon wafer.

[0115] S11, depositing a passivation anti-reflection layer on both sides of the processed silicon wafer by ALD deposition, wherein the passivation anti-reflection layer comprises AlO x Layer and SiN x Layer. Among them, AlO x The layer is generated by the reaction of Al(CH3)3 and water vapor, with a thickness of about 8 nm and a process temperature of 250°C. Subsequently, SiN is deposited on both sides of the silicon wafer using a tubular PECVD device. x layer with a thickness of about 82 nm and a refractive index of about 2.0; the reaction gases in the tubular cavity are SiH4 and NH3, the working pressure is 1600 mTorr, the power is 12000 W, the temperature is 440℃, the SiH4 gas flow rate is 980 sccm, the NH3 gas flow rate is 8000 sccm, and the deposition time is 10 min.

[0116] S12, screen printing the coated silicon wafer on the back to form a metal contact, then sintering at 770°C to form an Ag-Si ohmic contact, and finally light injection repair to obtain a TBC solar cell.

[0117] Comparative Example 2 The main difference between Comparative Example 2 and Example 1 is that only the first silicon oxide layer is formed in S3, that is, the second silicon oxide is not indirectly deposited. The specific conditions are: S3. Place the stacked silicon wafer side up and use PECVD process to oxidize a layer of insulating dielectric film on the side of the silicon wafer. The direct oxidation conditions are: N2O flow rate 300 sccm, RF power 3000 W, pressure 120 Torr, temperature 450℃, time 20 min, and the thickness of the first silicon oxide layer is about 12 nm.

[0118] Comparative Example 3 The main difference between Comparative Example 3 and Example 1 is that no additional source is performed during the boron diffusion process of S6. The specific conditions are: S3, boron diffusion, so that the inner layer and outer layer of the first intrinsic polysilicon layer are converted into a boron diffusion layer and a BSG layer respectively. Specifically, the boron diffusion conditions are: firstly, a mixed gas of BCl3 and O2 is introduced, the temperature is 850℃, the diffusion time is 10 min, the BCl3 gas flow rate is 200 sccm, and the O2 flow rate is 1200 sccm; then, O2 is introduced for oxidation advancement, the temperature is 950℃, the advancement time is 30 min, and the O2 flow rate is 7000 sccm, generating a BSG layer with a thickness of about 45 nm.

[0119] Performance Testing The electrical performance of the solar cells prepared in the above embodiments and comparative examples was tested, and the data are shown in the following table:

[0120] From the comparison of the data in the above table, we can see that: First, for Example 1, since an insulating dielectric film with a high dielectric constant is pre-deposited on the edge of the silicon wafer, the overall leakage value of the battery is low, and part of the edge position is further passivated by the insulating dielectric film, the corresponding electrical performance of the battery is better, and thus the overall electrical performance is optimal.

[0121] Secondly, for Example 2, a laser method is used to remove the oxide layer on the back of the silicon wafer, and then an alkaline cleaning is used to obtain a relatively flat surface without the oxide layer. Compared with Example 1, the use of the laser method will bring about the problem of laser damage to the silicon substrate, so the overall performance is slightly lower than that of Example 1.

[0122] For Comparative Example 1, since the side coating layer cannot be effectively removed during the preparation process of the battery (especially during the front / side de-coating process), the edge leakage has a greater impact, resulting in the worst overall electrical performance.

[0123] For Comparative Example 2, since only the "direct oxidation" method is used to form the first silicon oxide layer at the edge of the silicon wafer, the insulating dielectric film thickness is thin and the dielectric constant is low, which cannot effectively block the entry of doped atoms during the subsequent high-temperature diffusion process, resulting in an increased risk of battery leakage, which limits the overall performance improvement of the battery, but is higher than Comparative Example 1.

[0124] For Comparative Example 3, since the concentration of boron atoms introduced into the edge insulating dielectric film in the conventional one-step through-source boron diffusion process is low, the dielectric constant of the insulating dielectric film is limited. Compared with Examples 1-2, the overall electrical performance is lower, but this is due to Comparative Example 1-2.

[0125] The raw materials and equipment used in the present invention, unless otherwise specified, are all commonly used raw materials and equipment in the art; the methods used in the present invention, unless otherwise specified, are all conventional methods in the art.

[0126] The above description is only a preferred embodiment of the present invention and does not limit the present invention in any way. Any simple modification, change and equivalent transformation made to the above embodiment based on the technical essence of the present invention still falls within the protection scope of the technical solution of the present invention.

Claims

1. A method for preparing a TBC solar cell having an edge wrap coating, characterized in that include: S1, double-sided polishing of silicon wafer; S2, stacking; S3, oxidizing and depositing an insulating dielectric film at the edge of the silicon wafer; S4, back side oxide removal; S5, depositing a tunneling oxide layer and an intrinsic polysilicon layer on the back side; S6, two-step through-source boron diffusion, converting the intrinsic polysilicon layer into a boron diffusion layer and a BSG layer, densifying and boron-doping the insulating dielectric film; S7, removing the BSG layer in the phosphorus diffusion region and the isolation region; S8, alkali cleaning; S9, depositing a tunneling oxide layer and an intrinsic polysilicon layer on the back side; S10, phosphorus diffusion, converting the intrinsic polysilicon layer into a phosphorus diffusion layer and a PSG layer; S11, removing the PSG layer in the boron diffusion region and the isolation region; S12, de-plating; S13, cleaning and velveting; S14, double-sided coating; S15, screen printing, sintering, light injection.

2. The preparation method according to claim 1, characterized in that: In S2, the number of silicon wafers stacked each time is 100 to 300. After stacking, the front and back sides of adjacent silicon wafers are attached to each other, and the four edge sides are flush.

3. The preparation method according to claim 1, characterized in that: In S3, insulating dielectric films are sequentially constructed on the four edge sides of the stacked silicon wafers.

4. The preparation method according to claim 1, characterized in that: In S3, The insulating dielectric film is composed of a first silicon oxide layer and a second silicon oxide layer; The thickness of the first silicon oxide layer is 5 to 30 nm; The thickness of the second silicon oxide layer is 10-200 nm.

5. The preparation method according to claim 4, characterized in that: In S3, The oxidation comprises: introducing N2O to oxidize the shallow surface of the edge of the silicon wafer into a first silicon oxide layer; The deposition comprises: introducing SiH4 and N2O to deposit a second silicon oxide layer on the surface of the first oxide layer.

6. The preparation method according to claim 5, characterized in that: In S3, The oxidation conditions are: N2O flow rate 100-500 sccm, RF power 1000-10000 W, pressure 10-200 Torr, temperature 300-500°C, time 5-30 min; The deposition conditions are: flow ratio of SiH4 to N2O = 1:5~1:10, RF power 1000~10000 W, pressure 100~500 Torr, temperature 300~500°C, time 10~80 min.

7. The preparation method according to claim 1, characterized in that: In S4, a chain machine is used to acid-etch and remove the oxide layer on the back of the silicon wafer, using a 20-60 wt% HF aqueous solution as the etching solution and a belt speed of 1-10 m / min.

8. The preparation method according to claim 1, characterized in that: In S5 and S9, The deposition conditions of the tunnel oxide layer are: O2 flow rate 10000~80000 sccm, reaction temperature 400~800°C, time 200~1000 s, and tunnel oxide layer thickness 2~10 nm; The deposition conditions of the intrinsic polysilicon layer are: SiH4 flow rate 300~2000 sccm, reaction temperature 500~700°C, time 2~4 h, working gas pressure 100~500 mTorr, and intrinsic polysilicon layer thickness 100~300 nm.

9. The preparation method according to claim 1, characterized in that: In S6, the conditions for the two-step through-source boron diffusion are: One-step source: BCl3 flow rate 50~500 sccm, O2 flow rate 500~2000 sccm, temperature 800~950℃, time 5~50min; Oxidation promotion: O2 flow rate 5000~30000 sccm, temperature 900~1050℃, time 30~80 min; Two-step source: temperature 800~950℃, time 2~30 min, BCl3 flow rate 20~100 sccm, O2 flow rate 200~1000 sccm.

10. The preparation method according to claim 1, characterized in that: In S10, the conditions for phosphorus diffusion are: temperature 750~850℃, diffusion time 5~30 min, POCl3 is carried by nitrogen with a flow rate of 500~1200 sccm, O2 flow rate 500~1000sccm, oxidation advancement temperature 850~950℃, O2 flow rate 1000~10000 sccm, and advancement time 20~60 min.

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