Teleoperation surgery video transmitting system based on wireless transmission

Abstract

The invention discloses a teleoperation surgery video transmitting system based on wireless transmission. The teleoperation surgery video transmitting system comprises a video acquisition module, a video compression module, a data integration module and a wireless transmitting module, the video acquisition module is used for acquiring four paths of image data; the video compression module is connected with the video acquisition module and is used for compressing the four paths of image data; the data integration module is connected with the video compression module and is used for receiving the compressed four-way image data and integrating the compressed four-way image data; and the wireless sending module is connected with the data integration module, and is used for merging the integrated four paths of image data into one path and sending the one path to a wireless channel for transmission. According to the invention, the processing and transmission efficiency of the operation video in the operation can be improved.

Description

Technical Field

[0001] The invention relates to the technical field of image processing, and in particular to a remote-operation surgery video transmitting system based on wireless transmission. Background Art

[0002] Teleoperation surgery originated from the demand for surgical robots in minimally invasive surgery, and has attracted much attention and developed rapidly in recent years. Minimally invasive surgery is a surgical method that allows surgeons to perform treatment smoothly without causing large incisions to patients, mainly through endoscopes and various imaging technologies.

[0003] Minimally invasive surgery has formed a remote-controlled surgical system due to the rational application of surgical robot technology. It is usually composed of several slave surgical robotic arms, a video transmission imaging system and a main surgical console. The three independent subsystems have their own division of labor when performing the operation. Simply put, the attending physician stands next to the main console to control the surgical system. An endoscope and various surgical instruments can be installed at the end of the robot and directly inserted into the lesion area in the patient's body. During the whole process, the doctor only needs to observe the feedback image of the lesion area and control the joystick or buttons of the manipulator to control the robot to easily complete the surgical operation.

[0004] However, at present, my country has focused its research efforts on the control of the manipulator of surgical robots and the force feedback of scalpels, but rarely mentioned the research on surgical video transmission. However, surgical videos, as the eyes of doctors, cannot be ignored in the future development. The clarity of transmission has changed from 480P to 720 in the past to 1080P, which is the main research of this system, and then to 2K and 4K videos, etc., which will inevitably be studied with the continuous development of science and technology. The transmission of high-definition video, ultra-clear video and even blue-ray video is the general trend of future development. Summary of the invention

[0005] In view of the above-mentioned deficiencies in the prior art, the present invention provides a remote-operated surgical video transmission system based on wireless transmission, which solves the problem of low efficiency of surgical video processing in medical surgeries in the prior art.

[0006] In order to achieve the above-mentioned invention object, the technical solution adopted by the present invention is: a teleoperation surgery video transmission system based on wireless transmission, comprising:

[0007] Video acquisition module, video compression module, data integration module and wireless transmission module;

[0008] Video acquisition module, used to acquire four channels of image data;

[0009] The video compression module is connected to the video acquisition module and is used to compress the four-channel image data;

[0010] The data integration module is connected to the video compression module and is used to receive the compressed four-channel image data and integrate the compressed four-channel image data;

[0011] The wireless transmission module is connected to the data integration module and is used to merge the four channels of image data into one channel and send it to the wireless channel for transmission.

[0012] The beneficial effects of the above scheme are as follows: the present invention reduces the size of the original video data through the video compression module, making data transmission and storage more efficient, and reducing network bandwidth requirements and storage costs. The data integration module optimizes the data stream structure by rationally organizing and packaging data, making wireless transmission smoother and reducing potential delays and packet loss in data processing and transmission. The efficient data processing and transmission mechanism reduces the demand for expensive hardware resources, and the wireless transmission method also facilitates installation and wiring, further reducing deployment and operation and maintenance costs. This improves the processing and transmission efficiency of surgical videos during surgery.

[0013] Furthermore, the video acquisition module includes four OV5640 cameras, a SN74AVCA164245 level conversion chip, a SN74AVC2T45 chip, and a PCA9306 chip;

[0014] Each OV5640 camera is used to collect one channel of image data;

[0015] The external clock signal of the OV5640 camera is a 24MHz crystal oscillator.

[0016] Further, the video compression module includes a DSP chip;

[0017] The model of DSP chip is TMS320DM368;

[0018] The first pin of the DSP chip is connected to the first pin of each OV5640 camera through the SN74AVCA164245 level conversion chip. The SN74AVCA164245 level conversion chip is used to match the voltage of the first pin of each OV5640 camera with the voltage of the first pin of the DSP chip;

[0019] The second pin of the DSP chip is connected to the second pin of each OV5640 camera through the SN74AVC2T45 chip. The SN74AVC2T45 chip is used to realize the level conversion of the Reset signal and the PWDN enable signal.

[0020] The third pin of the DSP chip is connected to the third pin of each OV5640 camera through the PCA9306 chip. The PCA9306 chip is used to realize bidirectional voltage conversion of the SCCB control bus.

[0021] The beneficial effects of the above further scheme are: each OV5640 camera is a high-performance 5-megapixel sensor that can provide clear, high-quality image data; the SN74AVCA164245 level conversion chip is used to transmit signals between systems with different voltage levels, ensuring the signal compatibility and integrity between the OV5640 camera (which may run at a lower voltage level) and the subsequent higher voltage level logic circuit, avoiding signal loss or damage; the SN74AVC2T45 chip acts as a high-speed signal switch and level converter, which enhances the signal quality of the system during high-speed data transmission, especially between different power domains, helping to maintain signal stability and reduce noise interference; the PCA9306 chip acts as an I2C bus level converter, allowing effective communication between the camera module and other I2C devices even with different power supply voltages. Using a 24MHz external crystal oscillator to provide a clock signal for the OV5640 camera ensures that the camera can operate at an accurate and stable frequency, which is essential for synchronizing data acquisition and maintaining the continuity of the video stream, helping to reduce image distortion and improve overall system performance.

[0022] Further, the DSP chip includes a video processing front end VPSS, an ARM subsystem, an HDVICP processor, an MJCP processor, a video processing back end VPBE and peripheral devices;

[0023] The video processing front end VPSS is used to collect four-channel image data;

[0024] The ARM subsystem is used to perform system control tasks, including system initialization, configuration, and running commands;

[0025] HDVICP processor is used to implement H.264 encoding;

[0026] The MJCP processor is used to run image processing algorithms, which process image formats including MPEG and JPEG;

[0027] The video processing backend VPBE is used to connect to a variety of external displays;

[0028] Peripheral devices are used for communication, debugging, control and providing interfaces.

[0029] The beneficial effect of the above further scheme is that the DSP chip TMS320DM368 realizes the optimization of the whole chain from video data acquisition, processing, encoding to display through its highly integrated design and professional processing unit, providing a solid foundation for building an efficient, flexible and high-quality video processing system.

[0030] Further, the 8-bit data signal D[7:0] of each OV5640 camera is connected to the YIN[7:0] input interface of the VPFE port of the DSP chip;

[0031] The clock signal C_PCLK of each OV5640 camera is connected to the PCLK input interface of the VPFE port of the DSP chip;

[0032] The horizontal synchronization signal C_HD of each OV5640 camera is connected to the HD input interface of the VPFE port of the DSP chip;

[0033] The field synchronization signal C_VD of each OV5640 camera is connected to the VD input interface of the VPFE port of the DSP chip.

[0034] The beneficial effect of the above further scheme is: by directly connecting the camera's 8-bit data signal D[7:0] to the YIN[7:0] input interface of the DSP chip, it is ensured that the image pixel data can be captured and processed with the shortest delay and the highest integrity, ensuring the real-time processing of the video stream. The direct connection of C_PCLK (pixel clock signal) to the PCLK interface ensures the precise timing of data sampling, and each pixel data is read at the correct clock edge, avoiding data misalignment or loss, and improving the quality of image reconstruction. C_HD (line synchronization signal) and C_VD (field synchronization signal) are connected to the HD and VD interfaces respectively, so that the DSP can clearly identify the starting position of each line and each frame, which plays a decisive role in forming a complete video frame, avoiding screen tearing, and maintaining video smoothness.

[0035] Further, the data integration module includes an interface processing unit, a data integration unit and a packaging and sending unit;

[0036] Wherein, the data integration unit includes an FPGA chip;

[0037] The model of the FPGA chip is EP4CE30F23C6N;

[0038] The FPGA chip is connected to the EMIF interface of the DSP chip, and the EMIF interface is used to transmit compressed four-channel image data;

[0039] The FPGA chip is used to perform interleaving encoding on the compressed four-channel image data to obtain interleaved encoded image data, package the interleaved encoded image data and send it to the wireless transmission module using the Gigabit network port.

[0040] The beneficial effects of the above further scheme are: the FPGA chip has a high degree of parallel processing capability and programmability, and can be customized for the interleaved coding of image data, which accelerates the image data processing speed and improves the real-time performance of the entire system. The EMIF interface is connected to the DSP chip to ensure high-speed and stable data exchange, so that the compressed image data can be quickly transferred to the FPGA for subsequent processing, optimizing the data flow efficiency within the system. The FPGA intelligently packages the interleaved coded image data, which can more effectively utilize the bandwidth resources of the Gigabit network port, ensuring that high-data-volume image information can be sent to the wireless transmission module through the network in a timely and lossless manner, reducing network congestion and waiting time.

[0041] Furthermore, the FPGA chip includes 5 FIFOs, an interleaving processing module, a UDP protocol module, a controller module and a PLL phase-locked loop module;

[0042] The interleaving processing module is used to perform interleaving coding on the compressed four-channel image data.

[0043] The beneficial effects of the above further scheme are: the interleaving coding technology is implemented on the FPGA, which can reorganize the image data at the packet level, disperse the impact of consecutive errors, and improve the possibility of data recovery, which is especially important for packet loss or damage in wireless transmission, and enhances the robustness of data transmission.

[0044] Further, the wireless transmission module includes a WIFI module SKW77;

[0045] The WIFI module SKW77 is compatible with 802.11b / g / n, uses 2x2 MIMO radio frequency, and has a maximum rate of 300Mbps;

[0046] The WIFI module SKW77 includes dual-channel PA and LNA, and the minimum transmit output power of each PA and LNA is +28dBm;

[0047] The external power supplies of the WIFI module SKW77 are +5.0V and +3.3V respectively.

[0048] Further, the WIFI module SKW77 includes an MT7620A chip;

[0049] The MT7620A chip includes instruction pointer register, memory accessor, single error correction code, data frame buffer, media access control layer, baseband processor, SCH, SEC Tables and Packet Buffer.

[0050] Single error correction code is used to add checksum to the transmitted data.

[0051] The beneficial effect of the above further solution is that the single error correction code can add a check code during the data transmission process. When a data packet encounters slight interference or noise during wireless transmission, resulting in a single-bit error, the receiving end can automatically detect and correct the error through the check code, thereby ensuring the accuracy of the received data and improving the reliability of data transmission. Furthermore, the performance and user experience of the WIFI module SKW77 in complex wireless environments are improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] Figure 1 The diagram is a schematic diagram of the system structure of a teleoperated surgery video transmission system based on wireless transmission.

[0053] Figure 2 This is a schematic diagram of the FPGA structure.

[0054] Figure 3 It is a thread schematic block diagram of the DSP chip.

[0055] Figure 4 This is a simplified diagram of the internal logic of the FPGA chip.

[0056] Figure 5 This is the internal block diagram of the MT7620A chip. DETAILED DESCRIPTION

[0057] The present invention will be further described below in conjunction with the accompanying drawings and specific embodiments.

[0058] like Figure 1 As shown, a teleoperation surgery video transmission system based on wireless transmission includes:

[0059] Video acquisition module, video compression module, data integration module and wireless transmission module.

[0060] The video acquisition module is used to acquire four channels of image data.

[0061] The video compression module is connected to the video acquisition module and is used for compressing four channels of image data.

[0062] The data integration module is connected to the video compression module and is used for receiving the compressed four-channel image data and integrating the compressed four-channel image data.

[0063] The wireless transmission module is connected to the data integration module and is used to merge the four channels of image data into one channel and send it to the wireless channel for transmission.

[0064] In this embodiment, the video acquisition module includes four OV5640 cameras, a SN74AVCA164245 level conversion chip, a SN74AVC2T45 chip and a PCA9306 chip; each OV5640 camera is used to collect one channel of image data; the external clock signal of the OV5640 camera is a 24MHz crystal oscillator.

[0065] For example, the video acquisition module selects OV5640 of Omni Vision as the acquisition camera. The OV5640 chip supports 6-24MHz external clock input, so a 24MHz crystal oscillator can be provided as an external clock signal, and the required clock signal can be obtained through an internal phase-locked loop.

[0066] In this embodiment, the video compression module includes a DSP chip; the model of the DSP chip is TMS320DM368; the first pin of the DSP chip is connected to the first pin of each OV5640 camera through the SN74AVCA164245 level conversion chip, and the SN74AVCA164245 level conversion chip is used to match the first pin voltage of each OV5640 camera and the first pin voltage of the DSP chip; the second pin of the DSP chip is connected to the second pin of each OV5640 camera through the SN74AVC2T45 chip, and the SN74AVC2T45 chip is used to realize the level conversion of the Reset signal and the PWDN enable signal; the third pin of the DSP chip is connected to the third pin of each OV5640 camera through the PCA9306 chip, and the PCA9306 chip is used to realize the bidirectional voltage conversion of the SCCB control bus.

[0067] In this embodiment, the DSP chip includes a video processing front-end VPSS, an ARM subsystem, an HDVICP processor, an MJCP processor, a video processing back-end VPBE and peripheral devices; the video processing front-end VPSS is used to collect four-channel image data; the ARM subsystem is used to execute system control tasks, and the system control tasks include system initialization, configuration and running commands; the HDVICP processor is used to implement H.264 encoding; the MJCP processor is used to run the image processing algorithm, and the image formats processed by the image processing algorithm include MPEG and JPEG; the video processing back-end VPBE is used to connect to a variety of external displays; the peripheral devices are used for communication, debugging, control and providing interfaces.

[0068] For example, Figure 3 As shown, Figure 3 This is a thread diagram of the DSP chip. Figure 3In the DSP chip, high-definition compression encoding mainly relies on the main thread, control thread, video acquisition thread, video encoding thread and writing thread. The main thread's main task is to perform necessary initialization, the control thread controls and displays encoding parameters, the video acquisition thread acquires data input by the camera, the video encoding thread receives data from the video acquisition thread for encoding, and the video writing thread receives data from the video encoding thread and writes it into the cache.

[0069] In this embodiment, the 8-bit data signal D[7:0] of each OV5640 camera is connected to the YIN[7:0] input interface of the VPFE port of the DSP chip; the clock signal C_PCLK of each OV5640 camera is connected to the PCLK input interface of the VPFE port of the DSP chip; the line synchronization signal C_HD of each OV5640 camera is connected to the HD input interface of the VPFE port of the DSP chip; the field synchronization signal C_VD of each OV5640 camera is connected to the VD input interface of the VPFE port of the DSP chip.

[0070] Exemplarily, the OV5640 cameras in this embodiment all use 8-bit RAW Bayer format output, and the video acquisition module connects the output signals of OV5640: 8-bit data signal D[7:0], clock signal C_PCLK, line synchronization signal C_HD and field synchronization signal C_VD to the input interfaces YIN[7:0], PCLK, HD and VD of the VPFE port of the DSP chip respectively.

[0071] In this embodiment, the data integration module includes an interface processing unit, a data integration unit and a packaging and sending unit; wherein the data integration unit includes an FPGA chip; the model of the FPGA chip is EP4CE30F23C6N; the FPGA chip is connected to the EMIF interface of the DSP chip, and the EMIF interface is used to transmit the compressed four-channel image data; the FPGA chip is used to interleave the compressed four-channel image data to obtain the interleaved encoded image data, package the interleaved encoded image data and send it to the wireless transmission module using the gigabit network port.

[0072] For example, Figure 2 As shown, Figure 2 This is a schematic diagram of the FPGA structure. Figure 2 In the process, FPGA mainly implements several tasks: first, it connects with the EMIF interface to enable data transmission with the DSP; second, it interleaves and encodes the four-way video data; third, it packages the interleaved data and sends the data to the wireless transmission module using the Gigabit network port. Figure 2The power management and clock management provide stable power supply and correct clock for FPGA and peripheral circuits. The JTAG interface is used to download and debug programs, and FLASH is used to store the written programs.

[0073] For example, the TMS320DM368 chip compresses four-channel image data and transmits the compressed data to the FPGA through the EMIF interface for further processing. Each DSP chip uses the same format for output to avoid the problem of different amounts of encoded data after output. Among them, power management and clock management provide power and correct clocks for the DSP chip and other peripheral hardware to work properly. The four-channel image data collected by OV5640 is input by the ISIF interface in the video processing front end and configured with the IIC bus. UART and network interfaces can be used for early program debugging. DDR2 provides memory space for the operation of compressed applications, and flash can store operating systems and compression programs.

[0074] In this embodiment, the FPGA chip includes 5 FIFOs, an interleaving processing module, a UDP protocol module, a controller module and a PLL phase-locked loop module; the interleaving processing module is used to perform interleaving encoding on the compressed four-channel image data.

[0075] For example, Figure 4 This is a simplified diagram of the internal logic of the FPGA chip. The FPGA chip has powerful parallel processing capabilities, including two processes: data integration and packaging and sending.

[0076] exist Figure 4 In the figure, the black line is the data direction. The FPGA chip caches the data compressed by the DSP chip into the FIFO. Then the interleaving processing module takes out the data from the four FIFOs for interleaving encoding and stores the interleaved data into the FIFO for caching. Finally, the interleaved data in the FIFO is taken out for packaging and sending by the network protocol. The blue line is the control signal, which is provided by the controller and provides trigger signals for each part to achieve the purpose of control. The red line is the clock signal, which is provided by the PLL phase-locked loop module. The PLL phase-locked loop module divides or multiplies the clock and provides the correct clock signal to each part.

[0077] In the process of packet transmission, the Realtek Gigabit GPHY chip RTL8211E is used on the FPGA chip to realize Gigabit Ethernet data communication. The most important thing to realize Gigabit Ethernet data transmission is the packaging of the network protocol and driving the network port chip to complete the data transmission. Therefore, the UDP protocol is used for transmission. Based on the study of the protocol and the understanding of the data frame format, the Ethernet data transmission process is converted into code implementation to complete the logic design of the network port module. The process of packet transmission is as follows:

[0078] 1) First, the transport layer completes UDP data encapsulation, adds port number and checksum information to the encapsulated data, and transmits the obtained data information to the network layer.

[0079] 2) The network layer integrates the received data, encapsulates the data information into a datagram, adds an IP header to the encapsulated datagram and transmits it to the link layer.

[0080] 3) The data packet is sent through the MAC address. At this time, the MAC address and other information are added to the outside of the IP datagram obtained from the network layer and encapsulated into an Ethernet data frame.

[0081] In this embodiment, the wireless sending module includes a WIFI module SKW77; the WIFI module SKW77 is compatible with 802.11b / g / n, uses a 2x2MIMO radio frequency, and has a maximum rate of 300Mbps; the WIFI module SKW77 includes a dual-channel PA and LNA, and the minimum transmit output power of each PA and LNA is +28dBm; the external power supplies of the WIFI module SKW77 are +5.0V and +3.3V respectively.

[0082] For example, the WIFI module SKW77 has its own operating system and can communicate with the FPGA via a network port.

[0083] In this embodiment, the WIFI module SKW77 includes an MT7620A chip; the MT7620A chip includes an instruction pointer register, a memory accessor, a single error correction code, a data frame cache, a media access control layer, a baseband processor, SCH, SECTables and PacketBuffer; the single error correction code is used to add a check code to the transmitted data.

[0084] like Figure 5 As shown, Figure 5 This is the internal block diagram of the MT7620A chip. Figure 5In the MT7620A chip, the instruction pointer register communicates with other modules through the low-speed bus PBus. When the data sent from the network port is cached, it enters the direct memory access device (PDMA) through the high-speed data bus RBus, and the data is added with a check code through SEC (Single-Error-Correcting Code). After adding the SEC check, if there is a bit error in the sent data, the SEC check code can correct the data error at the receiving end. Then the data with the check code enters the PBF module for data frame cache. The cached data will enter the media access control layer (MAC), and the physical layer can be managed through the MAC layer. The MAC first detects the physical layer to determine whether the physical layer can meet the requirements of data transmission. If the physical layer meets the requirements, data transmission will be carried out. The MAC layer adds control information to the transmission data and then sends it to the baseband processor (BBP). The baseband encoding is completed through the BBP. When sending data through WIFI, the BBP encodes the data uploaded from the MAC, and then after D / A conversion, the data is sent to the wireless channel through the antenna device to complete the wireless transmission.

[0085] Among them, SEC check is similar to parity check, the only difference is that there is no linear relationship between the length of the data and the number of check code bits.

[0086] Those skilled in the art will appreciate that the embodiments described herein are intended to help readers understand the principles of the present invention, and should be understood that the protection scope of the present invention is not limited to such specific statements and embodiments. Those skilled in the art can make various other specific variations and combinations that do not deviate from the essence of the present invention based on the technical revelations disclosed by the present invention, and these variations and combinations are still within the protection scope of the invention.

Claims

1. A teleoperation surgery video transmission system based on wireless transmission, characterized in that: The teleoperation surgery video transmission system comprises: Video acquisition module, video compression module, data integration module and wireless transmission module; The video acquisition module is used to acquire four channels of image data; The video compression module is connected to the video acquisition module and is used to compress the four channels of image data; The data integration module is connected to the video compression module, and is used to receive the compressed four-channel image data and integrate the compressed four-channel image data; The wireless transmission module is connected to the data integration module and is used to merge the four channels of image data into one channel and send it to the wireless channel for transmission.

2. The system according to claim 1, characterized in that The video acquisition module includes 4 OV5640 cameras, SN74AVCA164245 level conversion chip, SN74AVC2T45 chip and PCA9306 chip; Each of the OV5640 cameras is used to collect one channel of image data; The external clock signal of the OV5640 camera is a 24MHz crystal oscillator.

3. The system according to claim 2, characterized in that The video compression module includes a DSP chip; The model of the DSP chip is TMS320DM368; The first pin of the DSP chip is connected to the first pin of each of the OV5640 cameras through the SN74AVCA164245 level conversion chip, and the SN74AVCA164245 level conversion chip is used to match the first pin voltage of each of the OV5640 cameras with the first pin voltage of the DSP chip; The second pin of the DSP chip is connected to the second pin of each of the OV5640 cameras through the SN74AVC2T45 chip, and the SN74AVC2T45 chip is used to realize the level conversion of the Reset signal and the PWDN enable signal; The third pin of the DSP chip is connected to the third pin of each of the OV5640 cameras through the PCA9306 chip, and the PCA9306 chip is used to realize bidirectional voltage conversion of the SCCB control bus.

4. The system according to claim 3, characterized in that The DSP chip includes a video processing front end VPSS, an ARM subsystem, an HDVICP processor, an MJCP processor, a video processing back end VPBE and peripheral devices; The video processing front end VPSS is used to collect the four channels of image data; The ARM subsystem is used to execute system control tasks, which include system initialization, configuration and operation commands; The HDVICP processor is used to implement H.264 encoding; The MJCP processor is used to run an image processing algorithm, and the image processing algorithm processes image formats including MPEG and JPEG; The video processing backend VPBE is used to connect to a variety of external displays; The peripheral devices are used for communication, debugging, control and providing interfaces.

5. The system according to any one of claims 2 to 4, characterized in that: The 8-bit data signal D[7:0] of each of the OV5640 cameras is connected to the YIN[7:0] input interface of the VPFE port of the DSP chip; The clock signal C_PCLK of each of the OV5640 cameras is connected to the PCLK input interface of the VPFE port of the DSP chip; The line synchronization signal C_HD of each of the OV5640 cameras is connected to the HD input interface of the VPFE port of the DSP chip; The field synchronization signal C_VD of each of the OV5640 cameras is connected to the VD input interface of the VPFE port of the DSP chip.

6. The system according to claim 5, characterized in that The data integration module includes an interface processing unit, a data integration unit and a packaging and sending unit; Wherein, the data integration unit includes an FPGA chip; The model of the FPGA chip is EP4CE30F23C6N; The FPGA chip is connected to the EMIF interface of the DSP chip, and the EMIF interface is used to transmit the compressed four-channel image data; The FPGA chip is used to perform interleaving encoding on the compressed four-channel image data to obtain interleaved encoded image data, package the interleaved encoded image data and send it to the wireless transmission module using the Gigabit network port.

7. The system according to claim 6, characterized in that The FPGA chip includes 5 FIFOs, an interleaving processing module, a UDP protocol module, a controller module and a PLL phase-locked loop module; The interleaving processing module is used to perform interleaving encoding on the compressed four-channel image data.

8. The system according to claim 1, characterized in that The wireless transmission module includes a WIFI module SKW77; The WIFI module SKW77 is compatible with 802.11b / g / n, uses 2x2 MIMO radio frequency, and has a maximum rate of 300Mbps; The WIFI module SKW77 includes a dual-channel PA and LNA, and the minimum transmission output power of each channel of the PA and LNA is +28dBm; The external power supplies of the WIFI module SKW77 are +5.0V and +3.3V respectively.

9. The system according to claim 1, characterized in that The WIFI module SKW77 includes an MT7620A chip; The MT7620A chip includes an instruction pointer register, a memory access device, a single error correction code, a data frame buffer, a media access control layer, a baseband processor, an SCH, SEC Tables and a Packet Buffer. The single error correction code is used to add a check code to the transmitted data.

Images