Array design and integration method of soft substrate circuit wafer

Abstract

The invention discloses an array design and integration method of a soft substrate circuit wafer, and relates to the field of micro-assembly, and the method comprises the steps: S1, carrying out the micro-module design; s2, carrying out circuit sheet layout design; s3, based on the output of the circuit piece layout design in the step S2, array integration tool design is carried out, and the micro-module design scheme in the step S1 and the circuit piece layout design scheme in the step S2 are optimized in combination with tool manufacturability; and S4, realizing array integration of the circuit wafer and the carrier plate and dividing and cutting the circuit wafer and the carrier plate. According to the method, batch integrated elements are introduced into the layout drawing design, the integration efficiency of the circuit wafer and the carrier plate can be remarkably improved, the loss of the circuit wafer in the disassembling and clamping processes can be reduced, the influence of human factors on the integration quality can be effectively reduced, and the whole process of carrier plate design, circuit wafer layout design and tool design can be greatly improved. And the requirements in a high-automation production state are met.

Description

Technical Field

[0001] The invention relates to the field of micro-assembly, and in particular to an array design and integration method of a soft substrate circuit chip. Background Art

[0002] The statements in this section merely provide background information related to the present disclosure and may not constitute prior art.

[0003] As the main transmission medium of microwave radio frequency, soft substrate circuit chips (hereinafter referred to as circuit chips) are widely used in the field of micro-assembly. With the trend of miniaturization and arraying of micro-modules, the traditional process of "disassembling the board first and then integrating" can no longer meet the needs of high production due to its complex process and high proportion of repetitive work.

[0004] Chinese patent CN108098232A discloses a parallel seam welding cover array fixture and welding method, which realizes the placement, fixation and welding of double-sided pin shells, greatly reduces loading and unloading time, and improves parallel seam welding efficiency. Japanese patent JP2901594B1 discloses a metal ball array method and device, which uses the array holes on the fixture to absorb metal balls in batches with the help of a vacuum device and transfers them to the carrier to realize batch inspection and installation of metal balls. Korean patent KR200467500Y1 discloses a line array fixture, which realizes the planar array of wires through the grooves of the fixture, and then realizes the three-dimensional array of wires through the fixture array, realizing the equal spacing of wires, and providing a basis for batch operation of subsequent processes. Chinese patent CN115551186A provides a large-area circuit chip welding structure and welding method. Through the array fixture design, the integration of circuit chips, preformed solder sheets and packaging carriers is realized, while improving welding efficiency, effectively reducing the problems of high void rate and uncontrollable overflow. Chinese patent CN201645105U discloses a welding fixture for microwave circuits, which effectively reduces the deformation of circuit chips after welding by clamping screws and pressing blocks, and has the advantages of simple clamping and good welding quality.

[0005] The above patents show that array chemical assembly can greatly improve production efficiency, but the current array integration still relies on the loading of discrete circuit chips, and cannot overcome the excess materials and scratches caused by circuit chip disassembly and frequent clamping.

[0006] Therefore, the present invention provides an arraying method for the integration of soft substrate circuit chips, which can realize the batch and rapid integration of metal carrier boards on the entire circuit chip panel, and then separate the boards by cutting, which can effectively reduce the impact of human operation on the integration of circuit chips. Compared with traditional bonding and welding processes, it reduces multiple steps and meets the current product form and output requirements. Summary of the invention

[0007] The purpose of the present invention is to provide an array design and integration method for soft substrate circuit chips in response to the problems existing in the prior art. Through the coordinated design of circuit chip layout and tooling, the array integration of circuit chips and metal carrier boards is realized, and an "integration first and then board disassembly" model is constructed. Compared with the traditional "first board disassembly and then integration" process path, it not only improves the output efficiency, but also effectively avoids a large number of repetitive operations and the generation of redundant materials, realizes the leap from traditional manual integration to semi-automatic integration, and significantly improves the integration efficiency and integration accuracy.

[0008] The technical solution of the present invention is as follows:

[0009] An array design and integration method of a soft substrate circuit chip, comprising:

[0010] Step S1: Designing a micromodule, including the size of the carrier board, the size of the circuit chip, and the relative position of the two. The design output of the micromodule is used as the design input of the circuit chip layout and array integration tooling;

[0011] Step S2: Conducting circuit board layout design; Based on the output of the micromodule design in step S1, conducting circuit board layout design, and iteratively optimizing the micromodule design scheme in step S1 in combination with arrayable integrated elements;

[0012] Step S3: Based on the output of the circuit board layout design in step S2, the array integration tooling design is carried out, and the micromodule design scheme in step S1 and the circuit board layout design scheme in step S2 are optimized in combination with the tooling manufacturability;

[0013] Step S4: realizing array integration of the circuit chip and the carrier board and cutting them into sections.

[0014] Furthermore, in step S1, the edge of the circuit chip and the edge of the carrier board overlap at least at one point.

[0015] Furthermore, in step S2, the circuit chip array spacing e is determined in combination with the relative positions of the circuit chip and the carrier board to ensure that the carrier board spacing f is greater than 4 mm.

[0016] Furthermore, the circuit chip process ribs are arranged at positions that are not adjacent to the pattern on the overlapping sides of the circuit chip edge and the carrier edge.

[0017] Furthermore, the pin holes are arranged at the outermost ribs of the circuit chip, the diameter of the pin holes shall not be less than 4 mm, and the distance between the edge of the pin hole and the edge of the circuit chip substrate where the hole is located shall not be less than 1 / 2 of the hole diameter; the number of pin holes is at least 4, located at the four corners of the circuit chip layout and symmetrically centered. If more than four pin holes are required, the total number of pin holes should be a multiple of 4 and be evenly distributed along the outermost ribs of the circuit chip, and the distance between the pin holes shall not be less than 2 times the hole diameter.

[0018] Furthermore, the tooling in step S3 includes: a base, a pressure block, and a pin; the material of the tooling should be the same as that of the micromodule carrier, the pin has a negative tolerance, the pin hole has a positive tolerance, the processing tolerance is less than 0.01mm, the flatness is less than 0.05mm, and the surface roughness is less than 1.6.

[0019] Furthermore, the tooling is provided with pin holes of the same size corresponding to the pin holes on the circuit chip layout drawing; the pin holes at the pressing block and the circuit chip are through holes, and the pin holes at the base are blind holes. After assembly, the pin ends should be at least 20 mm higher than the upper surface of the pressing block.

[0020] Furthermore, the depth g of the groove at the base for holding the micromodule carrier should be 1 / 3 to 1 / 2 of the thickness h of the micromodule carrier, the length and width of the base groove are 0.1 mm larger than the length and width of the carrier, and a positive tolerance is taken; the width c of the tooling pressing block is 0.1 mm smaller than the width b of the circuit chip on one side, and a high-temperature resistant gel should be attached to the bottom of the pressing block.

[0021] Furthermore, the single-side gap h between the inner contour of the base and the outer contour of the pressing block is less than 0.05 mm, a through hole is provided at the tooling base below the carrier plate, and the upper surface of the tooling pressing block should have a handle for separating it from the tooling base.

[0022] Furthermore, in step S4, the array integration of the micromodules is achieved in the order of placing a carrier board, placing adhesive / soldering material, placing a circuit chip, inserting pins, oven curing / reflow soldering, and cutting and disassembling the board.

[0023] The array design and integration method of a soft substrate circuit chip described in the present invention, compared with the traditional circuit chip layout design, introduces batch integration elements into the layout design, which can significantly improve the integration efficiency of the circuit chip and the carrier, reduce the loss of the circuit chip during the board removal and clamping process, effectively reduce the impact of human factors on the integration quality, and meet the needs of highly automated production from the entire process of carrier board design, circuit chip layout design, and tooling design. Compared with the prior art, the array integration method proposed by the present invention has the following advantages:

[0024] (1) A collaborative design model of micromodules, circuit board layouts, and tooling is adopted to achieve the ability to be arrayed and produced as soon as the micromodule design stage is completed.

[0025] (2) Through array integration, the semi-automatic integration of circuit chips is realized by "integrating first and then removing the board", which effectively avoids the "first removing the board and then integrating" in the traditional manual single-piece integration, and eliminates the current situation of pure manual bonding and frequent clamping of traditional soft substrate circuit chips.

[0026] (3) The present invention is applicable to both bonding and welding processes, and each micromodule of the tooling base has a through hole under it for easy disassembly. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 is the method overview diagram;

[0028] Figure 2 It is a schematic diagram of the overlap of the edges of the circuit chip and the carrier board;

[0029] Figure 3 It is the circuit board spacing control;

[0030] Figure 4 It is a cross-sectional view of the tooling;

[0031] Figure 5 It is a schematic diagram of carrier placement;

[0032] Figure 6 It is a schematic diagram of circuit chip placement;

[0033] Figure 7 It is a schematic diagram of the placement of the pressing block and the pins;

[0034] Figure 8 This is a schematic diagram of the plate cutting.

[0035] Figure numerals: 1-micromodule carrier, 2-circuit chip body, 3-circuit chip process ribs, 4-base, 5-pressing block, 6-pin, 7-gel pad, 8-adhesive / soldering material. DETAILED DESCRIPTION

[0036] It should be noted that relational terms such as "first" and "second" are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0037] The features and performance of the present invention are further described in detail below in conjunction with the embodiments.

[0038] Embodiment 1

[0039] See also Figure 1, an array design and integration method of a soft substrate circuit chip, specifically comprising the following steps:

[0040] Step S1: Micromodule design. Including the size of the carrier board, the size of the circuit chip and the relative position of the two, the design output of the micromodule is used as the design input of the circuit chip layout and array integration tooling.

[0041] Step S2: Based on the output of the micromodule design in S1, the circuit board layout design is carried out, and the micromodule design scheme in S1 is iteratively optimized in combination with arrayable integrated elements;

[0042] Step S3: Based on the output of the circuit board layout design in S2, carry out array integration tooling design, and optimize the micromodule design scheme in S1 and the circuit board layout design scheme in S2 in combination with the tooling manufacturability;

[0043] Step S4: realizing array integration of the circuit chip and the carrier board and cutting them into sections.

[0044] In this embodiment, specifically, in step S1, the edge of the circuit chip and the edge of the carrier board overlap at least at one point.

[0045] In this embodiment, specifically, in step S2, the circuit chip array spacing e should be determined in combination with the relative positions of the circuit chip and the carrier board to ensure that the carrier board spacing f is greater than 4 mm.

[0046] In this embodiment, specifically, the circuit chip process ribs should be arranged at a position that is not adjacent to the pattern on the overlapping side of the circuit chip edge and the carrier edge.

[0047] In this embodiment, specifically, the pin holes are arranged at the outermost ribs of the circuit sheet, the pin hole diameter shall not be less than 4 mm, and the distance between the edge of the pin hole and the edge of the circuit sheet substrate where the hole is located shall not be less than 1 / 2 of the hole diameter. The number of pin holes is at least 4, and they must be located at the four corners of the circuit sheet layout and symmetrically centered. If more than four pin holes are required, the total number of pin holes should be a multiple of 4 and be evenly spaced along the outermost ribs of the circuit sheet, and the distance between the pin holes shall not be less than 2 times the hole diameter.

[0048] In this embodiment, specifically, the material of the tooling (including the base, the pressure block, and the pin) in step S3 should be the same as that of the micromodule carrier, the pin has a negative tolerance, the pin hole has a positive tolerance, the processing tolerance is less than 0.01mm, the flatness is less than 0.05mm, and the surface roughness is less than 1.6.

[0049] In this embodiment, specifically, the positioning through holes of the circuit chip layout diagram described in (5) in the tooling should have pin holes of the same size. The pin holes at the tooling block and the circuit chip are through holes, and the pin holes at the tooling base are blind holes. After assembly, the pin ends should be at least 20 mm higher than the upper surface of the block.

[0050] In this embodiment, specifically, the depth g of the groove for holding the micromodule carrier at the tooling base should be 1 / 3 to 1 / 2 of the thickness h of the micromodule carrier, and the length and width of the tooling base groove are 0.1 mm larger than the length and width of the carrier, and a positive tolerance is taken. The width c of the tooling block should be 0.1 mm smaller than the width b of the circuit chip on one side, and a high temperature resistant gel should be attached to the bottom of the block.

[0051] In this embodiment, specifically, the single-sided gap h between the inner contour of the base and the outer contour of the pressing block is less than 0.05 mm, a through hole should be provided at the tooling base below the carrier plate, and the upper surface of the tooling pressing block should have a handle for separating it from the tooling base.

[0052] In this embodiment, specifically, in step S4, the array integration of micromodules is achieved in the order of placing a carrier board, placing adhesive / soldering material, placing a circuit chip, inserting pins, oven curing / reflow soldering, and cutting and disassembling the board.

[0053] Embodiment 2

[0054] This embodiment is a specific application of an array design and integration method of a soft substrate circuit chip proposed in the first embodiment, and specifically includes:

[0055] (1) Figure 1 As shown, this embodiment proposes to carry out collaborative design work according to the process of "micromodule design-circuit board design-tool design". The demand for batch manufacturability is introduced when designing the relative position of the circuit chip on the carrier, and the micro-printed board and fixture structure are collaboratively designed to achieve batch manufacturing of micromodules. The tooling produced by the design process can be used for three process routes: conductive adhesive bonding, prefabricated solder sheet welding, and solder paste coating welding.

[0056] (2) Figure 2 As shown, the size of the carrier board is 4mm*3mm*0.4mm, and it is made of 4J29 Kovar alloy. The size of the circuit chip is 3mm*3mm*0.127mm. The carrier board and the circuit chip have two overlapping edges, and process ribs are designed at the two edges to ensure the feasibility of subsequent cutting and sub-boarding.

[0057] (3) Circuit board layout design Figure 3As shown, the horizontal spacing of the circuit chips is e = 7mm. Combined with the size of the circuit chips and the carrier board in the micromodule design and their relative positions, the horizontal spacing of the carrier board is determined to be f = 6mm, which meets the requirement of at least 4mm in claim (3). The dimensional characteristics in the vertical direction are the same as those in the horizontal direction.

[0058] (4) Figure 4 As shown in the cross-sectional view, the groove for placing the carrier board at the tooling base is 4.1mm*3.1mm in length and width, and the depth g=0.2mm, both of which are positive tolerances, and the geometric center of the groove overlaps with the carrier board. The tooling base has a through hole at the corresponding position where the carrier board is placed. The width of the tooling block bump c=2.8mm, which is smaller than the width b (3mm) of the circuit chip. The tooling material is the same as the carrier board, Kovar 4J29.

[0059] (5) Figures 5 to 8 The figure shows the assembly process of the array integration tooling. The tooling of this patent can be applied in three scenarios: cutting after conductive glue array bonding, cutting after solder paste array welding, and cutting after prefabricated solder pad array welding. If the integration temperature is greater than 125°C, the high temperature resistance of the organic substrate and gel pad should be verified first. The use process of the tooling is as follows:

[0060] ① Place the carrier board. Figure 5 As shown, the metal carrier plate is placed in the array cavity of the tooling base by a manual or automatic material placing machine.

[0061] ② Adhesive / soldering material placement. If the adhesive process is used, the conductive glue is coated on the surface of the carrier board in an array using glue coating equipment; if the solder paste welding process is used, the solder paste is coated on the surface of the carrier board using screen printing technology; if the preformed solder sheet welding process is used, the solder sheet is placed on the surface of the carrier board manually or using an automatic material placing machine.

[0062] ③Circuit chip placement. Figure 6 As shown, align the through holes of the entire circuit board with the pin holes on the tooling base and place them in the tooling base, insert the pins into the positioning holes of the tooling base, place the tooling pressing block on the circuit board along the pin holes, and fix them with pins.

[0063] ④Send it into the oven for curing / reflow soldering. If the bonding process is adopted, send it into the oven to cure the adhesive; if the welding process is adopted, send it into the reflow furnace for soldering.

[0064] ⑤ Cutting and disassembling the board. After completing the array integration, remove the pins, disassemble the pressing block, cut the process ribs of the circuit sheet, discretize the micro-modules of the array, and then remove the micro-modules from the tooling base.

[0065] The above-mentioned embodiments only express the specific implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the protection scope of the present application. It should be pointed out that, for ordinary technicians in this field, several variations and improvements can be made without departing from the technical solution concept of the present application, and these all belong to the protection scope of the present application.

[0066] This background section is provided to generally present the context of the invention, and the work of the presently named inventors, the work to the extent described in this background section, and aspects of this section that did not constitute prior art at the time of application are neither explicitly nor implicitly admitted to be prior art to the present invention.

Claims

1. A method for array design and integration of a soft substrate circuit chip, characterized in that: include: Step S1: Perform micromodule design; Including the size of the carrier board, the size of the circuit chip and their relative position, the design output of the micromodule is used as the design input of the circuit chip layout and array integration tooling; Step S2: Conducting circuit board layout design; Based on the output of the micromodule design in step S1, conducting circuit board layout design, and iteratively optimizing the micromodule design scheme in step S1 in combination with arrayable integrated elements; Step S3: Based on the output of the circuit board layout design in step S2, the array integration tooling design is carried out, and the micromodule design scheme in step S1 and the circuit board layout design scheme in step S2 are optimized in combination with the tooling manufacturability; Step S4: realizing array integration of the circuit chip and the carrier board and cutting them into sections.

2. The array design and integration method of a soft substrate circuit chip according to claim 1, characterized in that: In step S1, the edge of the circuit chip and the edge of the carrier board overlap at least one place.

3. The array design and integration method of a soft substrate circuit chip according to claim 1, characterized in that: In the step S2, the circuit chip array spacing e is determined in combination with the relative positions of the circuit chip and the carrier board to ensure that the carrier board spacing f is greater than 4 mm.

4. The array design and integration method of a soft substrate circuit chip according to claim 1, characterized in that: The circuit chip process ribs are arranged at a position not bordering the pattern on the overlapping side of the circuit chip edge and the carrier board edge.

5. The array design and integration method of a soft substrate circuit chip according to claim 4, characterized in that: The pin holes are arranged at the outermost ribs of the circuit chip. The diameter of the pin holes shall not be less than 4mm, and the distance between the edge of the pin hole and the edge of the circuit chip substrate where the hole is located shall not be less than 1 / 2 of the hole diameter; the number of pin holes is at least 4, located in the four corners of the circuit chip layout and symmetrically centered. If more than four pin holes are required, the total number of pin holes should be a multiple of 4 and distributed at equal intervals along the outermost ribs of the circuit chip, and the distance between the pin holes shall not be less than 2 times the hole diameter.

6. The array design and integration method of a soft substrate circuit chip according to claim 1, characterized in that: The tooling in step S3 includes: a base, a pressure block, and a pin; the material of the tooling should be the same as that of the micromodule carrier, the pin has a negative tolerance, the pin hole has a positive tolerance, the processing tolerance is less than 0.01mm, the flatness is less than 0.05mm, and the surface roughness is less than 1.

6.

7. The array design and integration method of a soft substrate circuit chip according to claim 6, characterized in that: The tooling is provided with pin holes of the same size as the pin holes on the circuit board drawing; the pin holes at the pressing block and the circuit board are through holes, and the pin holes at the base are blind holes. After assembly, the pin ends should be at least 20 mm higher than the upper surface of the pressing block.

8. The array design and integration method of a soft substrate circuit chip according to claim 6, characterized in that: The depth g of the groove at the base for holding the micromodule carrier should be 1 / 3 to 1 / 2 of the thickness h of the micromodule carrier. The length and width of the base groove are 0.1 mm larger than the length and width of the carrier, and a positive tolerance is taken. The width c of the tooling pressing block is 0.1 mm smaller than the width b of the circuit chip on one side, and a high-temperature resistant gel should be attached to the bottom of the pressing block.

9. The array design and integration method of a soft substrate circuit chip according to claim 6, characterized in that: The single-side gap h between the inner contour of the base and the outer contour of the pressing block is less than 0.05 mm, a through hole is provided at the tooling base below the carrier plate, and the upper surface of the tooling pressing block should have a handle for separating it from the tooling base.

10. The array design and integration method of a soft substrate circuit chip according to claim 1, characterized in that: In step S4, the array integration of micromodules is achieved in the order of placing a carrier board, placing adhesive / soldering material, placing a circuit chip, inserting pins, oven curing / reflow soldering, and cutting and disassembling the board.

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