Power supply chip structure, power supply wafer structure, chip structure and forming methods of power supply chip structure, power supply wafer structure and chip structure

Abstract

The invention discloses a power supply chip structure, a power supply wafer structure, a chip structure and forming methods thereof. The power supply chip structure comprises a first substrate; the at least one coil layer is located on the first substrate, the coil layer comprises a dielectric layer and a coil located in the dielectric layer, and the coil is of an open-loop structure. The coil is manufactured in the power supply chip structure, induced current is generated in the coil by utilizing an electromagnetic induction principle, and then electric energy is provided for the device chip structure through bonding connection, so that the constraint of a traditional current circuit is eliminated, wireless use is realized, and convenience is brought to use of a product; meanwhile, the bandwidth and the data transmission efficiency can be effectively improved, and the current transmission energy consumption is reduced.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and in particular to a power chip structure, a power wafer structure, a chip structure and methods for forming the same. Background Art

[0002] In recent years, the advanced packaging method of introducing three-dimensional integrated circuits has received increasing research and attention because it can bond chips and devices of different functional types together in the vertical direction, thereby shortening the line connection, significantly increasing bandwidth and data transmission efficiency and reducing energy consumption.

[0003] Currently, the most common advanced packaging is to bond the logic chip and the memory chip together, but there is no technology for bonding the power supply. The current power supply currently used conducts current into the chip through external lines.

[0004] However, there are still many problems in the prior art in which power is transmitted through external lines. Summary of the invention

[0005] The technical problem solved by the present invention is to provide a power chip structure, a power wafer structure, a chip structure and their formation methods to increase bandwidth and data transmission efficiency and reduce current transmission energy consumption.

[0006] To solve the above problems, the technical solution of the present invention provides a power chip structure, including: a first substrate; at least one coil layer located on the first substrate, the coil layer includes a dielectric layer, and a coil located in the dielectric layer, and the coil is an open-loop structure.

[0007] Optionally, when the coil layer is multi-layer, each coil layer is stacked in sequence, and projections of inner regions enclosed by each coil layer in the dielectric layer on the first substrate overlap.

[0008] Optionally, it further includes: a metal core located on the first substrate, wherein the metal core penetrates an inner region of the coil enclosed in the dielectric layer.

[0009] Optionally, the material of the metal core includes: copper, aluminum, tungsten, cobalt, nickel or tantalum.

[0010] Optionally, the coil includes a first coil end and a second coil end opposite to each other, and the coil layer further includes: a first conductive plug and a second conductive plug located in the dielectric layer, and the first conductive plug is electrically connected to the first coil end, and the second conductive plug is electrically connected to the second coil end.

[0011] Optionally, when the coil layer is multi-layer, the coil layer located in the upper layer also includes: a plurality of first continuation conductive plugs and a plurality of second continuation conductive plugs located in the dielectric layer; the first continuation conductive plug in the coil layer located in the upper layer is electrically connected to the first conductive plug or the first continuation conductive plug in the coil layer located in the adjacent lower layer, so as to lead out the first coil ends of the coils in each layer; the second continuation conductive plug in the coil layer located in the upper layer is electrically connected to the second conductive plug or the second continuation conductive plug in the coil layer located in the adjacent lower layer, so as to lead out the second coil ends of the coils in each layer.

[0012] Optionally, it also includes: a wiring layer located on the topmost coil layer, wherein the wiring layer has a plurality of filter circuits, the coils in each layer are electrically connected to the filter circuits respectively, and the filter frequencies of the filter circuits electrically connected to the coils in each layer are different.

[0013] Optionally, the width of the coil ranges from 100 nanometers to 1000 nanometers.

[0014] Optionally, the shape of the coil includes: a spiral shape.

[0015] Correspondingly, the technical solution of the present invention also provides a method for forming a power chip structure, including: providing a power wafer, the power wafer including several power chip areas, the power chip areas having a first substrate; forming at least one coil layer on the first substrate, the coil layer including a dielectric layer, and a coil located in the dielectric layer, the coil being an open-loop structure; after forming the coil layer, dividing the several power chip areas of the power wafer to form several power chip structures.

[0016] Optionally, when the coil layer is multi-layer, each coil layer is stacked in sequence, and projections of inner regions enclosed by each coil layer in the dielectric layer on the first substrate overlap.

[0017] Optionally, after forming the coil layer, the method further includes: forming a metal core on the first substrate, wherein the metal core penetrates an inner area surrounded by the coil.

[0018] Optionally, the coil includes a first coil end and a second coil end opposite to each other, and the coil layer further includes: a first conductive plug and a second conductive plug located in the dielectric layer, and the first conductive plug is electrically connected to the first coil end, and the second conductive plug is electrically connected to the second coil end.

[0019] Optionally, the method for forming the coil layer includes: forming a first dielectric portion, the first dielectric portion having a first groove; forming the coil in the first groove; forming a second dielectric portion on the first dielectric portion, the first dielectric portion having two second grooves, the two second grooves respectively exposing the first coil end and the second coil end of the coil, the first dielectric portion and the second dielectric portion forming the dielectric layer; and forming the first conductive plug and the second conductive plug in the two second grooves respectively.

[0020] Optionally, when the coil layer is multi-layer, the coil layer located in the upper layer also includes: a plurality of first continuation conductive plugs and a plurality of second continuation conductive plugs located in the dielectric layer; the first continuation conductive plug in the coil layer located in the upper layer is electrically connected to the first conductive plug or the first continuation conductive plug in the coil layer located in the adjacent lower layer, so as to lead out the first coil ends of the coils in each layer; the second continuation conductive plug in the coil layer located in the upper layer is electrically connected to the second conductive plug or the second continuation conductive plug in the coil layer located in the adjacent lower layer, so as to lead out the second coil ends of the coils in each layer.

[0021] Optionally, after forming the coil layer, it also includes: forming a wiring layer on the coil layer located on the topmost layer, the wiring layer having a plurality of filter circuits, the coils in each layer are electrically connected to the filter circuits respectively, and the filter frequencies of the filter circuits electrically connected to the coils in each layer are different.

[0022] Correspondingly, the technical solution of the present invention also provides a power wafer structure, including: a power wafer, the power wafer including several power chip areas, the power chip areas having a first substrate; at least one coil layer located on the first substrate, the coil layer including a dielectric layer, and a coil located in the dielectric layer, the coil being an open-loop structure.

[0023] Correspondingly, the technical solution of the present invention also provides a method for forming a power wafer structure, including: providing a power wafer, the power wafer including several power chip areas, the power chip areas having a first substrate; forming at least one coil layer on the first substrate, the coil layer including a dielectric layer, and a coil located in the dielectric layer, the coil being an open-loop structure.

[0024] Correspondingly, the technical solution of the present invention also provides a chip structure, including: a power chip structure, the power chip structure including: a first substrate; at least one coil layer located on the first substrate, the coil layer including a dielectric layer, and a coil located in the dielectric layer, and the coil is an open-loop structure; a device chip structure, the device chip structure including: a second substrate; a plurality of device layers stacked in sequence located on the second substrate, and a plurality of device structures in the device layer; the power chip structure is bonded to the device chip structure so that each of the coils is electrically connected to at least one of the device structures to form a closed circuit.

[0025] Correspondingly, the technical solution of the present invention also provides a method for forming a chip structure, including: providing a power wafer, the power wafer including several power chip areas, the power chip areas having a first substrate; forming at least one coil layer on the first substrate, the coil layer including a dielectric layer and a coil located in the dielectric layer, and the coil is an open-loop structure; providing a device wafer, the device wafer including several device chip areas, the device chip areas having a second substrate; forming several layers of device layers stacked in sequence on the second substrate, the device layers having several device structures; bonding the power wafer and the device wafer so that the coil in each of the power chip areas is electrically connected to at least one of the device structures in the corresponding device chip area to form a closed circuit; after the bonding connection, segmenting the several power chip areas of the power wafer and the several device chip areas of the device wafer to form several chip structures.

[0026] Correspondingly, the technical solution of the present invention also provides a method for forming a chip structure, including: providing a power wafer, the power wafer including several power chip areas, the power chip areas having a first substrate; forming at least one coil layer on the first substrate, the coil layer including a dielectric layer and a coil located in the dielectric layer, and the coil is an open-loop structure; dividing the several power chip areas of the power wafer to form several power chip structures; providing a device wafer, the device wafer including several device chip areas, the device chip areas having a second substrate; forming several layers of device layers stacked in sequence on the second substrate, the device layers having several device structures; dividing the several device chip areas of the device wafer to form several device chip structures; bonding one power chip structure to one device chip structure to form one chip structure, the coil in the power chip structure in each chip structure is electrically connected to at least one device structure in the corresponding device chip structure to form a closed circuit.

[0027] Correspondingly, the technical solution of the present invention also provides a wafer structure, including: a power wafer, the power wafer including several power chip areas, the power chip areas having a first substrate; at least one coil layer located on the first substrate, the coil layer including a dielectric layer, and a coil located in the dielectric layer, the coil being an open-loop structure; a device wafer, the device wafer including several device chip areas, the device chip areas having a second substrate; several layers of device layers stacked in sequence located on the second substrate, the device layers having several device structures; the power wafer and the device wafer are bonded to each other so that the coil in each of the power chip areas is electrically connected to at least one of the device structures in the corresponding device chip area to form a closed circuit.

[0028] Correspondingly, the technical solution of the present invention also provides a method for forming a wafer structure, including: providing a power wafer, the power wafer including several power chip areas, the power chip areas having a first substrate; forming at least one coil layer on the first substrate, the coil layer including a dielectric layer and a coil located in the dielectric layer, and the coil is an open-loop structure; providing a device wafer, the device wafer including several device chip areas, the device chip areas having a second substrate; forming several layers of device layers stacked in sequence on the second substrate, the device layers having several device structures; bonding the power wafer and the device wafer so that the coil in each of the power chip areas is electrically connected to at least one of the device structures in the corresponding device chip area to form a closed circuit.

[0029] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0030] The power chip structure of the technical solution of the present invention includes: at least one coil layer located on the first substrate, the coil layer includes a dielectric layer, and a coil located in the dielectric layer, and the coil is an open-loop structure. By manufacturing the coil in the power chip structure, an induced current is generated in the coil using the principle of electromagnetic induction, and then the device chip structure is provided with power through bonding connection, thus getting rid of the constraints of traditional current lines, realizing wireless use to facilitate the use of products, and effectively increasing bandwidth and data transmission efficiency, and reducing current transmission energy consumption.

[0031] Furthermore, it also includes: a metal core located on the substrate, the metal core passing through the inner area surrounded by the coil in the dielectric layer. The metal core passing through the inner area surrounded by the coil can not only effectively enhance the electromagnetic induction effect, but also use the thermal conductivity of the metal to quickly remove the heat generated by the coil during the electromagnetic induction effect.

[0032] Furthermore, it also includes: a wiring layer located on the coil layer, wherein the wiring layer has a plurality of filter circuits, and the coils of each layer are electrically connected to the filter circuits respectively, and the filter frequencies of the filter circuits electrically connected to the coils of each layer are different. Since the filter frequencies of the filter circuits electrically connected to the coils of each layer are different, the magnetic field frequencies that can be received by the coils of each layer are different, and thus the currents generated by the coils of each layer are also different, so as to meet the requirements of different device structures.

[0033] In the method for forming the power chip structure of the technical solution of the present invention, at least one coil layer is formed on the first substrate, the coil layer includes a dielectric layer and a coil located in the dielectric layer, and the coil is an open-loop structure. By manufacturing the coil in the power chip structure, an induced current is generated in the coil using the principle of electromagnetic induction, and then the device chip structure is provided with power through bonding connection, thus getting rid of the constraints of traditional current lines, realizing wireless use to facilitate the use of products, and effectively increasing bandwidth and data transmission efficiency, and reducing current transmission energy consumption.

[0034] Furthermore, after forming the coil layer, the method further includes: forming a metal core on the first substrate, wherein the metal core penetrates the inner region surrounded by the coil. The metal core penetrates the inner region surrounded by the coil, which can not only effectively enhance the electromagnetic induction effect, but also utilize the thermal conductivity of the metal to quickly conduct away the heat generated by the coil during the electromagnetic induction effect.

[0035] Furthermore, after the coil layer is formed, a wiring layer is formed on the coil layer, wherein the wiring layer has a plurality of filter circuits, and the coils of each layer are electrically connected to the filter circuits, respectively, and the filter frequencies of the filter circuits electrically connected to the coils of each layer are different. In this embodiment, since the filter frequencies of the filter circuits electrically connected to the coils of each layer are different, the magnetic field frequencies that can be received by the coils of each layer are different, and thus the currents generated by the coils of each layer are also different, so as to meet the requirements of different device structures.

[0036] In the chip structure of the technical solution of the present invention, the power chip structure includes: at least one coil layer located on the first substrate, the coil layer includes a dielectric layer, and a coil located in the dielectric layer, and the coil is an open-loop structure. By manufacturing the coil in the power chip structure, an induced current is generated in the coil using the principle of electromagnetic induction, and then the device chip structure is provided with power through bonding connection, thus getting rid of the constraints of traditional current lines, realizing wireless use to facilitate the use of products, and effectively increasing bandwidth and data transmission efficiency, and reducing current transmission energy consumption.

[0037] In the method for forming a chip structure of the technical solution of the present invention, at least one coil layer is formed on the first substrate of the power chip structure, the coil layer includes a dielectric layer and a coil located in the dielectric layer, and the coil is an open-loop structure. By manufacturing the coil in the power chip structure, an induced current is generated in the coil using the principle of electromagnetic induction, and then the device chip structure is provided with electrical energy through bonding connection, thus getting rid of the constraints of traditional current lines, realizing wireless use to facilitate the use of products, and effectively increasing bandwidth and data transmission efficiency, and reducing current transmission energy consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figures 1 to 12 It is a schematic diagram of the structure of each step of the method for forming a power chip structure in an embodiment of the present invention;

[0039] Fig.13 is a schematic diagram of the structure of a chip in an embodiment of the present invention;

[0040] Figure 14 to Figure 15 Schematic diagram of the structure of the wafer in the embodiment of the present invention. DETAILED DESCRIPTION

[0041] As described in the background art, there are still many problems in the prior art of transmitting power through external lines, which will be described in detail below.

[0042] At present, chips are integrated on circuit boards, and the current is conducted into the chip through external lines. On the one hand, the use of the product is restricted by the location of the power socket and the length of the line. On the other hand, the length of the external line is generally in the order of meters, which increases the power consumption of current transmission. The wireless transmission used in the market only generates alternating current through the coil and then transmits the current to the chip circuit. The line length is also in the order of millimeters, and there is still a large transmission loss.

[0043] On this basis, the present invention provides a power chip structure, a power wafer structure, a chip structure and their formation methods. The coil is made in the power chip structure, and an induced current is generated in the coil using the principle of electromagnetic induction. Then, electrical energy is provided to the device chip structure through bonding connection, thereby getting rid of the constraints of traditional current lines and realizing wireless use to facilitate the use of products. At the same time, it can effectively increase bandwidth and data transmission efficiency, and reduce current transmission energy consumption.

[0044] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0045] Figures 1 to 12 It is a schematic diagram of the structure of each step of the method for forming a power chip structure in an embodiment of the present invention.

[0046] Please refer to Figure 1 and Figure 2 , Figure 2 yes Figure 1 The enlarged schematic diagram of the cross section along the AA line in FIG. 1 provides a power wafer 100 . The power wafer 100 includes a plurality of power chip regions 101 . The power chip regions 101 have a first substrate 102 .

[0047] In this embodiment, several of the power chip areas 101 in the power wafer 100 are subsequently used to manufacture a power chip structure thereon, and there are cutting lines (not shown) between each of the power chip areas 101. After the power chip structure is manufactured, the power wafer 100 will be cut along the cutting lines, thereby separating the several power chip structures from each other.

[0048] The material of the first substrate 102 includes silicon, silicon germanium, silicon carbide, silicon on insulator (SOI), or germanium on insulator (GOI).

[0049] In this embodiment, the material of the first substrate 102 is silicon.

[0050] In this embodiment, after providing the power wafer 100, the method further includes: forming at least one coil layer on the first substrate 102. Taking the formation of four coil layers on the first substrate 102 as an example, please refer to Figures 3 to 6 .

[0051] Please refer to Figure 3 and Figure 4 , Figure 4 yes Figure 3 In the cross-sectional view along line BB, a first dielectric portion 103 is formed, and a first groove 104 is provided in the first dielectric portion 103 .

[0052] In this embodiment, the method for forming the first dielectric portion 103 includes: forming an initial first dielectric portion (not shown) on the first substrate 102; forming a first patterned layer (not shown) on the initial first dielectric portion, wherein the first patterned layer exposes a portion of the top surface of the initial first dielectric portion; using the first patterned layer as a mask, etching the initial first dielectric portion to form the first dielectric portion 103, wherein the first dielectric portion 103 has the first groove 104 therein.

[0053] Please refer to Figure 5 and Figure 6 , Figure 6 yes Figure 5 In the cross-sectional schematic diagram along line CC, the coil 105 is formed in the first groove 104.

[0054] In this embodiment, the method for forming the coil 105 in the first groove 104 includes: forming a coil material layer (not shown) in the first groove 104 and on the surface of the first dielectric portion 103; and flattening the first coil material layer until the top surface of the first dielectric portion 103 is exposed to form the coil 105.

[0055] In this embodiment, the process of planarizing the first coil material layer adopts a chemical mechanical polishing process.

[0056] In this embodiment, the coil 105 is an open-loop structure, and the coil 105 includes a first coil end 105 a and a second coil end 105 b that are opposite to each other.

[0057] In this embodiment, the coil 105 is formed in a spiral shape.

[0058] In this embodiment, the width of the coil 105 is in the range of 100 nanometers to 1000 nanometers.

[0059] Please refer to Figure 7 , Figure 7 and Figure 6 a second dielectric portion 106 is formed on the first dielectric portion 103, the first dielectric portion 106 having two second grooves 107, the two second grooves 107 respectively expose the first coil end 105a and the second coil end 105b of the coil.

[0060] In this embodiment, the method for forming the second dielectric portion 106 includes: forming an initial second dielectric portion (not shown) on the first dielectric portion 103; forming a second patterned layer (not shown) on the initial second dielectric portion, wherein the second patterned layer exposes a portion of the top surface of the initial second dielectric portion; using the second patterned layer as a mask, etching the initial second dielectric portion to form the second dielectric portion 106, wherein the second dielectric portion 106 has two second grooves 107.

[0061] In this embodiment, the first dielectric portion 103 and the second dielectric portion 106 form a dielectric layer 108 in the coil layer.

[0062] Please refer to Figure 8 , the first conductive plug 109 and the second conductive plug 110 are respectively formed in the two second trenches 107 .

[0063] In this embodiment, the method for forming the first conductive plug 109 and the second conductive plug 110 in the two second trenches 107 respectively includes: forming a conductive plug material layer (not shown) in the second trench 107 and on the second dielectric portion 106; and planarizing the conductive plug material layer until the top surface of the second dielectric portion 106 is exposed, thereby forming the first conductive plug 109 and the second conductive plug 110.

[0064] In this embodiment, the process of planarizing the conductive plug material layer adopts a chemical mechanical polishing process.

[0065] In this embodiment, the first conductive plug 109 is electrically connected to the first coil end 105 a , and the second conductive plug 110 is electrically connected to the second coil end 105 b .

[0066] At this point, the first coil layer (ie, the coil layer at the bottom layer) is formed.

[0067] Please refer to Fig. 9 , three layers of coil layers stacked in sequence are formed on the first coil layer.

[0068] In this embodiment, the coil layer located in the upper layer (i.e., the coil layer in the second layer, the coil layer in the third layer, and the coil layer in the fourth layer) has the same other structures as the coil layer in the first layer, except that: the coil layer located in the upper layer also includes: a plurality of first continuation conductive plugs 111 and a plurality of second continuation conductive plugs 112 located in the dielectric layer 108; the first continuation conductive plug 111 in the coil layer located in the upper layer is electrically connected to the first conductive plug 109 or the first continuation conductive plug 111 in the coil layer located in the adjacent lower layer, so as to lead out the first coil end 105a of the coil 105 in each layer; the second continuation conductive plug 112 in the coil layer located in the upper layer is electrically connected to the second conductive plug 110 or the second continuation conductive plug 112 in the coil layer located in the adjacent lower layer, so as to lead out the second coil end 105b of the coil 105 in each layer.

[0069] It should be noted that, in the present embodiment, with respect to the coil layer of the first layer and the coil layer of the second layer, the coil layer of the second layer is the coil layer located at the upper layer, and the coil layer of the first layer is the coil layer located at the adjacent lower layer; with respect to the coil layer of the second layer and the coil layer of the third layer, the coil layer of the third layer is the coil layer located at the upper layer, and the coil layer of the second layer is the coil layer located at the adjacent lower layer, and so on.

[0070] In this embodiment, since there are only the first conductive plug 109 and the second conductive plug 110 in the coil layer of the first layer, the first continuation conductive plug 111 in the coil layer of the second layer is only electrically connected to the first conductive plug 109 in the coil layer of the first layer, and the second continuation conductive plug 112 in the coil layer of the second layer is only electrically connected to the second conductive plug 110 in the coil layer of the first layer.

[0071] The coil layer of the second layer has the first conductive plug 109, the second conductive plug 110, the first extended conductive plug 111 and the second extended conductive plug 112 at the same time. Therefore, the coil layer of the third layer needs to add two first extended conductive plugs 111 and two second extended conductive plugs 112, of which one first extended conductive plug 111 needs to be electrically connected to the first conductive plug 109 in the coil layer of the second layer, and the other first extended conductive plug 111 needs to be electrically connected to the first extended conductive plug 111 in the coil layer of the second layer; one second extended conductive plug 112 needs to be electrically connected to the second conductive plug 110 in the coil layer of the second layer, and the other second extended conductive plug 112 needs to be electrically connected to the second extended conductive plug 112 in the coil layer of the second layer. The same applies to the coil layer of the third layer and the coil layer of the fourth layer.

[0072] In this embodiment, the formation process of the first dielectric portion 103 and the coil 105 of the second coil layer, the third coil layer and the fourth coil layer is consistent with the formation process of the first dielectric portion 103 and the coil 105 located in the first coil layer.

[0073] In this embodiment, the formation process of the second dielectric portion 106, the first conductive plug 109 and the second conductive plug 110 of the second coil layer, the third coil layer and the fourth coil layer is consistent with the formation process of the second dielectric portion 106, the first conductive plug 109 and the second conductive plug 110 located in the first coil layer, except that: since the first dielectric portion 103 and the second dielectric portion 106 of the second coil layer, the third coil layer and the fourth coil layer also have the The first continuation conductive plug 111 and the second continuation conductive plug 112, therefore, in the process of forming the second groove 107, it is also necessary to form a third groove (not marked) required for the first continuation conductive plug 111 and the second continuation conductive plug 112 in the first dielectric portion 103 and the second dielectric portion 106, and in the process of filling the second groove 109 with the conductive plug material layer, the third groove is also filled, and after the planarization treatment, the first continuation conductive plug 111 and the second continuation conductive plug 112 are formed at the same time.

[0074] In this embodiment, the coil layers are stacked in sequence, and the projections of the inner regions enclosed by the coils of each layer in the dielectric layer 108 on the first substrate 102 overlap.

[0075] It should be noted that, in this embodiment, as the number of coil layers increases, the positions of adjacent coil layers are staggered to facilitate the lead-out of the conductive plug.

[0076] Please refer to Fig.10 After the coil layer is formed, a metal core 113 is formed on the first substrate 102 , and the metal core 113 penetrates the inner area surrounded by the coil 105 .

[0077] In this embodiment, the metal core 113 runs through the internal area surrounded by the coil 105, which can not only effectively enhance the electromagnetic induction effect, but also use the thermal conductivity of the metal to quickly remove the heat generated by the coil 105 during the electromagnetic induction effect.

[0078] In this embodiment, the method for forming the metal core 113 includes: forming a third patterning (not shown) on the coil layer located on the top layer, the third patterning layer exposing a portion of the top surface of the coil layer; using the third patterning layer as a mask, etching each layer of the coil layer to form a metal core opening (not shown); and forming the metal core 113 in the metal core opening.

[0079] In this embodiment, the material of the metal core 113 is copper; in other embodiments, the material of the coil may also be aluminum, tungsten, cobalt, nickel or tantalum.

[0080] Please refer to Fig.11 After the coil layer is formed, a wiring layer 114 is formed on the coil layer. The wiring layer 114 has a plurality of filter circuits (not shown). The coils 105 in each layer are electrically connected to the filter circuits, respectively, and the filter frequencies of the filter circuits to which the coils in each layer are electrically connected are different.

[0081] In this embodiment, since the filtering frequencies of the filtering circuits electrically connected to the coils 105 at each layer are different, the magnetic field frequencies that can be received by the coils 105 at each layer are different, and thus the currents generated by the coils 105 at each layer are also different to meet the requirements of different device structures.

[0082] Please refer to Fig.12 After the coil layer is formed, the power chip regions 101 of the power wafer 100 are divided to form a plurality of power chip structures 115 .

[0083] In this embodiment, the coil 105 is manufactured in the power chip structure 115, and the electromagnetic induction principle is used to generate an induced current in the coil 105, and then the device chip structure is provided with power through a bonding connection, thereby getting rid of the constraints of traditional current lines and realizing wireless use to facilitate the use of the product. At the same time, it can effectively increase the bandwidth and data transmission efficiency, and reduce the current transmission energy consumption.

[0084] In this embodiment, the dividing process of the plurality of power chip regions 101 of the power wafer 100 includes one or more of a laser cutting process and a knife cutting process.

[0085] Correspondingly, an embodiment of the present invention further provides a power chip structure, please continue to refer to Fig.11 , including: a first substrate 102; at least one coil layer located on the first substrate 102, the coil layer including a dielectric layer 108, and a coil 105 located in the dielectric layer 108, and the coil 105 is an open-loop structure.

[0086] In this embodiment, when the coil layers are multiple layers, the coil layers are stacked in sequence, and the projections of the inner regions enclosed by the coils 105 of each layer in the dielectric layer 108 on the first substrate 102 overlap.

[0087] In this embodiment, it further includes: a metal core 113 located on the first substrate 102, and the metal core 113 penetrates the inner region surrounded by the coil 105 in the dielectric layer 108. The metal core 113 penetrates the inner region surrounded by the coil 105, which can not only effectively enhance the electromagnetic induction effect, but also use the thermal conductivity of metal to quickly conduct away the heat generated by the coil during the electromagnetic induction effect.

[0088] In this embodiment, the material of the metal core 113 is copper; in other embodiments, the material of the metal core may also be aluminum, tungsten, cobalt, nickel or tantalum.

[0089] In this embodiment, the coil 105 includes a first coil end 105a and a second coil end 105b opposite to each other, and the coil layer also includes: a first conductive plug 109 and a second conductive plug 110 located in the dielectric layer 108, and the first conductive plug 109 is electrically connected to the first coil end 105a, and the second conductive plug 110 is electrically connected to the second coil end 105b.

[0090] In this embodiment, when the coil layer is multi-layer, the coil layer located in the upper layer further includes: a plurality of first continuation conductive plugs 111 and a plurality of second continuation conductive plugs 112 located in the dielectric layer 108; the first continuation conductive plug 111 in the coil layer located in the upper layer is electrically connected to the first conductive plug 109 or the first continuation conductive plug 111 in the coil layer located in the adjacent lower layer, so as to lead out the first coil end 105a of the coils in each layer; the second continuation conductive plug 112 in the coil layer located in the upper layer is electrically connected to the second conductive plug 110 or the second continuation conductive plug 112 in the coil layer located in the adjacent lower layer, so as to lead out the second coil end 105b of the coils in each layer.

[0091] In this embodiment, it also includes: a wiring layer 114 located on the topmost coil layer, wherein the wiring layer 114 has a plurality of filter circuits, and the coils 105 of each layer are electrically connected to the filter circuits respectively, and the filter frequencies of the filter circuits electrically connected to the coils 105 of each layer are different. Since the filter frequencies of the filter circuits electrically connected to the coils 105 of each layer are different, the magnetic field frequencies that can be received by the coils 105 of each layer are different, and thus the currents generated by the coils 105 of each layer are also different, so as to meet the requirements of different device structures.

[0092] In this embodiment, the width of the coil 105 is in the range of 100 nanometers to 1000 nanometers.

[0093] In this embodiment, the coil 105 is in a spiral shape.

[0094] Correspondingly, the embodiment of the present invention also provides a power wafer structure, please continue to refer to Figure 1 and Fig.11 The invention comprises: a power wafer 100, wherein the power wafer 100 comprises a plurality of power chip regions 101, wherein the power chip regions 101 have a first substrate 102; at least one coil layer located on the first substrate 102, wherein the coil layer comprises a dielectric layer 108, and a coil 105 located in the dielectric layer 108, wherein the coil 105 is an open-loop structure.

[0095] Correspondingly, the present invention also provides a method for forming a power wafer structure, please continue to refer to Figures 1 to 11 , including: providing a power wafer 100, the power wafer 100 includes a plurality of power chip areas 101, the power chip area 101 has a first substrate 102; forming at least one coil layer on the first substrate 102, the coil layer includes a dielectric layer 108, and a coil 105 located in the dielectric layer 108, and the coil 105 is an open-loop structure.

[0096] Fig.13 Schematic diagram of the chip structure in an embodiment of the present invention.

[0097] Correspondingly, a chip structure is also provided in the embodiment of the present invention, please refer to Fig.13 , including: a power chip structure 115, the power chip structure 115 includes: a first substrate 102; at least one coil layer located on the first substrate 102, the coil layer includes a dielectric layer 108, and a coil 105 located in the dielectric layer 108, and the coil 105 is an open-loop structure; a device chip structure 200, the device chip structure 200 includes: a second substrate 201; a plurality of device layers 202 stacked in sequence located on the second substrate 201, and a plurality of device structures (not marked) are provided in the device layer 202; the power chip structure 115 is bonded to the device chip structure 200 so that each of the coils 105 is electrically connected to at least one of the device structures to form a closed circuit.

[0098] In this embodiment, the coil 105 is fabricated in the power chip structure 115, and the electromagnetic induction principle is used to generate an induced current in the coil 105, and then the device chip structure 200 is provided with power through bonding connection, thereby getting rid of the constraints of traditional current lines, realizing wireless use to facilitate the use of products, and effectively increasing bandwidth and data transmission efficiency, and reducing current transmission energy consumption.

[0099] Accordingly, an embodiment of the present invention further provides a method for forming a chip structure, please continue to refer to Fig.13, including: providing a power wafer 100, the power wafer 100 including a plurality of power chip regions 101, the power chip region 101 having a first substrate 102; forming at least one coil layer on the first substrate 102, the coil layer including a dielectric layer 108 and a coil 105 located in the dielectric layer 108, the coil 105 being an open-loop structure; providing a device wafer (not shown), the device wafer including a plurality of device chip regions, the device chip region having a second substrate 201; forming a plurality of device layers 202 stacked in sequence on the second substrate 201, the device layer having a plurality of device structures; bonding the power wafer 100 and the device wafer so that the coil 105 in each of the power chip regions 101 is electrically connected to at least one of the device structures in the corresponding device chip region to form a closed circuit; after bonding, segmenting the plurality of power chip regions 101 of the power wafer 100 and the plurality of device chip regions of the device wafer to form a plurality of chip structures.

[0100] In this embodiment, the coil 105 is manufactured in the power chip structure 115, and the electromagnetic induction principle is used to generate an induced current in the coil 105, and then the device chip structure is provided with power through a bonding connection, thereby getting rid of the constraints of traditional current lines and realizing wireless use to facilitate the use of the product. At the same time, it can effectively increase the bandwidth and data transmission efficiency, and reduce the current transmission energy consumption.

[0101] Correspondingly, another embodiment of the present invention further provides a method for forming a chip structure, please continue to refer to Fig.13, including: providing a power wafer 100, the power wafer 100 including a plurality of power chip regions 101, the power chip region 101 having a first substrate 102; forming at least one coil layer on the first substrate 102, the coil layer including a dielectric layer 108, and a coil 105 located in the dielectric layer 108, the coil 105 being an open-loop structure; dividing the plurality of power chip regions 101 of the power wafer 100 to form a plurality of power chip structures 115; providing a device wafer (not shown), the device wafer including a plurality of device chip regions, the device chip regions It has a second substrate 201; a plurality of device layers 202 stacked in sequence are formed on the second substrate 201, and a plurality of device structures are provided in the device layer 202; a plurality of device chip regions of the device wafer are segmented to form a plurality of device chip structures 200; a power chip structure 115 is bonded to a device chip structure 200 to form a chip structure, and the coil 105 in the power chip structure 115 in each chip structure is electrically connected to at least one device structure in the corresponding device chip structure 200 to form a closed circuit.

[0102] In this embodiment, the coil 105 is manufactured in the power chip structure 115, and an induced current is generated in the coil by utilizing the principle of electromagnetic induction, and then electrical energy is provided to the device chip structure 200 through bonding connection, thereby getting rid of the constraints of traditional current lines and realizing wireless use to facilitate the use of the product. At the same time, it can effectively increase the bandwidth and data transmission efficiency, and reduce the energy consumption of current transmission.

[0103] Figure 14 to Figure 15 Schematic diagram of the structure of the wafer in the embodiment of the present invention.

[0104] Accordingly, a wafer structure is also provided in the embodiment of the present invention, please continue to refer to Fig.13 Combined with reference 14 and Fig.15 , Fig.15 yes Fig.14 Schematic diagram of the structure of the middle line DD, Fig.13 yes Fig.14The schematic diagram of the structure along the EE line in the figure includes: a power wafer 100, wherein the power wafer 100 includes a plurality of power chip areas 101, wherein the power chip area 101 has a first substrate 102; at least one coil layer located on the first substrate 102, wherein the coil layer includes a dielectric layer 108, and a coil 105 located in the dielectric layer 108, wherein the coil 105 is an open-loop structure; a device wafer 300, wherein the device wafer 300 includes a plurality of device chip areas (not shown), wherein the device chip area has a second substrate 201; a plurality of device layers 202 stacked in sequence located on the second substrate 201, wherein the device layers have a plurality of device structures; the power wafer 100 and the device wafer 300 are bonded and connected so that the coil 105 in each of the power chip areas 101 is electrically connected to at least one of the device structures in the corresponding device chip area to form a closed circuit.

[0105] Accordingly, the present invention also provides a method for forming a wafer structure, please continue to refer to Figures 13 to 15 , including: providing a power wafer 100, the power wafer 100 including a plurality of power chip regions 101, the power chip regions 101 having a first substrate 102; forming at least one coil layer on the first substrate 102, the coil layer including a dielectric layer 108, and a coil 105 located in the dielectric layer 108, the coil 105 being an open-loop structure; providing a device wafer 300, the device wafer 300 including a plurality of device chip regions, the device chip regions having a second substrate 201; forming a plurality of device layers 202 stacked in sequence on the second substrate 201, the device layer 202 having a plurality of device structures; bonding the power wafer 100 and the device wafer 300 so that the coil 105 in each of the power chip regions 101 is electrically connected to at least one of the device structures in the corresponding device chip region to form a closed circuit.

[0106] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A power chip structure, characterized in that: include: a first substrate; At least one coil layer is located on the first substrate, the coil layer includes a dielectric layer and a coil located in the dielectric layer, and the coil is an open-loop structure.

2. The power chip structure according to claim 1, characterized in that: When the coil layer is multi-layer, each coil layer is stacked in sequence, and the projections of the inner regions enclosed by each coil layer in the dielectric layer on the first substrate overlap.

3. The power chip structure according to claim 1 or 2, characterized in that: Also includes: A metal core is located on the first substrate, and the metal core penetrates an inner region of the coil enclosed in the dielectric layer.

4. The power chip structure according to claim 3, characterized in that: The material of the metal core includes: copper, aluminum, tungsten, cobalt, nickel or tantalum.

5. The power chip structure according to claim 1, characterized in that: The coil includes a first coil end and a second coil end opposite to each other, and the coil layer also includes: a first conductive plug and a second conductive plug located in the dielectric layer, wherein the first conductive plug is electrically connected to the first coil end, and the second conductive plug is electrically connected to the second coil end.

6. The power chip structure according to claim 5, characterized in that: When the coil layer is multi-layer, the coil layer located in the upper layer also includes: a plurality of first continuation conductive plugs and a plurality of second continuation conductive plugs located in the dielectric layer; the first continuation conductive plug in the coil layer located in the upper layer is electrically connected to the first conductive plug or the first continuation conductive plug in the coil layer located in the adjacent lower layer, so as to lead out the first coil ends of the coils in each layer; the second continuation conductive plug in the coil layer located in the upper layer is electrically connected to the second conductive plug or the second continuation conductive plug in the coil layer located in the adjacent lower layer, so as to lead out the second coil ends of the coils in each layer.

7. The power chip structure according to claim 1, characterized in that: Also includes: The wiring layer located on the topmost coil layer has a plurality of filter circuits in the wiring layer. The coils in each layer are electrically connected to the filter circuits respectively, and the filter frequencies of the filter circuits electrically connected to the coils in each layer are different.

8. The power chip structure according to claim 1, characterized in that: The width of the coil ranges from 100 nanometers to 1000 nanometers.

9. The power chip structure according to claim 1, characterized in that: The shape of the coil includes: a spiral shape.

10. A method for forming a power chip structure, characterized in that: include: Providing a power wafer, the power wafer comprising a plurality of power chip regions, the power chip regions having a first substrate; forming at least one coil layer on the first substrate, wherein the coil layer comprises a dielectric layer and a coil located in the dielectric layer, and the coil is an open-loop structure; After the coil layer is formed, a plurality of the power chip regions of the power wafer are divided to form a plurality of the power chip structures.

11. The method for forming a power chip structure according to claim 10, wherein: When the coil layer is multi-layer, each coil layer is stacked in sequence, and the projections of the inner regions enclosed by each coil layer in the dielectric layer on the first substrate overlap.

12. The method for forming a power chip structure according to claim 10 or 11, characterized in that: After forming the coil layer, the method further includes: forming a metal core on the first substrate, wherein the metal core penetrates an inner area surrounded by the coil.

13. The method for forming a power chip structure according to claim 10, wherein: The coil includes a first coil end and a second coil end opposite to each other, and the coil layer also includes: a first conductive plug and a second conductive plug located in the dielectric layer, wherein the first conductive plug is electrically connected to the first coil end, and the second conductive plug is electrically connected to the second coil end.

14. The method for forming a power chip structure according to claim 13, wherein: The method for forming the coil layer includes: forming a first dielectric portion, wherein the first dielectric portion has a first groove; forming the coil in the first groove; forming a second dielectric portion on the first dielectric portion, wherein the first dielectric portion has two second grooves, wherein the two second grooves respectively expose the first coil end and the second coil end of the coil, and the first dielectric portion and the second dielectric portion form the dielectric layer; and forming the first conductive plug and the second conductive plug in the two second grooves respectively.

15. The method for forming a power chip structure according to claim 13, wherein: When the coil layer is multi-layer, the coil layer located in the upper layer also includes: a plurality of first continuation conductive plugs and a plurality of second continuation conductive plugs located in the dielectric layer; the first continuation conductive plug in the coil layer located in the upper layer is electrically connected to the first conductive plug or the first continuation conductive plug in the coil layer located in the adjacent lower layer, so as to lead out the first coil ends of the coils in each layer; the second continuation conductive plug in the coil layer located in the upper layer is electrically connected to the second conductive plug or the second continuation conductive plug in the coil layer located in the adjacent lower layer, so as to lead out the second coil ends of the coils in each layer.

16. The method for forming a power chip structure according to claim 10, wherein: After forming the coil layer, it also includes: forming a wiring layer on the coil layer located at the top layer, wherein the wiring layer has a plurality of filter circuits, the coils in each layer are electrically connected to the filter circuits respectively, and the filter frequencies of the filter circuits electrically connected to the coils in each layer are different.

17. A power wafer structure, characterized in that: include: A power wafer, the power wafer comprising a plurality of power chip regions, the power chip regions having a first substrate; At least one coil layer is located on the first substrate, the coil layer includes a dielectric layer and a coil located in the dielectric layer, and the coil is an open-loop structure.

18. A method for forming a power wafer structure, characterized in that: include: Providing a power wafer, the power wafer comprising a plurality of power chip regions, the power chip regions having a first substrate; At least one coil layer is formed on the first substrate, wherein the coil layer includes a dielectric layer and a coil located in the dielectric layer, and the coil is an open-loop structure.

19. A chip structure, characterized in that: include: A power chip structure, the power chip structure comprising: a first substrate; at least one coil layer located on the first substrate, the coil layer comprising a dielectric layer and a coil located in the dielectric layer, the coil being an open-loop structure; A device chip structure, the device chip structure comprising: a second substrate; A plurality of device layers stacked in sequence and located on the second substrate, wherein the device layers have a plurality of device structures; The power chip structure is bonded to the device chip structure so that each of the coils is electrically connected to at least one of the device structures to form a closed circuit.

20. A method for forming a chip structure, characterized in that: include: Providing a power wafer, the power wafer comprising a plurality of power chip regions, the power chip regions having a first substrate; forming at least one coil layer on the first substrate, wherein the coil layer comprises a dielectric layer and a coil located in the dielectric layer, and the coil is an open-loop structure; Providing a device wafer, wherein the device wafer includes a plurality of device chip regions, and the device chip regions have a second substrate; forming a plurality of device layers stacked in sequence on the second substrate, wherein the device layers have a plurality of device structures; Bonding the power wafer and the device wafer so that the coil in each power chip region is electrically connected to at least one device structure in the corresponding device chip region to form a closed circuit; After the bonding, the power chip regions of the power wafer and the device chip regions of the device wafer are divided to form a plurality of chip structures.

21. A method for forming a chip structure, characterized in that: include: Providing a power wafer, the power wafer comprising a plurality of power chip regions, the power chip regions having a first substrate; forming at least one coil layer on the first substrate, wherein the coil layer comprises a dielectric layer and a coil located in the dielectric layer, and the coil is an open-loop structure; Segmenting the plurality of power chip regions of the power wafer to form a plurality of power chip structures; Providing a device wafer, wherein the device wafer includes a plurality of device chip regions, and the device chip regions have a second substrate; forming a plurality of device layers stacked in sequence on the second substrate, wherein the device layers have a plurality of device structures; Segmenting the plurality of device chip regions of the device wafer to form a plurality of device chip structures; A power chip structure is bonded to a device chip structure to form a chip structure, and the coil in the power chip structure in each chip structure is electrically connected to at least one device structure in the corresponding device chip structure to form a closed circuit.

22. A wafer structure, characterized in that: include: A power wafer, the power wafer comprising a plurality of power chip regions, the power chip regions having a first substrate; at least one coil layer located on the first substrate, the coil layer comprising a dielectric layer and a coil located in the dielectric layer, the coil being an open-loop structure; A device wafer, wherein the device wafer comprises a plurality of device chip regions, and the device chip regions have a second substrate; A plurality of device layers stacked in sequence and located on the second substrate, wherein the device layers have a plurality of device structures; The power wafer and the device wafer are bonded and connected so that the coil in each power chip area is electrically connected to at least one device structure in the corresponding device chip area to form a closed circuit.

23. A method for forming a wafer structure, characterized in that: include: Providing a power wafer, the power wafer comprising a plurality of power chip regions, the power chip regions having a first substrate; forming at least one coil layer on the first substrate, wherein the coil layer comprises a dielectric layer and a coil located in the dielectric layer, and the coil is an open-loop structure; Providing a device wafer, wherein the device wafer includes a plurality of device chip regions, and the device chip regions have a second substrate; forming a plurality of device layers stacked in sequence on the second substrate, wherein the device layers have a plurality of device structures; The power wafer and the device wafer are bonded and connected so that the coil in each power chip area is electrically connected to at least one device structure in the corresponding device chip area to form a closed circuit.

Images