MIM capacitor and manufacturing method thereof

Abstract

According to the MIM capacitor and the manufacturing method thereof provided by the invention, the lower polar plate and the lower metal interconnection line are formed by adopting the same metal layer, the thickness of a chip can be reduced, and the MIM capacitor can be in a folded structure at the three-dimensional structure pattern by utilizing a plurality of concave parts and a plurality of convex parts in the three-dimensional structure pattern of the lower polar plate, so that the thickness of the chip can be reduced. Therefore, compared with a conventional plane MIM capacitor structure, under the condition of the same total capacitance value, the area of the MIM capacitor can be greatly reduced, the area of a whole chip is further reduced, and higher cost performance is achieved.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor device manufacturing, and in particular to a MIM capacitor and a manufacturing method thereof. Background Art

[0002] Capacitors are a commonly used passive electronic device in integrated circuits (such as radio frequency circuits, mixed signal circuits, etc.), usually including metal oxide semiconductor (MOS) capacitors, PN junction capacitors, polysilicon-insulator-polysilicon (PIP) capacitors and metal-insulator-metal (MIM) capacitors.

[0003] Among them, MIM capacitor is a flat-plate capacitor, which is generally formed on a metal interconnect structure in the back-end of line (BEOL). It consists of two layers of metal as upper and lower electrodes, with an insulating dielectric layer (Dielectric) in the middle. The metal manufacturing process of the upper and lower electrodes is copper, aluminum, etc. that is compatible with the metal interconnection process.

[0004] Please refer to Figure 1 , an existing method for manufacturing MIM capacitors is to form the MIM capacitor in the metal interlayer dielectric layer IDL_n between two metal interconnect layers Metal_n-1 and Metal_n, which needs to be realized through a series of process steps such as lower electrode metal deposition, insulating dielectric layer CILD deposition, upper electrode metal deposition, upper electrode CTM lithography and etching, and lower electrode CBM lithography and etching. The upper electrode CTM and lower plate CBM of the MIM capacitor are led to Metal_n through corresponding through holes Via_n. Obviously, this method requires two additional masks (i.e., a mask for making the upper electrode and a mask for making the lower electrode), and because the manufactured MIM capacitor is a planar capacitor structure, when the capacitance value of the MIM capacitor is required to be large, based on the relationship that the capacitance value is proportional to the area, the area of ​​the MIM capacitor required is also large, which will expand the area of ​​the entire chip.

[0005] Please refer to Figure 2 Another existing method for manufacturing MIM capacitors is to use the metal interconnect layer Metal_n-1 to form the lower electrode, and then go through a series of process steps such as CIDL deposition of the insulating dielectric layer, metal deposition of the upper electrode, CTM lithography and etching of the upper electrode. This method can save a photomask and help reduce the thickness of the chip because the lower electrode and the metal interconnect layer Metal_n-1 of the MIM capacitor are realized by the same metal layer. However, the MIM capacitor manufactured by this method is a planar capacitor structure. When the capacitance value of the MIM capacitor is required to be large, based on the relationship that the capacitance value is proportional to the area, the area of ​​the MIM capacitor required is also large, which will expand the area of ​​the entire chip.

[0006] Therefore, there is an urgent need for a MIM capacitor and a manufacturing method thereof, which can obtain a larger capacitance value while helping to reduce the chip area and thickness and reduce production costs. Summary of the invention

[0007] The object of the present invention is to provide a MIM capacitor and a method for manufacturing the same, which can obtain a larger capacitance value while being beneficial to reducing the chip area and thickness and lowering the production cost.

[0008] To achieve the above object, the present invention provides a MIM capacitor, comprising: A lower electrode plate, wherein the lower electrode plate and the lower metal interconnection line are formed by using the same metal layer, and the lower electrode plate has a three-dimensional structure pattern composed of a plurality of concave portions and a plurality of convex portions; an insulating dielectric layer conformally covering the surface of the lower electrode plate so as to be convex on the convex portion and concave on the concave portion; An upper electrode plate, covering the insulating dielectric layer, so that the MIM capacitor has a folded structure at the three-dimensional structure pattern; An upper metal interlayer dielectric layer shields the lower electrode plate, the lower metal interconnection line, the insulating dielectric layer and the upper electrode plate, and an upper metal interconnection line is formed on the upper metal interlayer dielectric layer; The lower electrode plate, the lower metal interconnection line and the upper electrode plate are electrically connected to the upper metal interconnection line through conductive vias in the upper metal interlayer dielectric layer.

[0009] Optionally, the lower metal interconnect line and the lower electrode are formed on a lower metal interlayer dielectric layer, and the recessed portion of the three-dimensional structural pattern includes at least one of a first recess and a second recess, wherein the first recess exposes the top surface of the lower metal interlayer dielectric layer, and the second recess does not expose the top surface of the lower metal interlayer dielectric layer.

[0010] Optionally, the upper electrode plate is recessed at each of the recessed portions, or the upper electrode plate fills at least one recessed portion.

[0011] Optionally, the protrusion is selected from at least one of a strip-shaped protrusion, a polygonal column-shaped protrusion, a cylindrical protrusion, a prism-shaped protrusion, a truncated cone-shaped protrusion, and a spherical cone-shaped protrusion.

[0012] Optionally, the three-dimensional structural pattern includes at least one of a mesh structural pattern, a honeycomb structural pattern, a parallel line structural pattern and a ring structural pattern.

[0013] Optionally, a sidewall of at least one protrusion is a patterned sidewall for increasing a surface area, and the insulating dielectric layer conformally covers the patterned sidewall.

[0014] Optionally, the patterned sidewall includes at least one of a multi-step sidewall and a corrugated sidewall.

[0015] Optionally, the material of the lower electrode plate includes copper or aluminum, and / or the material of the upper electrode plate includes at least one of titanium, titanium nitride, tantalum and tantalum nitride.

[0016] Based on the same inventive concept, the present invention also provides a method for manufacturing a MIM capacitor, comprising the following steps: Providing a substrate having a lower metal interlayer dielectric layer, and depositing a lower metal interconnect layer on the lower metal interlayer dielectric layer and the exposed surface of the substrate; Photolithography and etching are performed on the lower metal interconnection layer to form a lower metal interconnection line and a lower electrode plate of the MIM capacitor, wherein the lower electrode plate has a three-dimensional structure pattern composed of a plurality of concave portions and a plurality of convex portions; Conformally depositing an insulating dielectric layer on the lower metal interconnection line, the lower electrode plate and the exposed substrate surface, wherein the insulating dielectric layer is raised on the raised portion and is recessed on the recessed portion; Depositing an upper plate material layer on the insulating dielectric layer, etching the upper plate material layer and the insulating dielectric layer to form an upper plate and removing the insulating dielectric layer exposed by the upper plate; Depositing an upper metal interlayer dielectric layer to shield the lower electrode plate, the lower metal interconnection line, the insulating dielectric layer and the upper electrode plate; Forming an upper metal interconnection line located on the upper metal interlayer dielectric layer and a conductive via located in the upper metal interlayer dielectric layer by a single damascene process or a dual damascene process; The lower electrode plate, the lower metal interconnection line and the upper electrode plate are electrically connected to the upper metal interconnection line through conductive vias in the upper metal interlayer dielectric layer.

[0017] Optionally, the step of performing photolithography and etching on the lower metal interconnect layer includes: Coating a photoresist layer on the lower metal interconnect layer; The photoresist layer is exposed by using a mask in which each light-transmitting area is a fully light-transmitting area or a half-tone mask, wherein the light-transmitting area of ​​the half-tone mask corresponding to at least one of the recessed portions is a semi-light-transmitting area, and the remaining light-transmitting areas are fully light-transmitting areas; developing the exposed photoresist layer to form a patterned photoresist layer; Using the patterned photoresist layer as a mask, etching the lower metal interconnection layer to form the lower metal interconnection lines and the lower electrode plate, and the gaps between adjacent lower metal interconnection lines expose the top surface of the lower metal interlayer dielectric layer; Wherein, when a photomask in which each light-transmitting area is a full light-transmitting area is used, each of the recessed portions in the lower electrode plate exposes the top surface of the lower metal interlayer dielectric layer; When a half-tone mask is used, the recessed portion in the lower electrode plate corresponding to the semi-transparent area does not expose the top surface of the lower metal interlayer dielectric layer.

[0018] Optionally, after forming the lower electrode plate and before depositing the insulating dielectric layer, it also includes: patterning the side wall of at least one of the protrusions in the lower electrode plate to form a patterned side wall for increasing the surface area; wherein the insulating dielectric layer conformally covers the patterned side wall.

[0019] Optionally, the step of patterning the side wall of at least one of the protrusions in the lower electrode plate comprises: (a) forming a patterned mask layer to expose the sidewall and a portion of the top of the corresponding protrusion of the lower electrode plate; (b) under the mask of the patterned mask layer, etching the lower electrode plate to form a step on the side wall of the corresponding protrusion; (c) expanding the opening of the patterned mask layer; (d) Jump to step (b) and repeat the process until the side wall of the protrusion has the desired multi-step stepped side wall.

[0020] Compared with the prior art, the technical solution of the present invention has at least one of the following beneficial effects: 1. The lower plate of the MIM capacitor and the lower metal interconnection line are formed by the same metal layer, which is beneficial to reduce the thickness of the chip.

[0021] 2. By utilizing the several recessed portions and several raised portions in the three-dimensional structure pattern of the lower electrode, the MIM capacitor is made into a folded structure at the three-dimensional structure pattern. Compared with the conventional planar MIM capacitor structure, under the condition of the same total capacitance value, the area of ​​the MIM capacitor can be greatly reduced, thereby reducing the area of ​​the entire chip and achieving a higher cost performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Those skilled in the art will appreciate that the accompanying drawings are provided for a better understanding of the present invention and do not constitute any limitation on the scope of the present invention. Figure 1 and Figure 2Schematic diagrams of two exemplary cross-sectional structures of existing MIM capacitors.

[0023] Figures 3 to 6 Schematic diagrams showing four cross-sectional structures of a MIM capacitor according to an embodiment of the present invention.

[0024] Figures 7 to 10 Schematic diagram of four examples of three-dimensional structure patterns of the bottom plate of a MIM capacitor according to an embodiment of the present invention.

[0025] Fig.11 Schematic diagram of an example of a sidewall surface of a three-dimensional structure pattern of a lower plate of a MIM capacitor according to an embodiment of the present invention.

[0026] Fig.12 FIG. 4 is a schematic flow chart of a method for manufacturing a MIM capacitor according to an embodiment of the present invention.

[0027] Figures 13 to 15 1 and 2 are three exemplary device structure cross sections in a method for manufacturing a MIM capacitor according to an embodiment of the present invention. DETAILED DESCRIPTION

[0028] In the following description, a large number of specific details are given in order to provide a more thorough understanding of the present invention. However, it is obvious to those skilled in the art that the present invention can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present invention, some technical features known in the art are not described. It should be understood that the present invention can be implemented in different forms and should not be interpreted as being limited to the embodiments proposed here. On the contrary, providing these embodiments will make the disclosure thorough and complete, and the scope of the present invention will be fully conveyed to those skilled in the art. The same reference numerals represent the same elements from beginning to end. It should be understood that when an element is referred to as "connected to", "coupled" other elements, it can be directly connected to other elements, or there can be intervening elements. On the contrary, when an element is referred to as "directly connected to" other elements, there is no intervening element. When used here, the singular forms of "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates another way. It should also be understood that the term "comprising" is used to identify the presence of features, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, steps, operations, elements, components and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0029] The technical solution proposed by the present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer according to the following description. It should be noted that the accompanying drawings are all in a very simplified form and are not in precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0030] Please refer to Figures 3 to 6 , Figures 7 to 10 as well as Fig.11 An embodiment of the present invention provides a MIM capacitor, which includes a lower plate, an insulating dielectric layer 103, an upper plate 104 and an upper metal interlayer dielectric layer 105.

[0031] Among them, the lower electrode plate and the lower metal interconnection line 101 are formed by the same metal layer (or "upper metal interconnection layer") Metal_n-1. The lower electrode plate has a three-dimensional structural pattern composed of a plurality of recessed portions 102b and a plurality of raised portions 102a. The insulating dielectric layer 103 conformally covers the surface of the lower electrode plate so as to be raised on the raised portions 102a and recessed on the recessed portions 102b. The upper electrode plate 104 covers the insulating dielectric layer 103, so that the MIM capacitor has a folded structure at the three-dimensional structural pattern of the lower electrode plate. The upper metal interlayer dielectric layer 105 shields the lower electrode plate, the lower metal interconnection line 101, the insulating dielectric layer 103 and the upper electrode plate 104.

[0032] The lower plate may include any conductive material, including but not limited to copper, aluminum or copper-aluminum alloy. The upper plate 104 may include any conductive material, including but not limited to at least one of titanium, titanium nitride, tantalum and tantalum nitride. The insulating dielectric layer 103 may include any dielectric material, including but not limited to at least one of silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, tantalum pentoxide, aluminum oxide, titanium oxide, hafnium oxide, lanthanum oxide and strontium titanate. The upper metal interlayer dielectric layer 105 may include any dielectric material, including but not limited to low-k dielectric material (dielectric constant k is lower than silicon oxide), silicon oxide, silicon nitride or silicon oxynitride.

[0033] In this embodiment, the protrusion 102a can be of any suitable shape, for example, a strip protrusion (such as Figure 7-Figure 8 As shown), polygonal columnar protrusions (such as Fig. 9 As shown, it can be a triangular prism, a quadrangular prism, a hexagonal prism, etc. It can be a solid cylinder or a polygonal ring-shaped cylinder), a cylindrical protrusion (such as Fig.10 As shown, it can be a solid cylinder, or a circular cylinder), a prism-shaped protrusion (not shown), a truncated cone-shaped protrusion (not shown), a spherical table-shaped protrusion (not shown), etc. For example, please refer to Figure 7 and Figure 8, all the protrusions 102a in the lower electrode plate are of a single shape of strip protrusions. For another example, please refer to Fig. 9 All the protrusions 102a in the lower plate are in a single shape of a hexagonal column. For another example, some of the protrusions 102a in the lower plate are annular columns, and some of the protrusions 102a are strip columns, and the strip columns connect adjacent annular columns.

[0034] The shape, size, position and other parameters of each recessed portion 102b are restricted by the surrounding raised portions 102a. Figures 3 to 5 , the line width d of the recessed portion 102b is larger, that is, the spacing between adjacent protruding portions 102a is larger, and after the insulating dielectric layer 103 and the upper electrode plate 104 are conformally covered, the recessed portion 102b is not filled, and the upper electrode plate 107 is recessed at each recessed portion 102b, thereby forming a recessed gap, which is filled by the upper metal interlayer dielectric layer 105. In another example, please refer to Figure 6 , at least one recessed portion 102b has a smaller line width d, that is, the spacing between the corresponding adjacent raised portions 102a is smaller. After the insulating dielectric layer 103 is conformally covered, the upper electrode plate 104 fills the recessed portion 102b with a smaller line width d, thereby utilizing the larger three-dimensional structure pattern density of the lower electrode plate to further increase the capacitance value of the MIM capacitor.

[0035] In addition, the depth of each recessed portion 102b is affected by etching and other processes, and may penetrate the lower electrode plate (or the lower metal layer Metal_n-1), or may not penetrate the lower electrode plate (or the lower metal layer Metal_n-1). Figure 3 and Figure 6 As shown, each recessed portion 102b (ie, the first recessed portion) in the lower electrode plate penetrates the lower electrode plate (or penetrates the lower metal layer Metal_n-1). In another example, please refer to Figure 4 , each recessed portion 102b (i.e., the second recessed portion) in the lower electrode plate does not penetrate the lower electrode plate (or penetrate the lower metal layer Metal_n-1). In another example, a portion of the recessed portion in the lower electrode plate is the first recessed portion 102b1, and another portion is the second recessed portion 102b2. The first recessed portion 102b1 penetrates the lower electrode plate (or penetrates the lower metal layer Metal_n-1), thereby exposing the top surface of the lower metal interlayer dielectric layer IDL_n-1; the second recessed portion 102b2 does not penetrate the lower electrode plate (or penetrates the lower metal layer Metal_n-1), thereby not exposing the top surface of the lower metal interlayer dielectric layer IDL_n-1.

[0036] It should be understood that, in this embodiment, the three-dimensional structural pattern of the lower electrode plate is any suitable pattern composed of all the protruding portions 102a and all the recessed portions 102b, and the present invention does not make any specific limitation on this.

[0037] For example, the three-dimensional structure pattern is a mesh structure pattern (such as Figure 8 As shown), honeycomb structure pattern (as Fig. 9 As shown), parallel linear structure patterns (such as Figure 7 as shown) or a ring-shaped structure pattern (as shown Fig.10 As shown); For another example, the three-dimensional structure diagram example is a mesh structure pattern (such as Figure 8 As shown), honeycomb structure pattern (as Fig. 9 As shown), parallel linear structure patterns (such as Figure 7 as shown) and the ring-shaped structure pattern (as Fig.10 A combination of two or more patterns such as shown).

[0038] The side walls of each protrusion 102a in the lower plate may be vertical side walls, such as Figures 3 to 6 As shown, it can also be a smooth inclined side wall, such as the side wall of a prism-shaped protrusion, a truncated cone-shaped protrusion, or a spherical cone-shaped protrusion.

[0039] Preferably, in order to further increase the capacitance value of the MIM capacitor, the sidewall of at least one protrusion 102a of the lower plate is a patterned sidewall for increasing the surface area, and the insulating dielectric layer 103 can conformally cover the patterned sidewall. The patterned sidewall is, for example, a multi-stepped sidewall, such as Fig.11 As shown, it can also be a corrugated side wall (not shown), or a combination of two or more side walls such as a multi-step stepped side wall, a smooth side wall, and a corrugated side wall.

[0040] In this embodiment, the MIM capacitor is formed based on the lower metal layer Metal_n-1 of the multi-layer interconnected metal structure, and is formed below the upper metal layer Metal_n used to form the upper metal interconnection line 107. Therefore, an upper metal interconnection line 107 is formed on the upper metal interlayer dielectric layer (IDL_n) 105 of the MIM capacitor, and the upper metal interconnection line 107 is formed by etching the upper metal interconnection layer Metal_n. The lower plate, the lower metal interconnection line 101 and the upper plate 104 are electrically connected to the upper metal interconnection line 107 through the conductive through hole 106 in the upper metal interlayer dielectric layer 105.

[0041] Optionally, the lower metal interconnection line 101 and the lower electrode plate are formed on the lower metal interlayer dielectric layer IDL_n_1, and below the lower metal interlayer dielectric layer IDL_n_1 is the metal interconnection layer Metal_n-2.

[0042] Based on the same invention concept, please refer to Fig.12 An embodiment of the present invention further provides a method for manufacturing a MIM capacitor, comprising the following steps: S1, providing a substrate having a lower metal interlayer dielectric layer, and depositing a lower metal interconnect layer on the lower metal interlayer dielectric layer and the exposed surface of the substrate; S2, performing photolithography and etching on the lower metal interconnection layer to form a lower metal interconnection line and a lower electrode plate of the MIM capacitor, wherein the lower electrode plate has a three-dimensional structure pattern composed of a plurality of concave portions and a plurality of convex portions; S3, conformally depositing an insulating dielectric layer on the lower metal interconnection line, the lower electrode plate and the exposed substrate surface, wherein the insulating dielectric layer is convex on the convex part and concave on the concave part; S4, depositing an upper plate material layer on the insulating dielectric layer, etching the upper plate material layer and the insulating dielectric layer to form an upper plate and removing the insulating dielectric layer exposed by the upper plate; S5, depositing an upper metal interlayer dielectric layer to shield the lower electrode plate, the lower metal interconnection line, the insulating dielectric layer and the upper electrode plate; S6, forming an upper metal interconnection line located on the upper metal interlayer dielectric layer and a conductive via located in the upper metal interlayer dielectric layer by a single damascene process or a dual damascene process; The lower electrode plate, the lower metal interconnection line and the upper electrode plate are electrically connected to the upper metal interconnection line through conductive vias in the upper metal interlayer dielectric layer.

[0043] The manufacturing process of MIM capacitors starts with making semiconductor devices on the surface of semiconductors (or epitaxial semiconductors on other materials) and metal interconnect structures (including through holes and metal interconnect lines) under the MIM capacitors.

[0044] Therefore, please refer to Fig.13 (A) or Fig.14In (A), in step S1, first, the metal interconnection structure (including through holes and metal interconnection lines) of the CMOS device and the like and the bottom of the MIM capacitor is prepared according to the conventional CMOS process steps to provide a substrate 100, wherein the substrate 100 includes a lower metal interlayer dielectric layer IDL_n-1 and a metal layer Metal_n-2 located below the lower metal interlayer dielectric layer IDL_n-1; then, the lower metal interconnection layer Metal_n-1 is deposited on the lower metal interlayer dielectric layer IDL_n-1 and the exposed substrate surface thereof by any suitable deposition process such as chemical vapor deposition (CVD) or organic metal oxide chemical vapor deposition (MOCVD) or atomic layer chemical vapor deposition (ALCVD).

[0045] In one example, in step S2, please refer to Fig.13 In (A) and (B), first, a photoresist layer 200 is coated on the lower metal interconnection layer Metal_n-1; then, a mask 300 is used in which each light-transmitting area 300a is a fully light-transmitting area to expose the photoresist layer, and then the exposed photoresist layer is developed to form a patterned photoresist layer 200, in which each opening of the patterned photoresist layer 200 is completely opened (i.e., penetrates the photoresist layer) to expose the top surface of the lower metal interconnection layer Metal_n-1; then, The patterned photoresist layer 200 is used as a mask to etch the lower metal interconnection layer Metal_n-1 to form lower metal interconnection lines 101 and a lower electrode plate, and the gaps between adjacent lower metal interconnection lines 101 expose the top surface of the lower metal interlayer dielectric layer Metal_n-1, and the lower electrode plate has a three-dimensional structural pattern composed of a plurality of recessed portions 102b and a plurality of raised portions 102a, and each recessed portion 102b exposes the top surface of the lower metal interlayer dielectric layer Metal_n-1.

[0046] In another example, in step S2, please refer to Fig.14In (A) and (B), first, a photoresist layer 200 is coated on the lower metal interconnection layer Metal_n-1; then, a half-tone mask 300 is used to expose the photoresist layer, wherein the light-transmitting area 300b of the half-tone mask 300 corresponding to the recessed portion 102b2 of the lower electrode plate is a semi-light-transmitting area, and the remaining light-transmitting areas 300a are fully light-transmitting areas; then, the exposed photoresist layer is developed to form a patterned photoresist layer 200, wherein the opening 200a of the patterned photoresist layer 200 corresponding to the recessed portion 102b2 of the lower electrode plate is not fully opened (i.e., does not penetrate the photoresist layer) and does not expose the top surface of the lower metal interconnection layer Metal_n-1, and the remaining openings are fully opened (i.e., penetrate the photoresist layer) to expose the top surface of the lower metal interconnection layer Metal_n-1; then, the patterned photoresist layer 200 is used to form a patterned photoresist layer 200. The photoresist layer 200 is used as a mask to etch the lower metal interconnection layer Metal_n-1 to form a lower metal interconnection line 101 and a lower electrode plate, and the gaps between adjacent lower metal interconnection lines 101 expose the top surface of the lower metal interlayer dielectric layer Metal_n-1, and the lower electrode plate has a three-dimensional structural pattern composed of a plurality of first recesses 102b1, a second recess 102b2 and a plurality of protrusions 102a, and each first recess 102b1 penetrates the lower metal interconnection layer Metal_n-1 and exposes the top surface of the lower metal interlayer dielectric layer Metal_n-1, and each second recess 102b2 is formed corresponding to the opening 200a without penetrating the lower metal interconnection layer Metal_n-1, thereby not exposing the top surface of the lower metal interlayer dielectric layer Metal_n-1.

[0047] In step S3, please refer to Fig.13 (C) or Fig.14 In (C), an insulating dielectric layer 103 is conformally deposited on the lower metal interconnect 101, the lower electrode and the exposed substrate surface by any suitable deposition process such as chemical vapor deposition (CVD) or atomic layer chemical vapor deposition (ALCVD), and the insulating dielectric layer 103 is raised on the raised portion 102a and recessed on the recessed portion 102b.

[0048] In step S4, please refer to Fig.13 (C) or Fig.14 In (C), first, an upper plate material layer is deposited on the insulating dielectric layer 103 by any suitable deposition process such as chemical vapor deposition (CVD) or organic metal oxide chemical vapor deposition (MOCVD) or atomic layer chemical vapor deposition (ALCVD); then, the upper plate material layer and the insulating dielectric layer are etched by a process combining photolithography and etching to form an upper plate 104 and remove the insulating dielectric layer 103 exposed by the upper plate 104.

[0049] In step S5, please refer to Fig.13 (D) or Fig.14 In (D), an upper metal interlayer dielectric layer 105 is deposited by any suitable deposition process such as chemical vapor deposition (CVD) or atomic layer chemical vapor deposition (ALCVD) to mask the lower electrode plate, the lower metal interconnect line 107, the insulating dielectric layer 105 and the upper electrode plate 107.

[0050] In step S6, please refer to Fig.13 (D) or Fig.14 In (D), an upper metal interconnection line 107 located on the upper metal interlayer dielectric layer 105 and a conductive via 106 located in the upper metal interlayer dielectric layer 105 are formed by a single damascene process or a dual damascene process.

[0051] Optionally, after completing step S3 and before executing step S4, after forming the lower electrode plate and before depositing the insulating dielectric layer 103, it also includes: using any suitable process to pattern the side wall of at least one protrusion 102a in the lower electrode plate to form a patterned side wall for increasing the surface area; wherein the insulating dielectric layer 103 conformally covers the patterned side wall, thereby utilizing the patterned side wall to further increase the equivalent area of ​​the MIM capacitor.

[0052] In an example, see Fig.15 After completing step S3 and before executing step S4, after forming the lower electrode plate and before depositing the insulating dielectric layer 103, the step of patterning the sidewall of at least one protrusion 102a in the lower electrode plate includes: (a) Please refer to Fig.15 (A) and (B) in the figure, a patterned mask layer 201 is formed by any suitable process such as photolithography or mask material deposition, photolithography combined with etching, etc., so as to expose the side wall and part of the top of the corresponding protrusion 102a of the lower electrode plate. The patterned mask layer 201 can be any suitable material such as photoresist and silicon nitride; (b) Please refer to Fig.15 In (B), under the masking of the patterned mask layer 201, the lower electrode plate is etched to form a step on the side wall of the corresponding protrusion 102a; (c) Please refer to Fig.15 In (B) and (C), the opening of the patterned mask layer 201 is expanded so that the line width of the opening is expanded from w1 to w2; (d) Please refer to Fig.15(C) and (D) in the above, and then jump to step (b), and etch the lower electrode plate under the mask of the outwardly expanded patterned mask layer 201 to form a new step on the side wall of the corresponding raised portion 102a; the above steps (b) to (d) are repeated until the side wall of the raised portion 102a has the desired multi-step stepped side wall.

[0053] In summary, the MIM capacitor and the manufacturing method thereof of the present invention, wherein the lower electrode plate and the lower metal interconnection line are formed by the same metal layer, is conducive to reducing the thickness of the chip, and can also utilize the several recessed portions and the several raised portions in the three-dimensional structure pattern of the lower electrode plate, so that the MIM capacitor is in a folded structure at the three-dimensional structure pattern. Therefore, compared with the conventional planar MIM capacitor structure, under the condition of the same total capacitance value, the area of ​​the MIM capacitor can be greatly reduced, thereby reducing the area of ​​the entire chip and achieving a higher cost performance.

[0054] The above description is only a description of the preferred embodiment of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the technical solution of the present invention.

Claims

1. A MIM capacitor, It is characterized in that include: A lower electrode plate, wherein the lower electrode plate and the lower metal interconnection line are formed by using the same metal layer, and the lower electrode plate has a three-dimensional structure pattern composed of a plurality of concave portions and a plurality of convex portions; an insulating dielectric layer conformally covering the surface of the lower electrode plate so as to be convex on the convex portion and concave on the concave portion; An upper electrode plate, covering the insulating dielectric layer, so that the MIM capacitor has a folded structure at the three-dimensional structure pattern; An upper metal interlayer dielectric layer shields the lower electrode plate, the lower metal interconnection line, the insulating dielectric layer and the upper electrode plate, and an upper metal interconnection line is formed on the upper metal interlayer dielectric layer; The lower electrode plate, the lower metal interconnection line and the upper electrode plate are electrically connected to the upper metal interconnection line through conductive vias in the upper metal interlayer dielectric layer.

2. The MIM capacitor according to claim 1, It is characterized in that The lower metal interconnection line and the lower electrode are formed on the lower metal interlayer dielectric layer, and the recessed portion of the three-dimensional structure pattern includes at least one of a first recess and a second recess, the first recess exposes the top surface of the lower metal interlayer dielectric layer, and the second recess does not expose the top surface of the lower metal interlayer dielectric layer.

3. The MIM capacitor according to claim 1, It is characterized in that The upper electrode plate is recessed at each of the recessed portions, or the upper electrode plate fills up at least one recessed portion.

4. The MIM capacitor according to claim 1, It is characterized in that The protrusion is selected from at least one of a strip-shaped protrusion, a polygonal column-shaped protrusion, a cylindrical protrusion, a prism-shaped protrusion, a truncated cone-shaped protrusion, and a spherical cone-shaped protrusion.

5. The MIM capacitor according to claim 4, It is characterized in that The sidewall and / or top surface of at least one protrusion is a patterned surface for increasing the surface area, and the insulating dielectric layer conformally covers the patterned surface.

6. The MIM capacitor according to claim 5, It is characterized in that The patterned surface includes at least one of a multi-step surface, a corrugated surface and an arc surface.

7. The MIM capacitor according to any one of claims 1 to 6, It is characterized in that The material of the lower electrode plate includes copper or aluminum; and / or the material of the upper electrode plate includes at least one of titanium, titanium nitride, tantalum and tantalum nitride.

8. A method for manufacturing a MIM capacitor according to any one of claims 1 to 7, It is characterized in that The following steps are involved: Providing a substrate having a lower metal interlayer dielectric layer, and depositing a lower metal interconnect layer on the lower metal interlayer dielectric layer and the exposed surface of the substrate; Photolithography and etching are performed on the lower metal interconnection layer to form a lower metal interconnection line and a lower electrode plate of the MIM capacitor, wherein the lower electrode plate has a three-dimensional structure pattern composed of a plurality of concave portions and a plurality of convex portions; Conformally depositing an insulating dielectric layer on the lower metal interconnection line, the lower electrode plate and the exposed substrate surface, wherein the insulating dielectric layer is raised on the raised portion and is recessed on the recessed portion; Depositing an upper plate material layer on the insulating dielectric layer, etching the upper plate material layer and the insulating dielectric layer to form an upper plate and removing the insulating dielectric layer exposed by the upper plate; Depositing an upper metal interlayer dielectric layer to shield the lower electrode plate, the lower metal interconnection line, the insulating dielectric layer and the upper electrode plate; Forming an upper metal interconnection line located on the upper metal interlayer dielectric layer and a conductive via located in the upper metal interlayer dielectric layer by a single damascene process or a dual damascene process; The lower electrode plate, the lower metal interconnection line and the upper electrode plate are electrically connected to the upper metal interconnection line through conductive vias in the upper metal interlayer dielectric layer.

9. The manufacturing method according to claim 8, It is characterized in that The steps of photolithography and etching the lower metal interconnect layer include: Coating a photoresist layer on the lower metal interconnect layer; The photoresist layer is exposed by using a mask in which each light-transmitting area is a fully light-transmitting area or a half-tone mask, wherein the light-transmitting area of ​​the half-tone mask corresponding to at least one of the recessed portions is a semi-light-transmitting area, and the remaining light-transmitting areas are fully light-transmitting areas; developing the exposed photoresist layer to form a patterned photoresist layer; Using the patterned photoresist layer as a mask, etching the lower metal interconnection layer to form the lower metal interconnection lines and the lower electrode plate, and the gaps between adjacent lower metal interconnection lines expose the top surface of the lower metal interlayer dielectric layer; Wherein, when a photomask in which each light-transmitting area is a full light-transmitting area is used, each of the recessed portions in the lower electrode plate exposes the top surface of the lower metal interlayer dielectric layer; When a half-tone mask is used, the recessed portion in the lower electrode plate corresponding to the semi-transparent area does not expose the top surface of the lower metal interlayer dielectric layer.

10. The manufacturing method according to claim 8, It is characterized in that After forming the lower electrode plate and before depositing the insulating dielectric layer, it also includes: patterning the side wall and / or top surface of at least one of the protrusions in the lower electrode plate to form a patterned surface for increasing the surface area; wherein the insulating dielectric layer conformally covers the patterned surface.

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